Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
32	Anteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi, Said Hamdioui	Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Yogesh Kumar, S. Sivakumar, John Jose	ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker	Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Dimitrios Samaras, Andreas Tsimpos, Alkis A. Hatzopoulos	A novel wide frequency range 65nm CMOS VCO.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Alexander Fusco, Md Sahil Hassan, Joshua Mack, Ali Akoglu	A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	U. Esteban Eraso, Carlos Sánchez-Azqueta, Concepción Aldea, Santiago Celma	A CMOS 4-bit Digitally Programmable Phase Shifter for the K-band.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Konstantinos Falis, Andreas Tsiougkos, Vasilis F. Pavlidis	Practical Day-Ahead Power Prediction of Solar Energy-Harvesting for IoT Systems.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Evangelos Vlachos, Kostas Blekos	Quantum Computing-Assisted Channel Estimation for Massive MIMO mmWave Systems.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Ashwin Bhat, Adou Sangbone Assoa, Arijit Raychowdhury	Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant	PA-PUF: A Novel Priority Arbiter PUF.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Rolf Drechsler, Alireza Mahzoon	Preserving Design Hierarchy Information for Polynomial Formal Verification.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Mahdi Zahedi, Taha Shahroodi, Geert Custers, Abhairaj Singh, Stephan Wong, Said Hamdioui	System Design for Computation-in-Memory: From Primitive to Complex Functions.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	George S. Vergos, Vasiliki Gogolou, C. Panagiotopoulou, A. Avgoustidis, Thomas Noulis, Kostas Siozios, Stilianos Siskos	Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	P. Esmaeili, Timothy Martin, Shawki Areibi, Gary Gréwal	Guiding FPGA Detailed Placement via Reinforcement Learning.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Alexander El-Kady, Apostolos P. Fournaris, Evangelos Haleplidis, Vassilis Paliouras	High-Level Synthesis design approach for Number-Theoretic Multiplier.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Chirag Sudarshan, Taha Soliman, Thomas Kämpfe, Christian Weis, Norbert Wehn	FeFET versus DRAM based PIM Architectures: A Comparative Study.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Stian Gerlach Sørensen, Christian Bartsch 0001, Dominik Stoffel, Wolfgang Kunz	Generation of Formal CPU Profiles for Embedded Systems.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Konstantinos D. Katsanos, George C. Alexandropoulos	Secrecy Spectral Efficiency Optimization in RIS-Enabled MIMO Communication Systems.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Carlos Fernandez, Ioannis Vourkas	On the Design and Development of a ReRAM-based Computational Memory Prototype.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Shubham Kumar, Swetaki Chatterjee, Simon Thomann, Paul R. Genssler, Yogesh Singh Chauhan, Hussam Amrouch	Cross-layer FeFET Reliability Modeling for Robust Hyperdimensional Computing.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Gourav Datta, Souvik Kundu 0002, Zihan Yin, Joe Mathai, Zeyu Liu 0003, Zixu Wang, Mulin Tian, Shunlin Lu, Ravi Teja Lakkireddy, Andrew G. Schmidt, Wael Abd-Almageed, Ajey P. Jacob, Akhilesh R. Jaiswal, Peter A. Beerel	P2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Akshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose	RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Asmae El Arrassi, Anteneh Gebregiorgis, Anass El Haddadi, Said Hamdioui	Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM).	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Georgios Kottaras, Theodoros Sarris, Athanasios M. Psomoulis, Ilias Ioakeimidis, Angelos Papathanasiou, David Pitchford, Ingmar Sandberg	A low-power, radiation-hardened Single Event Effect rate detection System on a Chip for Real Time Monitoring of Single Event Effects on Low Earth Orbit satellites.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Vasileios Leon, George Lentaris, Dimitrios Soudris, Simon Vellas, Mathieu Bernou	Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Artem Glukhov, Nicola Lepri, Valerio Milo, Andrea Baroni, Cristian Zambelli, Piero Olivo, Eduardo Pérez, Christian Wenger, Daniele Ielmini	End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros	A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Imlijungla Longchar, Palash Das, Hemangee K. Kapoor	ZaLoBI: Zero avoiding Load Balanced Inference accelerator.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	J. Fernández-Aragón, Guillermo Díez-Señorans, Miguel Garcia-Bosque, Santiago Celma	Design and characterisation of a Physically Unclonable Function on FPGA using second-order compensated measurement.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon	An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang	LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	Logic Locking of Finite-State Machines Using Transition Obfuscation.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Pedro Aquino Silva, Mateus Grellert, Cristina Meinhardt	Exploring Approximate Comparator Circuits on Power Efficient Design of Decision Trees.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Georgios Flamis, Stavros Kalapothas, Paris Kitsos	FPGA-SoC Deployment of Complex Deep Neural Network for Magnitude and Phase Computations in Denoising of Speech Signal.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez 0004, Milos Krstic, Eckhard Grass	High-Speed SC Decoder for Polar Codes achieving 1.7 Tb/s in 28 nm CMOS.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Vasileios Manouras, Ioannis Papananos	A Wideband High-Gain Power Amplifier Operating in the D Band.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Kritanta Saha, Pritha Banerjee 0001, Susmita Sur-Kolay	Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta 0001, Rolf Drechsler	Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Rupali Hongekar, Ankita Gupta, Jayakrishna Guddeti, Meghashyam Ashwathnarayan	Enabling Automotive Electrification on Heterogeneous Automotive Microcontroller using Virtual System Modelling.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat	Power Analysis Attack on Locking SIB based IJTAG Achitecture.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nikolaos Kefalas, George Theodoridis	An FPGA implementation of the VESA Display Stream Compression decoder.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nikolaos Vasileiadis, Alexandros Mavropoulis, Panagiotis Loukas, Pascal Normand, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis	Substrate Effect on Low-frequency Noise of synaptic RRAM devices.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Renjie Chen, Aaron Stillmaker, Bevan M. Baas	Architecture and 28 nm CMOS Design of a 1886 MBin/sec Context-Adaptive Binary Arithmetic Coder (CABAC) Encoder.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán	A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nikolaos Georgiou, Panayiotis Kolios	Accurate real-time UAV flight-mode classification.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas	Efficient Dynamic Logic Magnitude Comparators.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Brent Bohnenstiehl, Aaron Stillmaker, Timothy Andreas, Bevan M. Baas	A Low-Overhead Method for the Accurate Estimation of the Maximum Operating Clock Frequency.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Carlos Fernandez, Ioannis Vourkas	Reliability-Aware Ratioed Logic Operations for Energy-Efficient Computational ReRAM.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Chun-Jen Tsai, Yi-De Lee	Embedded TCP/IP Controller for a RISC-V SoC.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Vasileios Leon, Elissaios-Alexios Papatheofanous, George Lentaris, Charalampos Bezaitis, Nikolaos Mastorakis, Georgios Bampilis, Dionysios I. Reisis, Dimitrios Soudris	Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nahla A. El-Araby, David Frismuth, Nilson Neves Filho, Axel Jantsch	Run Time Power and Accuracy Management with Approximate Circuits.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Jorge Marqués-García, Alberto Arcusa-Puente, Antonio D. Martínez-Pérez, Francisco Aznar	Modeling frequency response of gm-boosted inductorless Common-Gate LNA.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nikolaos Blias, Iordanis Lilitsis, Stavros Simoglou, Evangelos Bakas, Christos P. Sotiriou	Investigation on Performance, Power, Area Trade-Offs using Deterministic and Monte-Carlo Process Variation Aware Synthesis Flows.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Johannes W. Farias, Diego V. Cirilo do Nascimento, Tiago Barros, Samuel Xavier de Souza	Speculative guardband: exploiting critical-delay variations across cached instructions.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Panagiotis Gkoutis, Georgios Konidas, Grigorios Kalivas	30 GHz Front-End with Adaptively Biased PA and Current Steering LNA for Phased Array Systems.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Jonas Gava, Ricardo Reis 0001, Luciano Ost	Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Pedro Aquino Silva, Mateus Grellert, Cristina Meinhardt	Approximation Workflow for Energy-Efficient Comparators in Decision Tree Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Sheiny Fabre Almeida, José Luís Güntzel, Laleh Behjat, Cristina Meinhardt	Routability-Driven Detailed Placement Using Reinforcement Learning.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Samuele Germiniani, Graziano Pravadelli	Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Anastasios Michailidis, Thomas Noulis, Kostas Siozios	Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Theo Soriano, David Novo, Guillaume Prenat, Gregory di Pendina, Pascal Benoit	MemCork: Exploration of Hybrid Memory Architectures for Intermittent Computing at the Edge.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Kyriaki Tsantikidou, Nicolas Sklavos 0001	Flexible Security and Privacy, System Architecture for IoT, in Healthcare.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Muhammad Awais 0009, Marco Platzner	Automated Framework for Fast Synthesis of Approximate Hardware Accelerators.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh	A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang	SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nathan Laubeuf	Analog Compute in Memory and Breaking Digital Number Representations.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Rupesh Raj Karn, Ibrahim Abe M. Elfadel	Confidential Inference in Decision Trees: FPGA Design and Implementation.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Elissaios-Alexios Papatheofanous, Ph. Tziolos, V. Kalekis, Tzouma Amrou, George E. Konstantoulakis, Georgios Venitourakis, Dionysios I. Reisis	SoC FPGA Acceleration for Semantic Segmentation of Clouds in Satellite Images.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Salvatore Levantino	Frequency Synthesizers for 5G Applications.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Antonis M. Paschalis, Panagiotis Chatziantoniou, Dimitris Theodoropoulos, Antonis Tsigkanos, Nektarios Kranitis	High-Performance Hardware Accelerators for Next Generation On-Board Data Processing.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Anu Asokan	A Signal-Integrity Aware ATPG Flow to Generate High-Quality Patterns for Testing System-on-Chip Designs.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Elif Bilge Kavun	A Power Reduction Technique Based on Linear Transformations for Block Ciphers.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Vinicius Zanandrea, Cristina Meinhardt	Exploring Approximate Computing Approaches to Design Power-efficient Multipliers.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Jose Cayo, Ioannis Vourkas, Antonio Rubio 0001	A Circuit-Level SPICE Modeling Strategy for the Simulation of Behavioral Variability in ReRAM.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Christopher Chuvalas, Ranga Vemuri	FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Nikolaos Chatzivangelis, Dimitris Valiantzas, Christos P. Sotiriou, Iordanis Lilitsis	Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Can Aknesil, Elena Dubrova	Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Konstantina Koliogeorgi, Dimitris Mylonakis, Sotirios Xydis, Dimitrios Soudris	High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32	Jonathan Merk, Changhai Lin, Matthias Kamuf	Assessing IMD of a Direct-to-RF Platform.	VLSI-SoC	2022	DBLP DOI BibTeX RDF
32		29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Akashdeep Saha, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty	Design and Analysis of Logic Locking Techniques.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Parya Zolfaghari, Sébastien Le Beux	A Reconfigurable Nanophotonic Architecture based on Phase Change Material.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Durba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra	Formal Analysis of Physically Unclonable Functions.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin	On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Siva Satyendra Sahoo, Akash Kumar 0001	Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler	Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Vikas Rao, Haden Ondricek, Priyank Kalla, Florian Enescu	Algebraic Techniques for Rectification of Finite Field Circuits.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Akshay Balaji, Sneh Saurabh	Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Francesco Daghero, Alessio Burrello, Chen Xie, Luca Benini, Andrea Calimera, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari	Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Qazi Arbab Ahmed	Hardware Trojans in Reconfigurable Computing.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Lilian Bossuet, El Mehdi Benhani	Security Assessment of Heterogeneous SoC-FPGA: On the Practicality of Cache Timing Attacks.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Konstantina Miteloudi, Lukasz Chmielewski, Lejla Batina, Nele Mentens	Evaluating the ROCKY Countermeasure for Side-Channel Leakage.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do	Efficient Implementation of Activation Functions for LSTM accelerators.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Dominik Sisejkovic, Rainer Leupers	Trustworthy Hardware Design with Logic Locking.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	S. Skandha Deepsita, Kuchipudi Divya, Sk. Noor Mahammad	Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Zhao Han, Deyan Wang, Gabriel Rutsch, Bowen Li, Sebastian Siegfried Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Wolfgang Ecker	Aspect-Oriented Design Automation with Model Transformation.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Zhaoyang Cao, Tan-Tan Zhang, Yuan Gao 0011, Wang Ling Goh	Design of Fully Differential Energy-Efficient Inverter-Based Low-Noise Amplifier for Ultrasound Imaging.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Stavros Nousias, Erion-Vasilis M. Pikoulis, Christos Mavrokefalidis, Aris S. Lalos, Konstantinos Moustakas	Accelerating 3D scene analysis for autonomous driving on embedded AI computing platforms.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
32	Luca Mocerino, Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Enrico Macii	AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedded ConvNets.	VLSI-SoC	2021	DBLP DOI BibTeX RDF