Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang 0010, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert |
Spin-electronics based logic fabrics. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Stephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz |
An area-efficient minimum-time FFT schedule using single-ported memory. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the development of diagnostic test programs for VLIW processors. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Yu Zhang, Gong Chen 0002, Qing Dong 0002, Mingyu Li, Shigetoshi Nakatake |
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Sébastien Le Beux, Zhen Li 0046, Christelle Monat, Xavier Letartre, Ian O'Connor |
Reconfigurable photonic switching: Towards all-optical FPGAs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | H. Fatih Ugurdag, Fatih Temizkan, Sezer Gören 0001 |
Generating fast logic circuits for m-select n-port Round Robin Arbitration. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues |
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Amir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Cristina Silvano |
A framework for Compiler Level statistical analysis over customized VLIW architecture. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Vourkas, Dimitrios Stathis 0001, Georgios Ch. Sirakoulis |
Improved read voltage margins with alternative topologies for memristor-based crossbar memories. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Bharath Sudev, Leandro Soares Indrusiak |
PFT - A low overhead predictability enhancement technique for non-preemptive NoCs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers |
Software-programmable digital pre-distortion on the Zynq SoC. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Seogoo Lee, Andreas Gerstlauer |
Fine grain word length optimization for dynamic precision scaling in DSP systems. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Mohsen Hassanpourghadi, Mohammad Sharifkhani |
Step response analysis of third order OpAmps With slew-rate. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Vikas S. Vij, Kenneth S. Stevens |
Automatic addition of reset in asynchronous sequential control circuits. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Giray Kömürcü, Ali Emre Pusane, Günhan Dündar |
Analysis of Ring Oscillator structures to develop a design methodology for RO-PUF circuits. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Filgueras, Eduard Gil, Carlos Álvarez 0001, Daniel Jiménez-González, Xavier Martorell, Jan Langer, Juanjo Noguera |
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Yuan Ren, Tobias G. Noll |
An accurate power estimation model for low-power hierarchical-architecture SRAMs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Sk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri |
New scan-based attack using only the test mode. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören 0001 |
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Artés, José Luis Ayala, Robert Fasthuber, Praveen Raghavan, Francky Catthoor |
Energy impact in the design space exploration of loop buffer schemes in embedded systems. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak |
Gate sizing in the presence of gate switching activity and input vector control. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Hussein Adel, Marie-Minerve Louërat, Marc Sabut |
Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Isil Öz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir, Oguz Tosun |
Examining Thread Vulnerability analysis using fault-injection. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Leandro Nunes, Tiago Reimann, Ricardo Reis 0001 |
GR-PA: A cost pre-allocation model for global routing. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Nicoleta Cucu Laurenciu, Yao Wang 0002, Sorin Dan Cotofana |
A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Arezoo Kamran, Zainalabedin Navabi |
Online periodic test mechanism for homogeneous many-core processors. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Amr M. S. Tosson, Siddharth Garg, Mohab H. Anis |
Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen |
Variation-aware and adaptive-latency accesses for reliable low voltage caches. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Chien-Min Lee, Chi-Kang Chen, Ren-Song Tsay |
A basic-block power annotation approach for fast and accurate embedded software power estimation. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Christopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas |
A framework to accelerate sequential programs on homogeneous multicores. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Kemal Ozanoglu, Selçuk Talay |
Effects of the positive feedback loop in self biased bandgap reference circuits. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Kaushik Triyambaka Mysur, Mihai Pricopi, Thomas Marconi, Tulika Mitra |
Implementation of core coalition on FPGAs. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Ricardo Povoa, Nuno Lourenço 0003, Nuno Horta, Rui Santos-Tavares, João Goes |
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Dong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara |
Thermal-aware test scheduling for NOC-based 3D integrated circuits. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Eric Guthmuller, Ivan Miro Panades, Alain Greiner |
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Sotiris Thomas, Kyprianos Papadimitriou, Apostolos Dollas |
Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGA. |
VLSI-SoC |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Radu David, Paul Bogdan, Radu Marculescu |
Dynamic power management for multicores: Case study using the intel SCC. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hamed Tabkhi, Gunar Schirner |
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Christina Gimmler-Dumont, Christian Brehm, Norbert Wehn |
Reliability study on system memories of an iterative MIMO-BICM system. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg |
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andreas Minwegen, Dominik Auras, Gerd Ascheid |
A multimode decision-directed channel estimation ASIC for MIMO-OFDM. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Qiuling Zhu, Larry T. Pileggi, Franz Franchetti |
Cost-effective smart memory implementation for parallel backprojection in computed tomography. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Bin Wu, Peng Li 0001 |
Load-aware stochastic feedback control for DVFS with tight performance guarantee. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov |
A scalable model based RTL framework zamiaCAD for static analysis. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Kyungsu Kang, Luca Benini, Giovanni De Micheli |
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Abhishek Guar, Hamid Mahmoodi |
Impact of technology scaling on performance of domino logic in nano-scale CMOS. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Victor Frederico Silva, Cantidio de Oliveira Fontes, Flávio Rech Wagner |
The impact of synchronization in message passing while scaling multi-core MPSoC systems. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg |
A physical design study of fabscalar-generated superscalar cores. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andy Motten, Luc Claesen, Yun Pan |
Trinocular disparity processor using a hierarchic classification structure. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
Evaluation of fault tolerant technique based on homogeneous FPGA architecture. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Michael Muehlberghuber, Christoph Keller, Norbert Felber, Christian Pendl |
100 Gbit/s authenticated encryption based on quantum key distribution. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Cristiano Thiele, Bruno Boessio Vizzotto, André L. M. Martinez, Vagner Santos Da Rosa, Sergio Bampi |
A low-cost and high efficiency entropy encoder architecture for H.264/AVC. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Farhad Alibeygi Parsan, Scott C. Smith |
CMOS implementation of static threshold gates with hysteresis: A new approach. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Le Zheng, Sangho Shin, Sung-Mo Steve Kang |
Design of a neural stimulator system with closed-loop charge cancellation. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mingyang Zhu, Jinho Lee, Kiyoung Choi |
An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami |
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Haven Blake Skinner, Xuchu Hu, Matthew R. Guthaus |
Harmonic resonant clocking. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Srinivas Katkoori, Matthew R. Guthaus, Ayse K. Coskun, Andreas Burg, Ricardo Reis 0001 (eds.) |
20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012 |
VLSI-SoC |
2012 |
DBLP BibTeX RDF |
|
1 | Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini |
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Takeshi Matsumoto, Shohei Ono, Masahiro Fujita |
An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Shilpa Pendyala, Srinivas Katkoori |
Interval arithmetic based input vector control for RTL subthreshold leakage minimization. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jie Meng, Fulya Kaplan, Ming-yu Hsieh, Ayse K. Coskun |
Topology-aware reliability optimization for multiprocessor systems. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba |
Using asymmetric layer repair capability to reduce the cost of yield enhancement in 3D stacked memories. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Fernando Corinto, Alon Ascoli, Marco Gilli |
A novel elementary memristive system. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Stefano Pietri, Chris Dao, Juxiang Ren, Jehoda Refaeli, Alfredo Olmos |
Safety oriented automotive MCU power management. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Daniel T. Grissom, Kenneth O'Neal, Benjamin Preciado, Hiral Patel, Robert Doherty, Nick Liao, Philip Brisk |
A digital microfluidic biochip synthesis framework. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Kenneth O'Neal, Daniel T. Grissom, Philip Brisk |
Force-Directed List Scheduling for Digital Microfluidic Biochips. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sandro Belfanti, Christian Benkeser, Karim Badawi, Qiuting Huang, Andreas Burg |
Successive interference cancellation for 3G downlink: Algorithm and VLSI architecture. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Matthew R. Guthaus |
Welcome from the general chair. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ilias Pappas 0001, Vasilios Kalenteridis, Stylianos Siskos, Spiridon Vlassis |
A complete over-current/short-circuit protection system for Low-Drop Out regulators. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro |
ATARDS: An adaptive fault-tolerant strategy to cope with massive defects in Network-on-Chip interconnections. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sebastian Steinhorst, Lars Hedrich |
Equivalence checking of nonlinear analog circuits for hierarchical AMS System Verification. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Surya Sharma, Trond Ytterdal |
Low noise front-end amplifier design for medical ultrasound imaging applications. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Advait Madhavan, Dmitri B. Strukov |
Mapping of image and network processing tasks on high-throughput CMOL FPGA circuits. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul D. Franzon |
A novel double floating-gate unified memory device. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer |
ArchFP: Rapid prototyping of pre-RTL floorplans. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hamid Mahmoodi |
Reliability enhancement of power gating transistor under time dependent dielectric breakdown. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung |
Cost-effective TSV redundancy configuration. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | K. T. Hafeez, Ashudeb Dutta, Shiv Govind Singh |
Efficient adaptive switch design for charge pumps in micro-scale energy harvesting. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ignatius Bezzam, Shoba Krishnan, Chakravarthy Mathiazhagan |
Low power SoCs with resonant dynamic logic using inductors for energy recovery. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson |
FPGA power reduction by guarded evaluation considering physical information. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Seokjoong Kim, Matthew R. Guthaus |
Dynamic voltage scaling for SEU-tolerance in low-power memories. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ligang Gao, Fabien Alibart, Dmitri B. Strukov |
Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Zhibin Xiao, Bevan M. Baas |
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Avijit Dutta |
Low cost adjacent double error correcting code with complete elimination of miscorrection within a dispersion window for Multiple Bit Upset tolerant memory. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hamed Sajjadi Kia, Cristinel Ababei |
A new reliability evaluation methodology and its application to network-on-chip routers. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sohail Asghar, Rocío del Río, José M. de la Rosa 0001 |
A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW flexible 4th-order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Christian Benkeser, Christoph Roth, Qiuting Huang |
Turbo decoder design for high code rates. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev |
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Haroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii |
Aging-aware caches with graceful degradation of performance. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak |
A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ravi Patel 0001, Eby G. Friedman |
Arithmetic encoding for memristive multi-bit storage. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Anupam Chattopadhyay, Goutam Paul 0001 |
Exploring security-performance trade-offs during hardware accelerator design of stream cipher RC4. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Pierre-Emmanuel Gaillardon, Davide Sacchetto, Shashikanth Bobba, Yusuf Leblebici, Giovanni De Micheli |
GMS: Generic memristive structure for non-volatile FPGAs. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Rajsaktish Sankaranarayanan, Matthew R. Guthaus |
A single-VDD ultra-low energy sub-threshold FPGA. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jaspal Singh Shah, David Nairn, Manoj Sachdev |
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the optimized generation of Software-Based Self-Test programs for VLIW processors. |
VLSI-SoC |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tadahiro Kuroda |
ThruChip interface (TCI) for 3D networks on chip. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Gianluca Palermo, Cristina Silvano |
Two-levels of adaptive buffer for virtual channel router in NoCs. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Oliver Mitea, Markus Meissner, Lars Hedrich |
Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts. |
VLSI-SoC |
2011 |
DBLP DOI BibTeX RDF |
|