Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	Ming Z. Zhang, Li Tao, Ming-Jung Seow, Vijayan K. Asari	Design of an Efficient Flexible Architecture for Color Image Enhancement.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	color image enhancement, reflectance/illumination model, HSV-domain image processing, log-domain computation, 2D convolution, multiplier-less architecture, quadrant symmetric architecture, parallel-pipelined architecture, homomorphic filter
8	Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan	Thermal characterization and optimization in platform FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal
8	Jason Cong, Yiping Fan, Wei Jiang	Platform-based resource binding using a distributed register-file microarchitecture.	ICCAD	2006	DBLP DOI BibTeX RDF	distributed register file, behavior synthesis, resource binding
8	Dong-Ho Kang, Byoung-Koo Kim, Jintae Oh, Taek Yong Nam, Jong-Soo Jang	FPGA Based Intrusion Detection System Against Unknown and Known Attacks.	PRIMA	2006	DBLP DOI BibTeX RDF	Protocol Anomaly Detection, Intrusion Detection, Network Security
8	Hans-Peter Löb, Rainer Buchty, Wolfgang Karl	A network agent for diagnosis and analysis of real-time Ethernet networks.	CASES	2006	DBLP DOI BibTeX RDF	industrial Ethernet, real-time, monitoring, system-on-chip
8	Christoforos Kachris, Stamatis Vassiliadis	Performance Evaluation of an Adaptive FPGA for Network Applications.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
8	David Valencia, Antonio Plaza	FPGA-Based Hyperspectral Data Compression Using Spectral Unmixing and the Pixel Purity Index Algorithm.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
8	H. Spaanenburg, J. Thompson, V. Abraham, Lambert Spaanenburg, Wenhai Fang	Need for large local FPGA-accessible memories in the integration of bio-inspired applications into embedded systems.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, José Luís Güntzel, Ivan Saraiva Silva, Sergio Bampi	High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Zhiqiang Cui, Zhongfeng Wang 0001	A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Isabelle LaRoche, Sébastien Roy 0002	An efficient regular matrix inversion circuit architecture for MIMO processing.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Zhaohui Cai, Jianzhong Hao, Sumei Sun, Francois Poshin Chin	A high-speed Reed-Solomon decoder for correction of both errors and erasures.	ISCAS	2006	DBLP DOI BibTeX RDF
8	Pawel Garstecki, Adam Luczak, Marta Stepniewska	A bit-serial implementation of mode decision algorithm for AVC encoders.	ISCAS	2006	DBLP DOI BibTeX RDF
8	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
8	Mustafa Parlak, Ilker Hamzaoglu	An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter.	AHS	2006	DBLP DOI BibTeX RDF
8	Andres Upegui, Eduardo Sanchez	Evolving Hardware with Self-reconfigurable connectivity in Xilinx FPGAs.	AHS	2006	DBLP DOI BibTeX RDF
8	Luciano Volcan Agostini, Roger Endrigo Carvalho Porto, Sergio Bampi, Leandro Rosa, José Luís Güntzel, Ivan Saraiva Silva	High throughput architecture for H.264/AVC forward transforms block.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	2-D FDCT, 2-D hadamard, H.264/AVC forward transforms, H.264/AVC standard, VLSI architecture, system prototyping
8	Riad Ben Mouhoub, Omar Hammami	System-Level Design Methodology with Direct Execution For Multiprocessors on SoPC.	ISQED	2006	DBLP DOI BibTeX RDF
8	José Manuel Claver, Manel Canseco, P. Agustí, Germán León	A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers.	ISPA	2006	DBLP DOI BibTeX RDF
8	Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi	A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering.	IJCNN	2006	DBLP DOI BibTeX RDF
8	Ming Z. Zhang, Ming-Jung Seow, Vijayan K. Asari	A Hardware Architecture for Color Image Enhancement Using a Machine Learning Approach with Adaptive Parameterization.	IJCNN	2006	DBLP DOI BibTeX RDF
8	Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar	An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization.	IJCNN	2006	DBLP DOI BibTeX RDF
8	Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami	An FPGA-Based Singular Value Decomposition Processor.	CCECE	2006	DBLP DOI BibTeX RDF
8	Rami S. Abielmona, Voicu Groza, Arkan Khalaf	Run-Time Reconfigurable Built-in-Self-Test.	CCECE	2006	DBLP DOI BibTeX RDF
8	Akila Gothandaraman, G. Lee Warren, Gregory D. Peterson, Robert J. Harrison	Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems.	SC	2006	DBLP DOI BibTeX RDF
8	Yu Bi, Gregory D. Peterson, G. Lee Warren, Robert J. Harrison	Poster reception - A reconfigurable supercomputing library for accelerated parallel lagged-Fibonacci pseudorandom number generation.	SC	2006	DBLP DOI BibTeX RDF
8	Peter J. Green, Desmond P. Taylor	Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors.	DELTA	2006	DBLP DOI BibTeX RDF
8	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Improving SHA-2 Hardware Implementations.	CHES	2006	DBLP DOI BibTeX RDF	SHA-2 (256, 512), FPGA, Cryptography, Hash functions
8	Sung Dae Kim, Choong Jin Hyun, Myung Hoon Sunwoo	VSIP : Implementation of Video Specific Instruction-set Processor.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Ming Z. Zhang, Vijayan K. Asari	A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Arjuna Madanayake, Leonard T. Bruton	Fully-multiplexed First-order 3D IIR Frequency-Planar Filter Module.	APCCAS	2006	DBLP DOI BibTeX RDF
8	S. Raghunath, Syed Mahfuzul Aziz	Design of an Area Efficient High-Speed Color FDWT Processor.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Arjuna Madanayake, Leonard T. Bruton	FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters.	APCCAS	2006	DBLP DOI BibTeX RDF
8	Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong	A hardware Gaussian noise generator using the Wallace method.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
8	Florent de Dinechin, Arnaud Tisserand	Multipartite Table Methods.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	elementary function evaluation, hardware operator, table lookup and addition method, Computer arithmetic
8	Sanghamitra Roy, Prith Banerjee	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic
8	Thomas W. Fry, Scott Hauck	SPIHT image compression on FPGAs.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
8	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
8	Ying Yi, Roger F. Woods, Lok-Kee Ting, C. F. N. Cowan	High Speed FPGA-Based Implementations of Delayed-LMS Filters.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	delayed LMS filters, retiming technique, hardware sharing, FPGA, adaptive filtering
8	Robert Fischer 0002, Klaus Buchenrieder, Ulrich Nageldinger	Reducing the Power Consumption of FPGAs through Retiming.	ECBS	2005	DBLP DOI BibTeX RDF
8	Shrutisagar Chandrasekaran, Abbes Amira	An area efficient low power inner product computation for discrete orthogonal transforms.	ICIP (3)	2005	DBLP DOI BibTeX RDF
8	Roman C. Kordasiewicz, Shahram Shirani	ASIC and FPGA implementations of H.264 DCT and quantization blocks.	ICIP (3)	2005	DBLP DOI BibTeX RDF
8	Humberto Calderon, Stamatis Vassiliadis	Reconfigurable Multiple Operation Array.	SAMOS	2005	DBLP DOI BibTeX RDF
8	Ming Z. Zhang, Hau T. Ngo, Adam R. Livingston, Vijayan K. Asari	An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels.	ISVLSI	2005	DBLP DOI BibTeX RDF	2-D convolution, symmetric kernel, pipelined architecture, systolic architecture
8	Deepak Rautela, Rajendra S. Katti	Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources.	ISVLSI	2005	DBLP DOI BibTeX RDF
8	Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho	A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Ling Zhuo, Viktor K. Prasanna	Sparse Matrix-Vector multiplication on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, reconfigurable architecture, high performance, floating-point, sparse matrix
8	Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh	Routing algorithms: enhancing routability & enabling ECO (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Edward D. Moreno, Fábio Dacêncio Pereira, Rodolfo B. Chiaramonte	A VLIW-based cryptoprocessor on FPGAs architecture and performance issues (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Bo Yang 0010, Nikhil Joshi, Ramesh Karri	A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Exploration of heterogeneous reconfigurable architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev	64-bit floating-point FPGA matrix multiplication.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, matrix multiplication, floating-point
8	Deepak Rautela, Rajendra S. Katti	Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
8	Flavius Gruian, Per Andersson, Krzysztof Kuchcinski, Martin Schoeberl	Automatic generation of application-specific systems based on a micro-programmed Java core.	SAC	2005	DBLP DOI BibTeX RDF	Java, FPGA, system-on-chip, co-design
8	Tim Schattkowsky, Wolfgang Müller 0003, Achim Rettberg	A Model-Based Approach for Executable Specifications on Reconfigurable Hardware.	DATE	2005	DBLP DOI BibTeX RDF
8	Roberto R. Osorio, Javier D. Bruguera	A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder.	DSD	2005	DBLP DOI BibTeX RDF
8	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
8	Il-Gu Lee, Seungbeom Lee, Sin-Chong Park	Effective Co-Verification of IEEE 802.11a MAC/PHY Combining Emulation and Simulation Technology.	Annual Simulation Symposium	2005	DBLP DOI BibTeX RDF
8	João Canas Ferreira, Miguel M. Silva	Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer.	IPDPS	2005	DBLP DOI BibTeX RDF
8	Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna	Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
8	Kjetil E. Vistnes, Oddvar Søråsen	Reconfigurable Address Generators for Stream-Based Computation Implemented on FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
8	Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara	Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA.	IPDPS	2005	DBLP DOI BibTeX RDF
8	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
8	Andres Upegui, Eduardo Sanchez	Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs.	ICES	2005	DBLP DOI BibTeX RDF
8	Tomás Martínek, Lukás Sekanina	An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA.	ICES	2005	DBLP DOI BibTeX RDF
8	Hugo Hedberg, Thomas Lenart, Henrik Svensson	A Complete MP3 Decoder on a Chip.	MSE	2005	DBLP DOI BibTeX RDF
8	Joseph Schneider, Mikel Bezdek, Ziyu Zhang, Zhao Zhang, Diane T. Rover	A Platform FPGA-Based Hardware-Software Undergraduate Laboratory.	MSE	2005	DBLP DOI BibTeX RDF
8	Mohammed Y. Niamat, Surya S. Hejeebu, Mansoor Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
8	Zachary K. Baker, Viktor K. Prasanna	Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
8	Young H. Cho, William H. Mangione-Smith	Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network.	FCCM	2005	DBLP DOI BibTeX RDF
8	Chuan He, Wei Zhao 0001, Mi Lu	Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform.	FCCM	2005	DBLP DOI BibTeX RDF
8	Paul Baker, Tim Todman, Henry Styles, Wayne Luk	Reconfigurable Designs for Radiosity.	FCCM	2005	DBLP DOI BibTeX RDF
8	Michael Attig, John W. Lockwood	A Framework for Rule Processing in Reconfigurable Network Systems.	FCCM	2005	DBLP DOI BibTeX RDF
8	M. Rajaram Narayanan, S. Gowri, S. Ravi 0001	An Evolvable Hardware Chip for Image Enhancement in Surface Roughness Estimation.	ICNC (3)	2005	DBLP DOI BibTeX RDF
8	Ming Z. Zhang, Hau T. Ngo, Vijayan K. Asari	Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
8	Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung	Automating custom-precision function evaluation for embedded processors.	CASES	2005	DBLP DOI BibTeX RDF	embedded systems, reconfigurable computing, fixed-point arithmetic, function evaluation
8	S. W. Song 0002, J. D. Zheng, William B. Gardner	Prototyping a Residential Gateway Using Xilinx ISE.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
8	Hua Li, Jianzhou Li	A High Performance Sub-Pipelined Architecture for AES.	ICCD	2005	DBLP DOI BibTeX RDF	sub-pipelined architecture, FPGA, cryptography, AES
8	Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra	Quantized LDPC decoder design for binary symmetric channels.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
8	Isa Servan Uzun, Abbes Amira	Design and FPGA implementation of finite Ridgelet transform [image processing applications].	ISCAS (6)	2005	DBLP DOI BibTeX RDF
8	C. Huggett, Koushik Maharatna, K. Paul	On the implementation of 128-pt FFT/IFFT for high-performance WPAN.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
8	Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä	Hardware Implementation Analysis of the MD5 Hash Algorithm.	HICSS	2005	DBLP DOI BibTeX RDF
8	Marcelo Götz, Achim Rettberg, Carlos Eduardo Pereira	A Run-Time Partitioning Algorithm for RTOS on Reconfigurable Hardware.	EUC	2005	DBLP DOI BibTeX RDF
8	Alessandro Cilardo, Antonino Mazzeo, Luigi Romano	An FPGA-based Key-Store for Improving the Dependability of Security Services.	WORDS	2005	DBLP DOI BibTeX RDF
8	Ling Zhuo, Viktor K. Prasanna	High-Performance and Area-Efficient Reduction Circuits on FPGAs.	SBAC-PAD	2005	DBLP DOI BibTeX RDF
8	Ling Zhuo, Viktor K. Prasanna	Design Tradeoffs for BLAS Operations on Reconfigurable Hardware.	ICPP	2005	DBLP DOI BibTeX RDF
8	Krishna Prasad Raghuraman, Haibo Wang 0005, Spyros Tragoudas	A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF
8	Jin Wang, Je Kyo Jung, Yong-Min Lee, Chong Ho Lee	Using Reconfigurable Architecture-Based Intrinsic Incremental Evolution to Evolve a Character Classification System.	CIS (1)	2005	DBLP DOI BibTeX RDF
8	Gerald R. Morris, Viktor K. Prasanna	An FPGA-Based Floating-Point Jacobi Iterative Solver.	ISPAN	2005	DBLP DOI BibTeX RDF
8	Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk	MiniBit: bit-width optimization via affine arithmetic.	DAC	2005	DBLP DOI BibTeX RDF	bit-width, simulated, FPGA, fixed-point, affine arithmetic, annealing
8	Dongil Han, Dae-Hwan Hwang	A Novel Stereo Matching Method for Wide Disparity Range Detection.	ICIAR	2005	DBLP DOI BibTeX RDF
8	Richard H. Turner, Roger F. Woods	Highly efficient, limited range multipliers for LUT-based FPGA architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
8	Henry Styles, Wayne Luk	Exploiting Program Branch Probabilities in Hardware Compilation.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	queuing theory, Automatic synthesis, dataflow architectures
8	Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte	The MOLEN Polymorphic Processor.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Custom computing machines, reconfigurable microcode, polymorphic processors, FPGA, reconfigurable processors, firmware
8	Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung	A Gaussian Noise Generator for Hardware-Based Simulations.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	simulation, error-checking, gate arrays, Algorithms implemented in hardware
8	Wai-Kei Mak	I/O placement for FPGAs with multiple I/O standards.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
8	Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis	Dynamic Hardware Reconfigurations: Performance Impact for MPEG2.	SAMOS	2004	DBLP DOI BibTeX RDF
8	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	Loading rho-µ-Code: Design Considerations.	SAMOS	2004	DBLP DOI BibTeX RDF	MOLEN, loading microcode, implementation, Reconfigurable architectures
8	Bret Woz, Andreas E. Savakis	A VHDL MPEG-7 shape descriptor extractor.	FPGA	2004	DBLP DOI BibTeX RDF
8	Richard Carbone, Andreas E. Savakis	A flexible hardware architecture for 2-D discrete wavelet transform.	FPGA	2004	DBLP DOI BibTeX RDF