Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Omar Fawzi, Paul Fermé |
Beating the Sum-Rate Capacity of the Binary Adder Channel with Non-Signaling Correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIT ![In: IEEE International Symposium on Information Theory, ISIT 2022, Espoo, Finland, June 26 - July 1, 2022, pp. 2750-2755, 2022, IEEE, 978-1-6654-2159-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Gökberk Erdogan, Georg Maringer, Nikita Polyanskii |
Signature Codes for a Noisy Adder Multiple Access Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITW ![In: IEEE Information Theory Workshop, ITW 2022, Mumbai, India, November 1-9, 2022, pp. 476-481, 2022, IEEE, 978-1-6654-8341-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Rafael B. Schvittz, Cristina Meinhardt |
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, SBCCI 2022, Porto Alegre, Brazil, August 22-26, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8128-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jongwook Sohn, David K. Dean, Eric Quintana, Wing Shek Wong |
Enhanced Floating-Point Adder with Full Denormal Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 29th IEEE Symposium on Computer Arithmetic, ARITH 2022, Lyon, France, September 12-14, 2022, pp. 1-8, 2022, IEEE, 978-1-6654-7827-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Teodor-Dumitru Ene, James E. Stine |
Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 29th IEEE Symposium on Computer Arithmetic, ARITH 2022, Lyon, France, September 12-14, 2022, pp. 68-75, 2022, IEEE, 978-1-6654-7827-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Shibaji Basu, Praveen Jain |
A Fully Soft-Switched Resonant Based DC-DC Converter using Adder Architecture for Fast EV Battery Charging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECON ![In: IECON 2022 - 48th Annual Conference of the IEEE Industrial Electronics Society, Brussels, Belgium, October 17-20, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8025-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Bhanprakash Goswami, Manan Suri |
Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, NANOARCH 2022, Virtual, OR, USA, December 7-9, 2022, pp. 1:1-1:6, 2022, ACM, 978-1-4503-9938-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato |
An Accuracy-Controllable Approximate Adder for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATAIT ![In: Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), Ibaraki and Virtual, Japan, August 24-26, 2022., pp. 60-66, 2022, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
13 | Philipp Niemann 0001, Rolf Drechsler |
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 52nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2022, Dallas, TX, USA, May 18-20, 2022, pp. 9-14, 2022, IEEE, 978-1-6654-2395-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Wenshuo Li, Xinghao Chen 0001, Jinyu Bai, Xuefei Ning, Yunhe Wang 0001 |
Searching for Energy-Efficient Hybrid Adder-Convolution Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR Workshops ![In: IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, CVPR Workshops 2022, New Orleans, LA, USA, June 19-20, 2022, pp. 1942-1951, 2022, IEEE, 978-1-6654-8739-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark |
Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR Workshops ![In: IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, CVPR Workshops 2022, New Orleans, LA, USA, June 19-20, 2022, pp. 2792-2796, 2022, IEEE, 978-1-6654-8739-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Sarada Musala, P. Durga Vasavi, B. Spandana, Avireni Srinivasulu, Cristian Ravariu |
A Novel 2:1 Multiplexer Based Quaternary Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022, pp. 372-377, 2022, IEEE, 979-8-3503-9922-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita |
Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 58-63, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami 0002, Dip Sankar Banerjee, Babita Jajodia |
EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jihyung Jung, Youngmin Kim |
A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 131-132, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Donghui Lee, Junhyuk Baik, Yongtae Kim |
An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 51-52, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hyelin Seok, Hyoju Seo, Jungwon Lee, Yongtae Kim |
A Novel Efficient Approximate Adder Design using Single Input Pair based Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 19th International SoC Design Conference, ISOCC 2022, Gangneung-si, Republic of Korea, October 19-22, 2022, pp. 57-58, 2022, IEEE, 978-1-6654-5971-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Anantharaj Thalaimalai Vanaraj, Raja Sekar Kumaresan, Marshal Raj, Anand Venkitachalam, G. Lakshminarayanan |
Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 13th International Conference on Computing Communication and Networking Technologies, ICCCNT 2022, Kharagpur, India, October 3-5, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-5262-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Panasa Srikanth, B. Srinivasu |
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 420-434, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal |
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 262-274, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh |
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 435-449, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Chenyu Xie, Chunmei Yang, Hailong Jiao |
A Karnaugh Map Approximate Adder With Intrinsic Error Compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 10-14, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Amir E. Oghostinos, Kareem Moussa, Amr Elnaggar, Alaa AbdAlRhman, Ahmed Soltan |
Single-Cycle MIPS Processor based on Configurable Approximate Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022, Bremen, Germany, June 8-10, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-6717-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad Javad Maleki, Ali Mir 0001, Mohammad Soroosh |
Ultra-fast all-optical full-adder based on nonlinear photonic crystal resonant cavities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 41(1), pp. 93-101, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Saeid Seyedi, Nima Jafari Navimipour |
Designing a three-level full-adder based on nano-scale quantum dot cellular automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Photonic Netw. Commun. ![In: Photonic Netw. Commun. 42(3), pp. 184-193, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Garima Thakur, Harsh Sohal, Shruti Jain |
A novel parallel prefix adder for optimized Radix-2 FFT processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multidimens. Syst. Signal Process. ![In: Multidimens. Syst. Signal Process. 32(3), pp. 1041-1063, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Aiman H. El-Maleh, Ghashmi H. Bin Talib |
Time redundancy and gate sizing soft error-tolerant based adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 78, pp. 49-59, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast |
A novel reversible ternary coded decimal adder/subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 12(7), pp. 7745-7763, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | |
Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Ambient Intell. Humaniz. Comput. ![In: J. Ambient Intell. Humaniz. Comput. 12(5), pp. 5513-5524, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jihad Mohamad Al Ja'am, Ramzi A. Jaber, Somaya Ali Al-Máadeed |
Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 56726-56735, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jungwon Lee, Hyoju Seo, Hyelin Seok, Yongtae Kim |
A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 119939-119953, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell, Nikos E. Mastorakis |
An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 4518-4530, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sarah Azimi, Corrado De Sio, Luca Sterpone |
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(8), pp. 1596-1600, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mukesh Patidar, Namit Gupta |
Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder-subtractor using QCA technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 77(8), pp. 7893-7915, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh |
A High Performance, Multi-Bit Output Logic-in-Memory Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 9(4), pp. 2223-2233, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Rakcinpha Hatibaruah, Vijay Kumar Nath, Deepika Hazarika |
Computed tomography image retrieval via combination of two local bit plane-based dissimilarities using an adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Wavelets Multiresolution Inf. Process. ![In: Int. J. Wavelets Multiresolution Inf. Process. 19(1), pp. 2050058:1-2050058:18, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Garima Thakur, Harsh Sohal, Shruti Jain |
A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(11), pp. 5682-5704, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani |
Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(7), pp. 3523-3535, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Inamul Hussain, Saurabh Chaudhury |
Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(4), pp. 1762-1787, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | J. Jean Jenifer Nesam, Sankar Ganesh S. |
Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(4), pp. 1832-1851, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan |
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(8), pp. 4089-4105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Seied Ali Hosseini, Sajjad Etezadi |
A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(3), pp. 1314-1332, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Thiruvengadam Rajagopal, Arvind Chakrapani |
A Novel High-Performance Hybrid Full Adder for VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(11), pp. 5718-5732, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | S. Rooban, Prasanna D. Lakshmi, Teja K. B. S. Durga, Kumar P. V. Mani |
Carry Select Adder Design with Testability using Reversible Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Perform. Eng. ![In: Int. J. Perform. Eng. 17(6), pp. 536, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Guilherme da Costa Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. da Costa, Sergio Bampi |
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 15(3), pp. 230-240, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mohamed Osman, Khaled El-Wazan |
Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 13(10), pp. 1842, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Andrei Bencze, Maria Luminita Scutaru, Marin Marin, Sorin Vlase, Ana Toderita |
Adder Box Used in the Heavy Trucks Transmission Noise Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Symmetry ![In: Symmetry 13(11), pp. 2165, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sharana Basappa, P. Ravi Babu |
A low power architecture for 1D median filter using carry look ahead adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Adv. Intell. Paradigms ![In: Int. J. Adv. Intell. Paradigms 20(1/2), pp. 16-37, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, Cheng-Tse Chiang |
Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(8), pp. 3328-3336, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Zhufei Chu, Zeqiang Li, Yinshui Xia, Lunyao Wang, Weiqiang Liu 0001 |
BCD Adder Designs Based on Three-Input XOR and Majority Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(6), pp. 1942-1946, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Túlio Araujo, Matheus B. R. Cardoso, Erivelton G. Nepomuceno, Carlos H. Llanos, Janier Arias-Garcia |
A new floating-point adder FPGA-based implementation using RN-coding of numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 90, pp. 106947, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mehedi Hasan, Md. Shahbaz Hussain, Mainul Hossain, Mohd. Hasan, Hasan U. Zaman, Sharnali Islam |
A high-speed and scalable XOR-XNOR-based hybrid full adder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 93, pp. 107200, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan |
Improved Redundant Binary Adder Realization in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(16), pp. 2150287:1-2150287:14, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen |
CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(10), pp. 2150172:1-2150172:33, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen |
CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(11), pp. 2192001:1, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini |
An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(2), pp. 2150021:1-2150021:17, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | M. Priyadharshni, Antra Raj Gupta, Venkatachalam Nithish Kumar, Sundaram Kumaravel 0001 |
An error efficient and low complexity approximate multi-bit adder for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(8), pp. 2373-2381, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sadat Riyaz, Syed Farah Naz, Vijay Kumar Sharma |
Multioperative reversible gate design with implementation of 1-bit full adder and subtractor along with energy dissipation analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(4), pp. 990-1012, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Mehedi Hasan, Sharnali Islam, Mainul Hossain, Hasan U. Zaman |
A scalable high-speed hybrid 1-bit full adder design using XOR-XNOR module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(11), pp. 3597-3606, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus |
Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 29(Part), pp. 100457, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Seyed Erfan Fatemieh, Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad |
LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 30, pp. 100529, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jinping Fan, Yujie Gu, Masahiro Hachimori, Ying Miao 0001 |
Signature Codes for Weighted Binary Adder Channel and Multimedia Fingerprinting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 67(1), pp. 200-216, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani |
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 108, pp. 104962, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal |
Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 115, pp. 105205, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam |
A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 109, pp. 104992, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | M. Rahimi, M. B. Ghaznavi-Ghoushchi |
A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105086, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 107, pp. 104961, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Nabiollah Shiri |
An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 118, pp. 105287, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sandip Swarnakar, Amrutha Guddati, Siva Koti Reddy, Ramanand Harijan, Santosh Kumar 0005 |
Performance analysis of optimized plasmonic half-adder circuit using Mach-Zehnder interferometer for high-speed switching applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 111, pp. 105040, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ebrahim Farahmand, Ali Mahani 0001, Muhammad Abdullah Hanif, Muhammad Shafique 0001 |
High Performance and Optimal Configuration of Accurate Heterogeneous Block-Based Approximate Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.08800, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Hanting Chen, Yunhe Wang 0001, Chang Xu 0002, Chao Xu 0006, Chunjing Xu, Tong Zhang 0001 |
Adder Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.14202, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Q. Y. Yu, K. X. Song |
Uniquely Decodable Multi-Amplitude Sequence for Massive Grant-free Multiple-Access Adder Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.11827, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao |
Recurrent Neural Network from Adder's Perspective: Carry-lookahead RNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2106.12901, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Xinghao Chen 0001, Chang Xu 0002, Minjing Dong, Chunjing Xu, Yunhe Wang 0001 |
An Empirical Study of Adder Neural Networks for Object Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2112.13608, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Samuel H. Florin, Matthew H. Ho, Zilin Jiang |
On the binary adder channel with complete feedback, with an application to quantitative group testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2101.09898, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.02223, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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13 | Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente |
Numerical model for 32-bit magnonic ripple carry adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2109.12973, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa |
An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electr. Comput. Eng. ![In: J. Electr. Comput. Eng. 2021, pp. 8856399:1-8856399:9, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Bharat Garg, Sujit Kumar Patel |
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 93(1), pp. 99-111, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Mário P. Véstias, Horácio C. Neto |
Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms ![In: Algorithms 14(7), pp. 198, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao |
Recurrent neural network from adder's perspective: Carry-lookahead RNN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Networks ![In: Neural Networks 144, pp. 297-306, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Woong Choi, Minseob Shim, Hyelin Seok, Yongtae Kim |
DCPA: approximate adder design exploiting dual carry prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 18(23), pp. 20210431, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Bala Sindhuri Kandula, Padma Vasavi Kalluru, Santi Prabha Inty |
Design of area efficient VLSI architecture for carry select adder using logic optimization technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Intell. ![In: Comput. Intell. 37(3), pp. 1155-1165, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | N. Duraivel, Paulchamy Balaiyah |
Simulation and performance analysis of 15 Nm FinFET based carry skip adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Intell. ![In: Comput. Intell. 37(2), pp. 799-818, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Rolf Drechsler |
PolyAdd: Polynomial Formal Verification of Adder Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021, pp. 99-104, 2021, IEEE, 978-1-6654-3595-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Nikhil Advaith Gudala, Trond Ytterdal, John J. Lee 0001, Maher E. Rizkalla |
Implementation of High Speed and Low Power Carry Select Adder with BEC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 64th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021, Lansing, MI, USA, August 9-11, 2021, pp. 377-381, 2021, IEEE, 978-1-6654-2461-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Hongwei Li, Xuemei Fan, Qiang Li, Hao Liu 0013 |
An Efficient Light-weight Configurable Approximate Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2614-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Emmanuel Tonatihu Juárez-Velázquez, Derlis Hernández Lara, Carlos Alfonso Trejo-Villanueva |
Finite-Field Parallel Adder Circuit Over Prime Numbers Based on Spiking Neural P Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICAI (2) ![In: Advances in Soft Computing - 20th Mexican International Conference on Artificial Intelligence, MICAI 2021, Mexico City, Mexico, October 25-30, 2021, Proceedings, Part II, pp. 208-215, 2021, Springer, 978-3-030-89819-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jaeyoon Park, Youngmin Kim |
Design and Implementation of Ternary Carry Lookahead Adder on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEIC ![In: International Conference on Electronics, Information, and Communication, ICEIC 2021, Jeju, South Korea, January 31 - February 3, 2021, pp. 1-2, 2021, IEEE, 978-1-7281-9161-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee, Milos D. Ercegovac |
Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSCC ![In: 55th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2021, Pacific Grove, CA, USA, October 31 - November 3, 2021, pp. 938-942, 2021, IEEE, 978-1-6654-5828-3. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Kancharla Vijaya Vardhan, Sarada Musala, Avireni Srinivasulu |
Novel Modular Adder Based on Thermometer Coding for Residue Number Systems Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI ![In: 13th International Conference on Electronics, Computers and Artificial Intelligence, ECAI 2021, Pitesti, Romania, July 1-3, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-2534-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xunbo Hu, Jiarui Xu, Bei Xu, Zixuan Peng, Guoyi Yu, Yuhui He, Chao Wang 0096 |
A Data Non-destructive IMPLY-based Memristive Semi-parallel Full-Adder for Computing-in-memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2021, Zhuhai, China, November 24-26, 2021, pp. 212-213, 2021, IEEE, 978-1-6654-1745-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Yuehong Gong, Min Luo, Chenxu Wang |
An MTJ reading and writing control circuit applied in a 1-bit full adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IECC ![In: IECC 2021: 3rd International Electronics Communication Conference, Ho Chi Minh City, Vietnam, July 8 - 10, 2021, pp. 22-27, 2021, ACM, 978-1-4503-8993-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Teodor-Dumitru Ene, James E. Stine |
A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021, pp. 125-129, 2021, IEEE, 978-1-6654-3219-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui |
Spin Wave Based Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt |
SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2057-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui |
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Zhixin Wu, Yuejun Zhang, Shimin Du, Zhecheng Guo, Wanlong Zhao |
A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-3, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xinghao Chen 0001, Chang Xu 0002, Minjing Dong, Chunjing Xu, Yunhe Wang 0001 |
An Empirical Study of Adder Neural Networks for Object Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NeurIPS ![In: Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, NeurIPS 2021, December 6-14, 2021, virtual., pp. 6894-6905, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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