Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Omar Fawzi, Paul Fermé	Beating the Sum-Rate Capacity of the Binary Adder Channel with Non-Signaling Correlations.	ISIT	2022	DBLP DOI BibTeX RDF
13	Gökberk Erdogan, Georg Maringer, Nikita Polyanskii	Signature Codes for a Noisy Adder Multiple Access Channel.	ITW	2022	DBLP DOI BibTeX RDF
13	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Rafael B. Schvittz, Cristina Meinhardt	Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing.	SBCCI	2022	DBLP DOI BibTeX RDF
13	Jongwook Sohn, David K. Dean, Eric Quintana, Wing Shek Wong	Enhanced Floating-Point Adder with Full Denormal Support.	ARITH	2022	DBLP DOI BibTeX RDF
13	Teodor-Dumitru Ene, James E. Stine	Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees.	ARITH	2022	DBLP DOI BibTeX RDF
13	Shibaji Basu, Praveen Jain	A Fully Soft-Switched Resonant Based DC-DC Converter using Adder Architecture for Fast EV Battery Charging Applications.	IECON	2022	DBLP DOI BibTeX RDF
13	Bhanprakash Goswami, Manan Suri	Single Cycle XOR (SCXOR) and Stateful n-bit Parallel Adder Implementation Using 2D RRAM Crossbar.	NANOARCH	2022	DBLP DOI BibTeX RDF
13	Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato	An Accuracy-Controllable Approximate Adder for FPGAs.	ATAIT	2022	DBLP BibTeX RDF
13	Philipp Niemann 0001, Rolf Drechsler	Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic.	ISMVL	2022	DBLP DOI BibTeX RDF
13	Wenshuo Li, Xinghao Chen 0001, Jinyu Bai, Xuefei Ning, Yunhe Wang 0001	Searching for Energy-Efficient Hybrid Adder-Convolution Neural Networks.	CVPR Workshops	2022	DBLP DOI BibTeX RDF
13	Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark	Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN.	CVPR Workshops	2022	DBLP DOI BibTeX RDF
13	Sarada Musala, P. Durga Vasavi, B. Spandana, Avireni Srinivasulu, Cristian Ravariu	A Novel 2:1 Multiplexer Based Quaternary Full Adder.	iSES	2022	DBLP DOI BibTeX RDF
13	Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita	Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees.	ISQED	2022	DBLP DOI BibTeX RDF
13	Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami 0002, Dip Sankar Banerjee, Babita Jajodia	EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification.	ISQED	2022	DBLP DOI BibTeX RDF
13	Jihyung Jung, Youngmin Kim	A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory.	ISOCC	2022	DBLP DOI BibTeX RDF
13	Donghui Lee, Junhyuk Baik, Yongtae Kim	An Accurate and Efficient Stochastic Computing Adder Exploiting Bit Shuffle Control Scheme.	ISOCC	2022	DBLP DOI BibTeX RDF
13	Hyelin Seok, Hyoju Seo, Jungwon Lee, Yongtae Kim	A Novel Efficient Approximate Adder Design using Single Input Pair based Computation.	ISOCC	2022	DBLP DOI BibTeX RDF
13	Anantharaj Thalaimalai Vanaraj, Raja Sekar Kumaresan, Marshal Raj, Anand Venkitachalam, G. Lakshminarayanan	Reliable Quantum-dot Cellular Automata Coplanar Adder and Subtractor for Multi-bit Designs.	ICCCNT	2022	DBLP DOI BibTeX RDF
13	Panasa Srikanth, B. Srinivasu	High Performance Ternary Full Adder in CNFET-Memristor Logic Technology.	VDAT	2022	DBLP DOI BibTeX RDF
13	S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal	An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.	VDAT	2022	DBLP DOI BibTeX RDF
13	Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh	Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees.	VDAT	2022	DBLP DOI BibTeX RDF
13	Chenyu Xie, Chunmei Yang, Hailong Jiao	A Karnaugh Map Approximate Adder With Intrinsic Error Compensation.	APCCAS	2022	DBLP DOI BibTeX RDF
13	Amir E. Oghostinos, Kareem Moussa, Amr Elnaggar, Alaa AbdAlRhman, Ahmed Soltan	Single-Cycle MIPS Processor based on Configurable Approximate Adder.	MOCAST	2022	DBLP DOI BibTeX RDF
13	Mohammad Javad Maleki, Ali Mir 0001, Mohammad Soroosh	Ultra-fast all-optical full-adder based on nonlinear photonic crystal resonant cavities.	Photonic Netw. Commun.	2021	DBLP DOI BibTeX RDF
13	Saeid Seyedi, Nima Jafari Navimipour	Designing a three-level full-adder based on nano-scale quantum dot cellular automata.	Photonic Netw. Commun.	2021	DBLP DOI BibTeX RDF
13	Garima Thakur, Harsh Sohal, Shruti Jain	A novel parallel prefix adder for optimized Radix-2 FFT processor.	Multidimens. Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Aiman H. El-Maleh, Ghashmi H. Bin Talib	Time redundancy and gate sizing soft error-tolerant based adder design.	Integr.	2021	DBLP DOI BibTeX RDF
13	Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast	A novel reversible ternary coded decimal adder/subtractor.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
13		Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
13	Jihad Mohamad Al Ja'am, Ramzi A. Jaber, Somaya Ali Al-Máadeed	Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders.	IEEE Access	2021	DBLP DOI BibTeX RDF
13	Jungwon Lee, Hyoju Seo, Hyelin Seok, Yongtae Kim	A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation.	IEEE Access	2021	DBLP DOI BibTeX RDF
13	Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell, Nikos E. Mastorakis	An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application.	IEEE Access	2021	DBLP DOI BibTeX RDF
13	Sarah Azimi, Corrado De Sio, Luca Sterpone	A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
13	Mukesh Patidar, Namit Gupta	Efficient design and implementation of a robust coplanar crossover and multilayer hybrid full adder-subtractor using QCA technology.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
13	Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh	A High Performance, Multi-Bit Output Logic-in-Memory Adder.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
13	Rakcinpha Hatibaruah, Vijay Kumar Nath, Deepika Hazarika	Computed tomography image retrieval via combination of two local bit plane-based dissimilarities using an adder.	Int. J. Wavelets Multiresolution Inf. Process.	2021	DBLP DOI BibTeX RDF
13	Garima Thakur, Harsh Sohal, Shruti Jain	A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani	Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Inamul Hussain, Saurabh Chaudhury	Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	J. Jean Jenifer Nesam, Sankar Ganesh S.	Truncated Multiplier with Delay-Minimized Exact Radix-8 Booth Recoder Using Carry Resist Adder.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan	CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Seied Ali Hosseini, Sajjad Etezadi	A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	Thiruvengadam Rajagopal, Arvind Chakrapani	A Novel High-Performance Hybrid Full Adder for VLSI Circuits.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
13	S. Rooban, Prasanna D. Lakshmi, Teja K. B. S. Durga, Kumar P. V. Mani	Carry Select Adder Design with Testability using Reversible Gates.	Int. J. Perform. Eng.	2021	DBLP DOI BibTeX RDF
13	Guilherme da Costa Ferreira, Guilherme Paim, Leandro M. G. Rocha, Gustavo M. Santana, Renato H. Neuenfeld, Eduardo A. C. da Costa, Sergio Bampi	Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors.	IET Comput. Digit. Tech.	2021	DBLP DOI BibTeX RDF
13	Mohamed Osman, Khaled El-Wazan	Efficient Designs of Quantum Adder/Subtractor Using Universal Reversible Gate on IBM Q.	Symmetry	2021	DBLP DOI BibTeX RDF
13	Andrei Bencze, Maria Luminita Scutaru, Marin Marin, Sorin Vlase, Ana Toderita	Adder Box Used in the Heavy Trucks Transmission Noise Reduction.	Symmetry	2021	DBLP DOI BibTeX RDF
13	Sharana Basappa, P. Ravi Babu	A low power architecture for 1D median filter using carry look ahead adder.	Int. J. Adv. Intell. Paradigms	2021	DBLP DOI BibTeX RDF
13	Kun-Lin Tsai, Yen-Jen Chang, Chien-Ho Wang, Cheng-Tse Chiang	Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
13	Zhufei Chu, Zeqiang Li, Yinshui Xia, Lunyao Wang, Weiqiang Liu 0001	BCD Adder Designs Based on Three-Input XOR and Majority Gates.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
13	Túlio Araujo, Matheus B. R. Cardoso, Erivelton G. Nepomuceno, Carlos H. Llanos, Janier Arias-Garcia	A new floating-point adder FPGA-based implementation using RN-coding of numbers.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
13	Mehedi Hasan, Md. Shahbaz Hussain, Mainul Hossain, Mohd. Hasan, Hasan U. Zaman, Sharnali Islam	A high-speed and scalable XOR-XNOR-based hybrid full adder design.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
13	Satya Ranjan Sahu, Bandan Kumar Bhoi, Manoranjan Pradhan	Improved Redundant Binary Adder Realization in FPGA.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
13	Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
13	Jayanta Pal, Mrinal Goswami, Apu Kumar Saha, Bibhash Sen	CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
13	Hadise Ramezani, Majid Mohammadi, Amir Sabbagh Molahoseini	An Efficient Implementation of Low-Latency Two-Dimensional Gaussian Smoothing Filter using Approximate Carry-Save Adder.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
13	M. Priyadharshni, Antra Raj Gupta, Venkatachalam Nithish Kumar, Sundaram Kumaravel 0001	An error efficient and low complexity approximate multi-bit adder for image processing applications.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
13	Sadat Riyaz, Syed Farah Naz, Vijay Kumar Sharma	Multioperative reversible gate design with implementation of 1-bit full adder and subtractor along with energy dissipation analysis.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
13	Mehedi Hasan, Sharnali Islam, Mainul Hossain, Hasan U. Zaman	A scalable high-speed hybrid 1-bit full adder design using XOR-XNOR module.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
13	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits.	Sustain. Comput. Informatics Syst.	2021	DBLP DOI BibTeX RDF
13	Seyed Erfan Fatemieh, Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad	LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS.	Sustain. Comput. Informatics Syst.	2021	DBLP DOI BibTeX RDF
13	Jinping Fan, Yujie Gu, Masahiro Hachimori, Ying Miao 0001	Signature Codes for Weighted Binary Adder Channel and Multimedia Fingerprinting.	IEEE Trans. Inf. Theory	2021	DBLP DOI BibTeX RDF
13	Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani	Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal	Design and implementation of 20-T hybrid full adder for high-performance arithmetic applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Mehedi Hasan, Muhammad Saddam Hossain, Abdul Hasib Siddique, Mainul Hossain, Hasan U. Zaman, Sharnali Islam	A high-speed 4-bit Carry Look-Ahead architecture as a building block for wide word-length Carry-Select Adder.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	M. Rahimi, M. B. Ghaznavi-Ghoushchi	A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri	CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Abhay S. Vidhyadharan, Sanjay Vidhyadharan	An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Mahmood Rafiee, Farshad Pesaran, Ayoub Sadeghi, Nabiollah Shiri	An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Sandip Swarnakar, Amrutha Guddati, Siva Koti Reddy, Ramanand Harijan, Santosh Kumar 0005	Performance analysis of optimized plasmonic half-adder circuit using Mach-Zehnder interferometer for high-speed switching applications.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
13	Ebrahim Farahmand, Ali Mahani 0001, Muhammad Abdullah Hanif, Muhammad Shafique 0001	High Performance and Optimal Configuration of Accurate Heterogeneous Block-Based Approximate Adder.	CoRR	2021	DBLP BibTeX RDF
13	Hanting Chen, Yunhe Wang 0001, Chang Xu 0002, Chao Xu 0006, Chunjing Xu, Tong Zhang 0001	Adder Neural Networks.	CoRR	2021	DBLP BibTeX RDF
13	Q. Y. Yu, K. X. Song	Uniquely Decodable Multi-Amplitude Sequence for Massive Grant-free Multiple-Access Adder Channels.	CoRR	2021	DBLP BibTeX RDF
13	Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao	Recurrent Neural Network from Adder's Perspective: Carry-lookahead RNN.	CoRR	2021	DBLP BibTeX RDF
13	Xinghao Chen 0001, Chang Xu 0002, Minjing Dong, Chunjing Xu, Yunhe Wang 0001	An Empirical Study of Adder Neural Networks for Object Detection.	CoRR	2021	DBLP BibTeX RDF
13	Samuel H. Florin, Matthew H. Ho, Zilin Jiang	On the binary adder channel with complete feedback, with an application to quantitative group testing.	CoRR	2021	DBLP BibTeX RDF
13	Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri	CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic.	CoRR	2021	DBLP BibTeX RDF
13	Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente	Numerical model for 32-bit magnonic ripple carry adder.	CoRR	2021	DBLP BibTeX RDF
13	Ismail Gassoumi, Lamjed Touil, Abdellatif Mtibaa	An Efficient Design of QCA Full-Adder-Subtractor with Low Power Dissipation.	J. Electr. Comput. Eng.	2021	DBLP DOI BibTeX RDF
13	Bharat Garg, Sujit Kumar Patel	Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency.	J. Signal Process. Syst.	2021	DBLP DOI BibTeX RDF
13	Mário P. Véstias, Horácio C. Neto	Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor.	Algorithms	2021	DBLP DOI BibTeX RDF
13	Haowei Jiang, Feiwei Qin, Jin Cao, Yong Peng 0001, Yanli Shao	Recurrent neural network from adder's perspective: Carry-lookahead RNN.	Neural Networks	2021	DBLP DOI BibTeX RDF
13	Woong Choi, Minseob Shim, Hyelin Seok, Yongtae Kim	DCPA: approximate adder design exploiting dual carry prediction.	IEICE Electron. Express	2021	DBLP DOI BibTeX RDF
13	Bala Sindhuri Kandula, Padma Vasavi Kalluru, Santi Prabha Inty	Design of area efficient VLSI architecture for carry select adder using logic optimization technique.	Comput. Intell.	2021	DBLP DOI BibTeX RDF
13	N. Duraivel, Paulchamy Balaiyah	Simulation and performance analysis of 15 Nm FinFET based carry skip adder.	Comput. Intell.	2021	DBLP DOI BibTeX RDF
13	Rolf Drechsler	PolyAdd: Polynomial Formal Verification of Adder Circuits.	DDECS	2021	DBLP DOI BibTeX RDF
13	Nikhil Advaith Gudala, Trond Ytterdal, John J. Lee 0001, Maher E. Rizkalla	Implementation of High Speed and Low Power Carry Select Adder with BEC.	MWSCAS	2021	DBLP DOI BibTeX RDF
13	Hongwei Li, Xuemei Fan, Qiang Li, Hao Liu 0013	An Efficient Light-weight Configurable Approximate Adder Design.	VLSI-SoC	2021	DBLP DOI BibTeX RDF
13	Emmanuel Tonatihu Juárez-Velázquez, Derlis Hernández Lara, Carlos Alfonso Trejo-Villanueva	Finite-Field Parallel Adder Circuit Over Prime Numbers Based on Spiking Neural P Systems.	MICAI (2)	2021	DBLP DOI BibTeX RDF
13	Jaeyoon Park, Youngmin Kim	Design and Implementation of Ternary Carry Lookahead Adder on FPGA.	ICEIC	2021	DBLP DOI BibTeX RDF
13	Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee, Milos D. Ercegovac	Adder with Reduced Latency and Minimized Interconnect for Streaming Inner Products.	ACSCC	2021	DBLP DOI BibTeX RDF
13	Kancharla Vijaya Vardhan, Sarada Musala, Avireni Srinivasulu	Novel Modular Adder Based on Thermometer Coding for Residue Number Systems Applications.	ECAI	2021	DBLP DOI BibTeX RDF
13	Xunbo Hu, Jiarui Xu, Bei Xu, Zixuan Peng, Guoyi Yu, Yuhui He, Chao Wang 0096	A Data Non-destructive IMPLY-based Memristive Semi-parallel Full-Adder for Computing-in-memory Systems.	ICTA	2021	DBLP DOI BibTeX RDF
13	Yuehong Gong, Min Luo, Chenxu Wang	An MTJ reading and writing control circuit applied in a 1-bit full adder.	IECC	2021	DBLP DOI BibTeX RDF
13	Teodor-Dumitru Ene, James E. Stine	A Comprehensive Exploration of the Parallel Prefix Adder Tree Space.	ICCD	2021	DBLP DOI BibTeX RDF
13	Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui	Spin Wave Based Full Adder.	ISCAS	2021	DBLP DOI BibTeX RDF
13	Rafael N. M. Oliveira, Fábio G. R. G. da Silva, Ricardo Reis 0001, Cristina Meinhardt	SET Mitigation Techniques on Mirror Full Adder at 7 nm FinFET Technology.	LATS	2021	DBLP DOI BibTeX RDF
13	Xiangyu Zhang, Feng Wei, Xiaoyan Liu, Xiaole Cui	Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array.	ASICON	2021	DBLP DOI BibTeX RDF
13	Zhixin Wu, Yuejun Zhang, Shimin Du, Zhecheng Guo, Wanlong Zhao	A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States.	ASICON	2021	DBLP DOI BibTeX RDF
13	Xinghao Chen 0001, Chang Xu 0002, Minjing Dong, Chunjing Xu, Yunhe Wang 0001	An Empirical Study of Adder Neural Networks for Object Detection.	NeurIPS	2021	DBLP BibTeX RDF