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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 471 occurrences of 218 keywords
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Results
Found 784 publication records. Showing 784 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Arun Shanbhag, Srinivasa R. Danda, Naveed A. Sherwani |
Floorplanning for mixed macro block and standard cell designs. |
Great Lakes Symposium on VLSI |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Yachyang Sun, Majid Sarrafzadeh |
Floorplanning by Graph Dualization: L-shaped Modules. |
Algorithmica |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Yachyang Sun, Kok-Hoo Yeap |
Edge Covering of Complex triangles in Rectangular Dual floorplanning. |
J. Circuits Syst. Comput. |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Nasir-ud-Din Gohar, Peter Y. K. Cheung |
A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. |
ISCAS |
1993 |
DBLP BibTeX RDF |
|
17 | Jürgen Herrmann, Renate Beckmann |
LEFT - A learning tool for early floorplanning. |
Microprocess. Microprogramming |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim |
Workload-Driven Floorplanning for MIPS Optimization. |
ICCD |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Canonical Embedding of Rectangular Duals with Applications to VLSI Floorplanning. |
DAC |
1992 |
DBLP BibTeX RDF |
|
17 | Luis París, G. Berbel, T. Osés |
Floorplanning strategy for mixed analog-digital VLSI integrated circuits. |
EURO-DAC |
1991 |
DBLP BibTeX RDF |
|
17 | Sang-Gil Choi, Chong-Min Kyung |
A Floorplanning Algorithm Using Rectangular Voronoi Diagram and Force-Directed Block Shaping. |
ICCAD |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Jen-Pin Weng, Alice C. Parker |
3D Scheduling: High-Level Synthesis with Floorplanning. |
DAC |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Somchai Prasitjutrakul |
Performance-driven chip floorplanning and global routing |
|
1991 |
RDF |
|
17 | Rolf Müller 0003 |
Hierarchisches Floorplanning mit integrierter globaler Verdrahtung. |
|
1990 |
RDF |
|
17 | Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh |
Floorplanning with Pin Assignment. |
ICCAD |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Thomas Lengauer, Rolf Müller |
A Robust Framework for Hierarchical Floorplanning with Integrated Global Wiring. |
ICCAD |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Alexander Herrigel |
GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell Design. |
ICCAD |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Gopalakrishnan Vijayan, Ren-Song Tsay |
Floorplanning by Topological Constraint Reduction. |
ICCAD |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Massoud Pedram, Bryan Preas |
A hierarchical floorplanning approach. |
ICCD |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Rolf Müller 0003 |
Ein robuster Rahmen für hierarchisches Floorplanning mit integrierter globaler Verdrahtung. |
GI Jahrestagung (2) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Daniel R. Brasen, Michael L. Bushnell |
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Eric Rosenberg |
Optimal module sizing in VLSI floorplanning by nonlinear programming. |
ZOR Methods Model. Oper. Res. |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Alexander Herrigel, M. Glaser, Wolfgang Fichtner |
A global floorplanning technique for VLSI layout. |
ICCD |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Marwan A. Jabri, David J. Skellern |
PIAF: A Knowledge-based/Algorithm Top-Down Floorplanning System. |
DAC |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Marwan A. Jabri, David J. Skellern |
Implementation of a knowledge base for interpreting and driving integrated circuit floorplanning algorithms. |
Artif. Intell. Eng. |
1987 |
DBLP DOI BibTeX RDF |
|
17 | David P. La Potin, Stephen W. Director |
Mason: A Global Floorplanning Approach for VLSI Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1986 |
DBLP DOI BibTeX RDF |
|
17 | André Leblond |
CAF: A computer-assisted floorplanning tool. |
DAC |
1983 |
DBLP BibTeX RDF |
|
16 | Neeraj Kaul |
Design planning trends and challenges. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
clock planning, feedthrough generation, macro placement, power domains, power planning, time budgeting, voltage areas, prototyping, partitioning, floorplanning, feasibility, hierarchical design, constraints generation, pin assignment |
16 | Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu |
Congestion prediction in early stages of physical design. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
placement, Estimation, floorplanning |
16 | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung |
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP) |
16 | Robert Fischbach, Jens Lienig, Tilo Meister |
From 3D circuit technologies and data structures to interconnect prediction. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
3d floorplanning, three-dimensional circuits, data structures, 3d integration, interconnect prediction |
16 | Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack |
Constraint-driven floorplan repair. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
constraints, Floorplanning, legalization |
16 | Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai |
Chip placement in a reticle for multiple-project wafer fabrication. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Multiple-project wafers (MPW), compatibility graph, reticle floorplanning, shuttle mask, wafer dicing, simulated annealing (SA), set cover, mixed-integer linear programming (MILP), conflict graph, set partition |
16 | Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das |
Hierarchical partitioning of VLSI floorplans by staircases. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
balanced bipartitioning, NP-completeness, Floorplanning, network flow, global routing |
16 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
General Floorplans with L/T-Shaped Blocks Using Corner Block List. |
J. Comput. Sci. Technol. |
2006 |
DBLP DOI BibTeX RDF |
corner block list, L/T-shaped blocks, floorplanning |
16 | Royce L. S. Ching, Evangeline F. Y. Young, Kevin C. K. Leung, Chris C. N. Chu |
Post-placement voltage island generation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
tree, floorplanning, voltage island |
16 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
Placement of digital microfluidic biochips using the t-tree formulation. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
placement, floorplanning, microfluidics, biochip |
16 | Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden |
Recursive bisection placement: feng shui 5.0 implementation details. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
mixed block design, placement, floorplanning |
16 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in early stages. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
placement, floorplanning, interconnect estimation |
16 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Stairway compaction using corner block list and its applications with rectilinear blocks. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
corner block list, rectilinear blocks, Floorplanning |
16 | Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden |
Recursive bisection based mixed block placement. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
mixed block design, placement, floorplanning |
16 | Hayward H. Chan, Igor L. Markov |
Practical slicing and non-slicing block-packing without simulated annealing. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
block-packing, optimal, evaluation, branch-and-bound, floorplanning, slicing, hierarchical, large-scale, soft blocks |
16 | Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang |
Rectilinear block placement using B*-trees. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
placement, layout, floorplanning, Computer-aided design of VLSI |
16 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
congestion, floorplanning, buffer insertion, routability |
16 | Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya |
Monotone bipartitioning problem in a planar point set with applications to VLSI. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
Complexity of algorithms, routing, very large scale integration (VLSI), partitioning, floorplanning |
16 | Evangeline F. Y. Young, Chris C. N. Chu, M. L. Ho |
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
placement constraint, physical design, floorplanning |
16 | Xiaobo Hu 0001, Danny Z. Chen, Rajeshkumar S. Sambandam |
Efficient list-approximation techniques for floorplan area minimization. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
k-link shortest paths, list approximation, floorplanning, area minimization |
16 | Wei-Jin Dai |
Hierarchical physical design methodology for multi-million gate chips. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
physical prototype, partitioning, placement, floorplanning, deep sub-micron, hierarchical design |
16 | Israel Koren |
Should Yield be a Design Objective? |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
routing, floorplanning, yield, compaction, critical area |
16 | P. Ghosh, Ramon Mangaser, C. Mark, Kenneth Rose |
Interconnect-Dominated VLSI Design. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
Microprocessor Performance Estimation, Interconnects, Floorplanning, VLSI Design, Repeater Insertion |
16 | Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro |
Improved Selay Prediction for On-Chip Buses. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
RC wiring delay, buffer optimization, high-level synthesis, floorplanning, interconnect optimization |
16 | Parthasarathi Dasgupta, Susmita Sur-Kolay |
Slicibility of rectangular graphs and floorplan optimization. |
ISPD |
1997 |
DBLP DOI BibTeX RDF |
graph dualization, nonslicible floorplans, slicible floorplans, very large scale integration, heuristic search, planar graphs, floorplanning |
16 | Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
A unified approach to topology generation and area optimization of general floorplans. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
VLSI floorplanning, AND-OR graphs, placement, heuristic search |
10 | Vassilios Gerousis |
Physical design implementation for 3D IC: methodology and tools. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv |
10 | Dipanjan Sengupta, Resve A. Saleh |
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
10 | David S. Kung 0001, Ruchir Puri |
CAD challenges for 3D ICs. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Zaichen Qian, Evangeline F. Y. Young |
Multi-voltage floorplan design with optimal voltage assignment. |
ISPD |
2009 |
DBLP DOI BibTeX RDF |
multi-voltage assignment optimization branch-and-bound |
10 | Debasri Saha, Susmita Sur-Kolay |
Encoding of Floorplans through Deterministic Perturbation. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Yinghai Lu, Hai Zhou 0001, Li Shang, Xuan Zeng 0001 |
Multicore parallel min-cost flow algorithm for CAD applications. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
min-cost flow, parallel programming, multicore |
10 | Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Case Study of Reliability-Aware and Low-Power Design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Maharaj Mukherjee, Kanad Chakraborty |
A Randomized Greedy Method for Rectangular-Pattern Fill Problems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Yong Zhan, Sachin S. Sapatnekar |
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong |
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
3D packing, microarchitecture, 3D integration, thermal |
10 | Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong |
Heuristic power/ground network and floorplan co-design method. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto |
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim |
A unified methodology for power supply noise reduction in modern microarchitecture design. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig |
Seamless design flow for reconfigurable systems. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
floorplanner, soft modules, zero deadspace, fixed-outline |
10 | Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001 |
Unified Incremental Physical-Level and High-Level Synthesis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim |
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
10 | M. Thenappan, Arasu T. Senthil, K. M. Sreekanth, Ramesh S. Guzar |
An Overlap Removal Algorithm for Macrocell Placement in VLSI Layouts. |
ICCTA |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong |
Interconnect Power Optimization Based on Timing Analysis. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shigetoshi Nakatake |
Structured Placement with Topological Regularity Evaluation. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Tien-Ting Fang, Ting-Chi Wang |
Fast Buffered Delay Estimation Considering Process Variations. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
statistical buffer insertion method, buffered delay estimation, first-order canonical forms, buffer blockages, deterministic delay estimation method, process variations |
10 | Jin Guo 0001, Antonis Papanikolaou, Francky Catthoor |
Topology exploration for energy efficient intra-tile communication. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Wai-Kei Mak, Jr-Wei Chen |
Voltage Island Generation under Performance Requirement for SoC Designs. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann |
A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han |
Performance modeling for early analysis of multi-core systems. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
early analysis, multi-core systems modeling, physical analysis, performance, power analysis, transaction-level modeling |
10 | Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar |
Module assignment for pin-limited designs under the stacked-Vdd paradigm. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong |
Fine grain 3D integration for microarchitecture design through cube packing exploration. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ali Jahanian 0001, Morteza Saheb Zamani |
Improved timing closure by early buffer planning in floor-placement design flow. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer planning, design convergence, buffer insertion |
10 | Sachin S. Sapatnekar |
Computer-aided design of 3d integrated circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Hongjie Bai, Sheqin Dong, Xianlong Hong |
Congestion Driven Buffer Planning for X-Architecture. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Zhuo Li 0001, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi |
Probabilistic Congestion Prediction with Partial Blockages. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane |
FABSYN: floorplan-aware bus architecture synthesis. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod |
Linear-programming-based techniques for synthesis of network-on-chip architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Erik Larsson, Zebo Peng |
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
test set selection, TAM design, power consumption, hot-spots, Test scheduling, design exploration |
10 | Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze |
Accurate estimation of global buffer delay within a floorplan. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Yuan Xie 0001, Wei-Lun Hung |
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
thermal-aware design, scheduling, embedded system design, system-on-chip design |
10 | Shengqi Yang, Wayne H. Wolf, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Reliability-Aware SOC Voltage Islands Partition and Floorplan. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller |
A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
digital film, stream-based architecture, weak-programming, FPGA, motion-estimation, reconfigurable |
10 | Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang |
An automated design flow for 3D microarchitecture evaluation. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai |
Design space exploration for minimizing multi-project wafer production cost. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
Physical design implementation of segmented buses to reduce communication energy. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Zhe Feng 0002, Yu Hu 0002, Tong Jing, Xianlong Hong, Xiaodong Hu 0001, Guiying Yan |
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. |
ISPD |
2006 |
DBLP DOI BibTeX RDF |
?-geometry, O(nlogn), Steiner tree construction, obstacle-avoiding |
10 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
Floorplan driven leakage power aware IP-based SoC design space exploration. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
floorplan, leakage power, temperature |
10 | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen 0001 |
Buffer planning based on block exchanging. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sheng-Ta Hsieh, Tsung-Ying Sun, Cheng-Wei Lin, Chun-Ling Lin |
Placement Constraints and Macrocell Overlap Removal Using Particle Swarm Optimization. |
ANTS Workshop |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Song Chen 0001, Takeshi Yoshimura |
On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
10 | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong |
Simultaneous power supply planning and noise avoidance in floorplan design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
10 | Renshen Wang, Sheqin Dong, Xianlong Hong |
An improved P-admissible floorplan representation based on Corner Block List. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
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