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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 502 occurrences of 325 keywords
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Results
Found 5680 publication records. Showing 5680 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin |
A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020, pp. 52-57, 2020, IEEE, 978-1-7281-5409-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Yuan Zhou 0011, Benwei Xu, Yun Chiu |
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(8), pp. 2207-2218, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo |
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 54(3), pp. 659-671, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Tsung-Chih Hung, Fan-Wei Liao, Tai-Haur Kuo |
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(11), pp. 1810-1814, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez |
A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9), pp. 3352-3364, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo |
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019, pp. 1-4, 2019, IEEE, 978-1-5386-9395-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Yuichiro Unno, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo |
Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: 2019 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2019, Taipei, Taiwan, December 3-6, 2019, pp. 1-2, 2019, IEEE, 978-1-7281-3038-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto |
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 53(11), pp. 3026-3038, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Kenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya |
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(9), pp. 1777-1787, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Vineeth Sarma, Nevin Alex Jacob, Bibhudatta Sahoo 0002, Venkateswaran Narayanaswamy, Vikas Choudhary |
A 250-MHz Pipelined ADC-Based fS/4 Noise-Shaping Bandpass ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6), pp. 1785-1794, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo |
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
20 | Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang |
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017, Leuven, Belgium, September 11-14, 2017, pp. 183-186, 2017, IEEE, 978-1-5090-5025-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult |
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(7), pp. 1592-1603, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Yao Liu 0003, Reza Lotfi, Yongchang Hu, Wouter A. Serdijn |
A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3), pp. 671-679, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi |
A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 153-156, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Jeffrey Fredenburg, Michael P. Flynn |
ADC trends and impact on SAR ADC architecture and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015, pp. 1-8, 2015, IEEE, 978-1-4799-8682-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
20 | Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer |
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 49(6), pp. 1366-1382, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Guanhua Wang, Foti Kacani, Yun Chiu |
IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 61-II(1), pp. 11-15, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult |
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014, pp. 67-70, 2014, IEEE, 978-1-4799-5694-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | John A. McNeill, Christopher L. David, Michael C. W. Coln, Ka Yan Chan, Cody Brenneman |
Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
I2MTC ![In: IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2013, Minneapolis, MN, USA, May 6-9, 2013, pp. 310-313, 2013, IEEE, 978-1-4673-4621-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong |
Multi-histogram ADC BIST System for ADC Linearity Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 22nd Asian Test Symposium, ATS 2013, Yilan County, Taiwan, November 18-21, 2013, pp. 213-214, 2013, IEEE Computer Society, 978-0-7695-5080-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Yuan-Fu Lyu, Chung-Yu Wu, Li-Chen Liu, Wei-Ming Chen |
A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 2046-2049, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
20 | Paolo Carbone |
Guest Editorial Special Section on IMEKO 2011 International Workshop on ADC Modeling, Testing and Data Converter Analysis and Design and the IEEE 2011 ADC Forum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 61(11), pp. 2858-2859, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon |
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 59-II(11), pp. 741-745, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi 0001 |
Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(7), pp. 1233-1236, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | John A. McNeill, Ka Yan Chan, Michael C. W. Coln, Christopher L. David, Cody Brenneman |
All-Digital Background Calibration of a Successive Approximation ADC Using the "Split ADC" Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10), pp. 2355-2365, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
20 | Young-Hwa Kim, Jaewon Lee, SeongHwan Cho |
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 4041-4044, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Yohei Tan, Satoshi Ito, Haruo Kobayashi 0001 |
Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, pp. 200-203, 2010, IEEE, 978-1-4244-7454-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
20 | John A. McNeill, Christopher L. David, Michael C. W. Coln, Rosa Croughwell |
"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 56-II(5), pp. 344-348, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Geert Van der Plas, Bob Verbruggen |
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008, pp. 242-243, 2008, IEEE, 978-1-4244-2010-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jipeng Li, Un-Ku Moon, John A. McNeill, Michael C. W. Coln, Brian J. Larivee |
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(6), pp. 1481, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Lukas Dörrer, Franz Kuttner, Patrizia Greco, Patrick Torta, Thomas Hartig |
A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(12), pp. 2416-2427, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | John A. McNeill, Michael C. W. Coln, Brian J. Larivee |
"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(12), pp. 2437-2445, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Vladimír Haasz, Jaroslav Roztocil, David Slepicka |
Evaluation of ADC testing systems using ADC transfer standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Instrum. Meas. ![In: IEEE Trans. Instrum. Meas. 54(3), pp. 1150-1155, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Stephen O'Driscoll, Teresa H. Meng |
Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005, pp. 301-304, 2005, IEEE, 0-7803-9066-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | A. Cruz Serra |
Introduction to the special issue on ADC testing, 6th EuroWorkshop on ADC Modelling and Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Stand. Interfaces ![In: Comput. Stand. Interfaces 25(1), pp. 1-2, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Philippe Cauvet |
Erratum to "Improving the dynamic measurements of ADC's using the 2-ADC method" [Computer standard and interfaces vol. 22 issue 4, 281-286]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Stand. Interfaces ![In: Comput. Stand. Interfaces 23(3), pp. 237, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Jiren Yuan, Crister Svensson |
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 29(8), pp. 866-872, August 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann |
An SOC platform for ADC test and measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 4-7, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Shun Li, Hua Chen, Feng Zhou |
A Novel Technique for Improving Temperature Independency of Ring-ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 694-697, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Andrea Agnes, Edoardo Bonizzoni, Franco Maloberti |
Design of an ultra-low power SA-ADC with medium/high resolution and speed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1-4, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang |
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(6), pp. 549-558, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Reconfigurable oscillator, Sinusoidal signal generator, Sigma-delta modulator |
19 | Andreas Mang, Oscar Camara 0001, Gisele Brasil-Caseiras, William R. Crum, Julia A. Schnabel, Thorsten M. Buzug, Jeremy Rees, John S. Thornton, Hans Rolf Jäger, David J. Hawkes |
Registration of Rcbv and Adc Maps with Structural and Physiological Mr Images in Glioma Patients: Study and Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: Proceedings of the 2007 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, Washington, DC, USA, April 12-16, 2007, pp. 37-40, 2007, IEEE, 1-4244-0672-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Erdem Serkan Erdogan, Sule Ozev |
An ADC-BiST scheme using sequential code analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 713-718, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Behnam Sedighi, Mehrdad Sharif Bakhtiar |
An 8-bit Switched-Resistor Pipeline ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1963-1966, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot |
A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 485-488, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Soon-Ik Cho, Suki Kim, Shin-Il Lim, Kwang-Hyun Baek |
A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3379-3382, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire |
On-Line Histogram Equalization for Flash ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3598-3601, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jiri Haze, Lukas Fujcik, Ondrej Sajdl, Radimir Vrba |
Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICN/ICONS/MCL ![In: Fifth International Conference on Networking and the International Conference on Systems (ICN / ICONS / MCL 2006), 23-29 April 2006, Mauritius, pp. 180, 2006, IEEE Computer Society, 0-7695-2552-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | B. Tavassoli, Omid Shoaei |
Digital background calibration of pipeline ADC with open-loop gain stage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Yu M. Chi, Udayan Mallik, Edward Choi, Matthew A. Clapp, G. Gauwenberghs, Ralph Etienne-Cummings |
CMOS pixel-level ADC with change detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Vincenzo Ferragina, Nicola Ghittori, Franco Maloberti |
Low-power 6-bit flash ADC for high-speed data converters architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud |
A nanowatt ADC for ultra low power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Kati Virtanen, Mikko Pänkäälä, Mika Laiho, Ari Paasio |
Implementation of an asynchronous current-mode ADC with adaptive quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Josh Carnes, Un-Ku Moon |
The effect of switch resistance on pipelined ADC MDAC settling time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta |
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Xian Ping Fan, Pak Kwong Chan |
Improving Source-Follower Buffer for High-Speed ADC Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 21-24, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Ludovic Barrandon, Samuel Crand, Dominique Houzet |
Systematic Figure of Merit Computation for the Design of Pipeline ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 277-278, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin |
A 120nm low power asynchronous ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 60-65, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous technology, level-crossing sampling, analog-to-digital conversion |
19 | Bruno Vaz, João Goes, R. Piloto, J. Neto, Rui Monteiro, Nuno Paulino 0002 |
A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4074-4077, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger |
A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 784-787, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hanjun Jiang, Degang Chen 0001, Randall L. Geiger |
Dither incorporated deterministic dynamic element matching for high resolution ADC test using extremely low resolution DACs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4285-4288, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hsin-Hung Ou, Bin-Da Liu |
A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1972-1975, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jannik Hammel Nielsen, Pietro Andreani, Piero Malcovati, Andrea Baschirotto |
Technology scaling impact on embedded ADC design for telecom receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4614-4617, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Kati Virtanen, Mikko Pänkäälä, Ari Paasio |
A current-mode ADC with adaptive quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3115-3118, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala |
A New Test Methodology For DNL Error In Flash ADC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 582-590, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Daniela De Venuto, Grazia Marchione, Leonardo Reyneri |
A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 440-447, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Syed Masood Ali, Rabin Raut, Mohamad Sawan |
A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada, pp. 123-126, 2005, IEEE Computer Society, 0-7695-2403-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jiri Haze, Radimir Vrba |
ADC Position-Sense Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 11th IEEE International Conference on the Engineering of Computer-Based Systems (ECBS 2004), 24-27 May 2004, Brno, Czech Republic, pp. 429-434, 2004, IEEE Computer Society, 0-7695-2125-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu |
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 252-256, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator |
19 | Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio |
A gray-code current-mode ADC for mixed-mode cellular computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 81-84, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger |
Parameter optimization of deterministic dynamic element matching DACs for accurate and cost-effective ADC testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 924-927, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ralph Mason, Chris DeVries, Eugene Ivanov |
An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 477-480, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell |
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 469-479, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell |
A New Methodology For ADC Test Flow Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 201-209, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | R. Batten, Terri S. Fiez |
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 715-718, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Hung-Kai Chen 0001, Chih-Hu Wang, Chau-Chin Su |
A Self Calibrated ADC BIST Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 117-122, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Vittaya Tipsuwanporn, Arjin Numsomran, W. Chuchotsakunleot, S. Chuenarom, S. Maitreechit |
Algorithmic ADC using current mode without DAC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 453-456, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Peter Kiss, Un-Ku Moon, Jesper Steensgaard, John T. Stonick, Gabor C. Temes |
Multibit Sigma-Delta ADC with mixed-mode DAC error correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 280-283, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Alex R. Bugeja, Sung-Ung Kwak |
Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 428-431, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas |
Self-Testable Pipelined ADC with Low Hardware Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 272-278, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Sanjay Mohan, Michael L. Bushnell |
A Code Transition Delay Model for ADC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 274-282, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand |
Hardware Resource Minimization for Histogram-Based ADC BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 247-254, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Kantilal Bacrania, Tzi-Hsiung Shu |
A CMOS 10 b 60 Msample/s ADC with ultra fast gain control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 55-58, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen |
A 2.5 V 10 bit SAR ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 525-526, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani |
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adc, sd card, fpga, real-time, multiplexing, data acquisition, fft |
19 | Byoungho Kim, Nash Khouzam, Jacob A. Abraham |
Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 293-298, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Loopback Test, Aperture Jitter, Digital-to-Analog Converter, Analog-to-Digital Converter, ADC, Mixed-Signal Testing, DAC |
19 | Jamiil Tourabaly, Adam Osseiran |
A Jittered-Sampling Correction Technique for ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 249-252, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Jitter correction, data converters, ADC |
19 | Tao Wang, Liping Liang |
Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 79-84, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ADC, continuous time, wide band, sigma delta |
19 | Chia-han Lee, Wayne H. Wolf |
Design Methodology for Software Radio Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings, pp. 355-364, 2007, Springer, 978-3-540-73622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
baseband, methodology, convex optimization, ADC, RF, front-ends, Software radio |
19 | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell |
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(3), pp. 234-243, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
DFT, ADC, mixed-signal testing, SiP, DAC, system-in-package |
19 | Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy |
High Speed Curve Interpolating D/A Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 38(1), pp. 5-11, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI, interpolation, interpolator, DSP, digital, linear, circuits, ADC, curve, DAC |
19 | Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown |
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 520-525, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low voltage analog, varactor, low power, SoC, system-on-chip, design methodology, MEMS, microcontroller, ADC, mixed-signal, PGA, microsystem, SD, inductor, clock generation |
19 | Omid Oliaei |
Oversampled gain-boosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 221-226, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MOS amplifier, gain boosting, gain enhancement, switched-capacitor, bootstrapping, ADC, DAC, OTA, sigma-delta |
19 | Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka |
Ultrahigh-Speed Circuits Using Resonant Tunneling Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 150-153, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
HEMT, D-FF, optoelectronic circuit, ADC, resonant tunneling diode |
18 | Hsiu-Ming Chang 0001, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu |
An error tolerance scheme for 3D CMOS imagers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 917-922, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
image sensor, error tolerance, 3D IC |
18 | Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko |
Experience in Virtual Testing of RSD cyclic A/D converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 178-181, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Hervé Boisgontier, Vincent Noblet, Félix Renard, Fabrice Heitz, Lucien Rumbach, Jean-Paul Armspach |
Statistical Detection of Longitudinal Changes between Apparent Diffusion Coefficient Images: Application to Multiple Sclerosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICCAI (1) ![In: Medical Image Computing and Computer-Assisted Intervention - MICCAI 2009, 12th International Conference, London, UK, September 20-24, 2009, Proceedings, Part I, pp. 959-966, 2009, Springer, 978-3-642-04267-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | Hsiu-Ming Chang 0001, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng |
A Built-in self-calibration scheme for pipelined ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 266-271, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
18 | David Grant, Guy G. Lemieux |
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(3), pp. 16:1-16:24, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Automated development tools, hardware-supporting software, testing, graph algorithms, design automation, place and route |
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