Search results for "ADC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin	A 0.8V 875 MS/s 7b low-power SAR ADC for ADC-Based Wireline Receivers in 22nm FDSOI.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
20	Yuan Zhou 0011, Benwei Xu, Yun Chiu	A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
20	Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo	A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
20	Tsung-Chih Hung, Fan-Wei Liao, Tai-Haur Kuo	A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
20	Mohammad H. Naderi, Chulhyun Park, Suraj Prakash, Martin Kinyua, Eric G. Soenen, José Silva-Martínez	A 27.7 fJ/conv-step 500 MS/s 12-Bit Pipelined ADC Employing a Sub-ADC Forecasting Technique and Low-Power Class AB Slew Boosted Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
20	Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo	A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE.	CICC	2019	DBLP DOI BibTeX RDF
20	Yuichiro Unno, Tatsuji Matsuura, Ryo Kishida, Akira Hyogo	Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy.	ISPACS	2019	DBLP DOI BibTeX RDF
20	Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto	A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
20	Kenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya	A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
20	Vineeth Sarma, Nevin Alex Jacob, Bibhudatta Sahoo 0002, Venkateswaran Narayanaswamy, Vikas Choudhary	A 250-MHz Pipelined ADC-Based fS/4 Noise-Shaping Bandpass ADC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
20	Shiva Kiran, Shengchang Cai, Ying Luo 0010, Sebastian Hoyos, Samuel Palermo	A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE.	CICC	2018	DBLP DOI BibTeX RDF
20	Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang	Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.	ESSCIRC	2017	DBLP DOI BibTeX RDF
20	Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult	A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
20	Yao Liu 0003, Reza Lotfi, Yongchang Hu, Wouter A. Serdijn	A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
20	Hasan Molaei, Ata Khorami, Mohammad S. Eslampanah Sendi, Khosrow Hajsadeghi	A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application.	ICECS	2015	DBLP DOI BibTeX RDF
20	Jeffrey Fredenburg, Michael P. Flynn	ADC trends and impact on SAR ADC architecture and analysis.	CICC	2015	DBLP DOI BibTeX RDF
20	Soon-Kyun Shin, Jacques Christophe Rudell, Denis C. Daly, Carlos E. Muñoz, Dong-Young Chang, Kush Gulati, Hae-Seung Lee, Matthew Z. Straayer	A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
20	Guanhua Wang, Foti Kacani, Yun Chiu	IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
20	Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult	A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.	ESSCIRC	2014	DBLP DOI BibTeX RDF
20	John A. McNeill, Christopher L. David, Michael C. W. Coln, Ka Yan Chan, Cody Brenneman	Split ADC background self-calibration of a 16-b successive approximation ADC in 180nm CMOS.	I2MTC	2013	DBLP DOI BibTeX RDF
20	Koay Soon Chan, Nuzrul Fahmi Nordin, Kim Chon Chan, Terk Zyou Lok, Chee Wai Yong	Multi-histogram ADC BIST System for ADC Linearity Testing.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
20	Yuan-Fu Lyu, Chung-Yu Wu, Li-Chen Liu, Wei-Ming Chen	A Low power 10bit 500kS/s delta-modulated SAR ADC (DMSAR ADC) for implantable medical devices.	ISCAS	2013	DBLP DOI BibTeX RDF
20	Paolo Carbone	Guest Editorial Special Section on IMEKO 2011 International Workshop on ADC Modeling, Testing and Data Converter Analysis and Design and the IEEE 2011 ADC Forum.	IEEE Trans. Instrum. Meas.	2012	DBLP DOI BibTeX RDF
20	Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon	A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
20	Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Satoshi Ito, Yohei Tan, Haruo Kobayashi 0001	Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
20	John A. McNeill, Ka Yan Chan, Michael C. W. Coln, Christopher L. David, Cody Brenneman	All-Digital Background Calibration of a Successive Approximation ADC Using the "Split ADC" Architecture.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
20	Young-Hwa Kim, Jaewon Lee, SeongHwan Cho	A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages.	ISCAS	2010	DBLP DOI BibTeX RDF
20	Takuya Yagi, Kunihiko Usui, Tatsuji Matsuura, Satoshi Uemori, Yohei Tan, Satoshi Ito, Haruo Kobayashi 0001	Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure.	APCCAS	2010	DBLP DOI BibTeX RDF
20	John A. McNeill, Christopher L. David, Michael C. W. Coln, Rosa Croughwell	"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
20	Geert Van der Plas, Bob Verbruggen	A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC.	ISSCC	2008	DBLP DOI BibTeX RDF
20	Jipeng Li, Un-Ku Moon, John A. McNeill, Michael C. W. Coln, Brian J. Larivee	Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
20	Lukas Dörrer, Franz Kuttner, Patrizia Greco, Patrick Torta, Thomas Hartig	A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
20	John A. McNeill, Michael C. W. Coln, Brian J. Larivee	"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
20	Vladimír Haasz, Jaroslav Roztocil, David Slepicka	Evaluation of ADC testing systems using ADC transfer standard.	IEEE Trans. Instrum. Meas.	2005	DBLP DOI BibTeX RDF
20	Stephen O'Driscoll, Teresa H. Meng	Adaptive ADC design for neuro-prosthetic interfaces: base ADC cell.	ECCTD	2005	DBLP DOI BibTeX RDF
20	A. Cruz Serra	Introduction to the special issue on ADC testing, 6th EuroWorkshop on ADC Modelling and Testing.	Comput. Stand. Interfaces	2003	DBLP DOI BibTeX RDF
20	Philippe Cauvet	Erratum to "Improving the dynamic measurements of ADC's using the 2-ADC method" [Computer standard and interfaces vol. 22 issue 4, 281-286].	Comput. Stand. Interfaces	2001	DBLP DOI BibTeX RDF
20	Jiren Yuan, Crister Svensson	A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
19	Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann	An SOC platform for ADC test and measurement.	DDECS	2009	DBLP DOI BibTeX RDF
19	Shun Li, Hua Chen, Feng Zhou	A Novel Technique for Improving Temperature Independency of Ring-ADC.	DATE	2008	DBLP DOI BibTeX RDF
19	Andrea Agnes, Edoardo Bonizzoni, Franco Maloberti	Design of an ultra-low power SA-ADC with medium/high resolution and speed.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang	Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reconfigurable oscillator, Sinusoidal signal generator, Sigma-delta modulator
19	Andreas Mang, Oscar Camara 0001, Gisele Brasil-Caseiras, William R. Crum, Julia A. Schnabel, Thorsten M. Buzug, Jeremy Rees, John S. Thornton, Hans Rolf Jäger, David J. Hawkes	Registration of Rcbv and Adc Maps with Structural and Physiological Mr Images in Glioma Patients: Study and Validation.	ISBI	2007	DBLP DOI BibTeX RDF
19	Erdem Serkan Erdogan, Sule Ozev	An ADC-BiST scheme using sequential code analysis.	DATE	2007	DBLP DOI BibTeX RDF
19	Behnam Sedighi, Mehrdad Sharif Bakhtiar	An 8-bit Switched-Resistor Pipeline ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Yi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot	A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Soon-Ik Cho, Suki Kim, Shin-Il Lim, Kwang-Hyun Baek	A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire	On-Line Histogram Equalization for Flash ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Jiri Haze, Lukas Fujcik, Ondrej Sajdl, Radimir Vrba	Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
19	B. Tavassoli, Omid Shoaei	Digital background calibration of pipeline ADC with open-loop gain stage.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Yu M. Chi, Udayan Mallik, Edward Choi, Matthew A. Clapp, G. Gauwenberghs, Ralph Etienne-Cummings	CMOS pixel-level ADC with change detection.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Vincenzo Ferragina, Nicola Ghittori, Franco Maloberti	Low-power 6-bit flash ADC for high-speed data converters architectures.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A nanowatt ADC for ultra low power applications.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Kati Virtanen, Mikko Pänkäälä, Mika Laiho, Ari Paasio	Implementation of an asynchronous current-mode ADC with adaptive quantization.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Josh Carnes, Un-Ku Moon	The effect of switch resistance on pipelined ADC MDAC settling time.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta	An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Xian Ping Fan, Pak Kwong Chan	Improving Source-Follower Buffer for High-Speed ADC Testing.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Ludovic Barrandon, Samuel Crand, Dominique Houzet	Systematic Figure of Merit Computation for the Design of Pipeline ADC.	DATE	2005	DBLP DOI BibTeX RDF
19	Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin	A 120nm low power asynchronous ADC.	ISLPED	2005	DBLP DOI BibTeX RDF	asynchronous technology, level-crossing sampling, analog-to-digital conversion
19	Bruno Vaz, João Goes, R. Piloto, J. Neto, Rui Monteiro, Nuno Paulino 0002	A low-voltage 3 mW 10-bit 4MS/s pipeline ADC in digital CMOS for sensor interfacing.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
19	Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger	A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
19	Hanjun Jiang, Degang Chen 0001, Randall L. Geiger	Dither incorporated deterministic dynamic element matching for high resolution ADC test using extremely low resolution DACs.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Hsin-Hung Ou, Bin-Da Liu	A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Jannik Hammel Nielsen, Pietro Andreani, Piero Malcovati, Andrea Baschirotto	Technology scaling impact on embedded ADC design for telecom receivers.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
19	Kati Virtanen, Mikko Pänkäälä, Ari Paasio	A current-mode ADC with adaptive quantization.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
19	Michael Wieckowski, John C. Liobe, Quentin Diduck, Martin Margala	A New Test Methodology For DNL Error In Flash ADC's.	DFT	2005	DBLP DOI BibTeX RDF
19	Daniela De Venuto, Grazia Marchione, Leonardo Reyneri	A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC.	ISQED	2005	DBLP DOI BibTeX RDF
19	Syed Masood Ali, Rabin Raut, Mohamad Sawan	A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture.	IWSOC	2005	DBLP DOI BibTeX RDF
19	Jiri Haze, Radimir Vrba	ADC Position-Sense Interface.	ECBS	2004	DBLP DOI BibTeX RDF
19	Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu	A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.	ISLPED	2004	DBLP DOI BibTeX RDF	CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator
19	Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio	A gray-code current-mode ADC for mixed-mode cellular computer.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
19	Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger	Parameter optimization of deterministic dynamic element matching DACs for accurate and cost-effective ADC testing.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
19	Ralph Mason, Chris DeVries, Eugene Ivanov	An RF sub-sampling mixer, PGA and Sigma Delta ADC for conversion at 900 MHz.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
19	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF
19	Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell	A New Methodology For ADC Test Flow Optimization.	ITC	2003	DBLP DOI BibTeX RDF
19	R. Batten, Terri S. Fiez	An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
19	Hung-Kai Chen 0001, Chih-Hu Wang, Chau-Chin Su	A Self Calibrated ADC BIST Methodology.	VTS	2002	DBLP DOI BibTeX RDF
19	Vittaya Tipsuwanporn, Arjin Numsomran, W. Chuchotsakunleot, S. Chuenarom, S. Maitreechit	Algorithmic ADC using current mode without DAC.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
19	Peter Kiss, Un-Ku Moon, Jesper Steensgaard, John T. Stonick, Gabor C. Temes	Multibit Sigma-Delta ADC with mixed-mode DAC error correction.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
19	Alex R. Bugeja, Sung-Ung Kwak	Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
19	Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas	Self-Testable Pipelined ADC with Low Hardware Overhead.	VTS	2001	DBLP DOI BibTeX RDF
19	Sanjay Mohan, Michael L. Bushnell	A Code Transition Delay Model for ADC Test.	VLSI Design	2001	DBLP DOI BibTeX RDF
19	Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand	Hardware Resource Minimization for Histogram-Based ADC BIST.	VTS	2000	DBLP DOI BibTeX RDF
19	Kantilal Bacrania, Tzi-Hsiung Shu	A CMOS 10 b 60 Msample/s ADC with ultra fast gain control.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
19	Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen	A 2.5 V 10 bit SAR ADC.	VLSI Design	1997	DBLP DOI BibTeX RDF
19	Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani	Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller.	FPGA	2009	DBLP DOI BibTeX RDF	adc, sd card, fpga, real-time, multiplexing, data acquisition, fft
19	Byoungho Kim, Nash Khouzam, Jacob A. Abraham	Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Loopback Test, Aperture Jitter, Digital-to-Analog Converter, Analog-to-Digital Converter, ADC, Mixed-Signal Testing, DAC
19	Jamiil Tourabaly, Adam Osseiran	A Jittered-Sampling Correction Technique for ADCs.	DELTA	2008	DBLP DOI BibTeX RDF	Jitter correction, data converters, ADC
19	Tao Wang, Liping Liang	Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR.	DELTA	2008	DBLP DOI BibTeX RDF	ADC, continuous time, wide band, sigma delta
19	Chia-han Lee, Wayne H. Wolf	Design Methodology for Software Radio Systems.	SAMOS	2007	DBLP DOI BibTeX RDF	baseband, methodology, convex optimization, ADC, RF, front-ends, Software radio
19	Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell	A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	DFT, ADC, mixed-signal testing, SiP, DAC, system-in-package
19	Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy	High Speed Curve Interpolating D/A Converter.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	VLSI, interpolation, interpolator, DSP, digital, linear, circuits, ADC, curve, DAC
19	Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown	A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference.	DAC	2003	DBLP DOI BibTeX RDF	low voltage analog, varactor, low power, SoC, system-on-chip, design methodology, MEMS, microcontroller, ADC, mixed-signal, PGA, microsystem, SD, inductor, clock generation
19	Omid Oliaei	Oversampled gain-boosting.	ISLPED	2002	DBLP DOI BibTeX RDF	MOS amplifier, gain boosting, gain enhancement, switched-capacitor, bootstrapping, ADC, DAC, OTA, sigma-delta
19	Masafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka	Ultrahigh-Speed Circuits Using Resonant Tunneling Devices.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	HEMT, D-FF, optoelectronic circuit, ADC, resonant tunneling diode
18	Hsiu-Ming Chang 0001, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu	An error tolerance scheme for 3D CMOS imagers.	DAC	2010	DBLP DOI BibTeX RDF	image sensor, error tolerance, 3D IC
18	Miloslav Kubar, Ondrej Subrt, Pravoslav Martínek, Jiri Jakovenko	Experience in Virtual Testing of RSD cyclic A/D converters.	DDECS	2009	DBLP DOI BibTeX RDF
18	Hervé Boisgontier, Vincent Noblet, Félix Renard, Fabrice Heitz, Lucien Rumbach, Jean-Paul Armspach	Statistical Detection of Longitudinal Changes between Apparent Diffusion Coefficient Images: Application to Multiple Sclerosis.	MICCAI (1)	2009	DBLP DOI BibTeX RDF
18	Hsiu-Ming Chang 0001, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng	A Built-in self-calibration scheme for pipelined ADCs.	ISQED	2009	DBLP DOI BibTeX RDF
18	David Grant, Guy G. Lemieux	Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Automated development tools, hardware-supporting software, testing, graph algorithms, design automation, place and route