Search results for "ASIC"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Jun Huang, Ning Ning 0002, Renxiong Li, Qi Ding, Yutuo Guo, Yu Wang, Kunqin He, Yaxin Liu, Lulu Peng	An Ultra-Low Specific On-Resistance LDMOS With Segmented LOCOS In 0.18 μm BCD Process Platform.	ASICON	2023	DBLP DOI BibTeX RDF
14	Jyi-Tsong Lin, Kuan-Pin Lin	A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact.	ASICON	2023	DBLP DOI BibTeX RDF
14	Maolin Pan, Luyu Wang, Qiang Wang, Penghao Zhang, Yuhang Wang, Min Xu	Monolithic Logic Units based on DCFL Structure on p-GaN platform for GaN ICs.	ASICON	2023	DBLP DOI BibTeX RDF
14	Xuanqi Li, Takashi Imagawa, Hiroyuki Ochi	Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction.	ASICON	2023	DBLP DOI BibTeX RDF
14	Yichen Ouyang, Xianglong Wang, Gang Shi, Lei Chen 0001, Fengwei An	A Dynamic Codec with Adaptive Quantization for Convolution Neural Network.	ASICON	2023	DBLP DOI BibTeX RDF
14	Han Wu 0003, Miaolin Zhang, Zhichun Shao, Jiaqi Guo, Kian Ann Ng, Liwei Lin, Jerald Yoo	An Ultrasound ASIC With Universal Energy Recycling for >7-m All-Weather Metamorphic Robotic Vision.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
14	Yannick M. Hopf, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-Yao Chang, Chao Chen 0019, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs	A Pitch-Matched Transceiver ASIC With Shared Hybrid Beamforming ADC for High-Frame-Rate 3-D Intracardiac Echocardiography.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
14	Atakan Dogan, Kemal Ebcioglu	Cloud Building Block Chip for Creating FPGA and ASIC Clouds.	ACM Trans. Reconfigurable Technol. Syst.	2022	DBLP DOI BibTeX RDF
14	Takaki Asanuma, Takanori Isobe 0001	A Proof of Work based on Preimage Problem of Variants of SHA-3 with ASIC Resistance.	J. Inf. Process.	2022	DBLP DOI BibTeX RDF
14	Loukas Petrou, Julius Georgiou	An ASIC Architecture With Inter-Chip Networking for Individual Control of Adaptive-Metamaterial Cells.	IEEE Access	2022	DBLP DOI BibTeX RDF
14	Sun Sik Lee, Thanh Dat Nguyen, Pramod Kumar Meher, Sang Yoon Park	Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design.	IEEE Access	2022	DBLP DOI BibTeX RDF
14	Rohit B. Chaurasiya, Rahul Shrestha	Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
14	Vahhab Samadi Bokharaie, Ali Jahanian 0001	Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
14	Yuntao Liu, Shuo Fang, Ying Wang	A Novel Time-Multiplexed Fully Differential Interface ASIC With Strong Nonlinear Suppression for MEMS Accelerometers.	IEEE Trans. Instrum. Meas.	2022	DBLP DOI BibTeX RDF
14	Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula	A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
14	Brady Taylor, Qilin Zheng, Ziru Li, Shiyu Li, Yiran Chen 0001	Processing-in-Memory Technology for Machine Learning: From Basic to ASIC.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
14	Ahmet Can Mert, Erdinç Öztürk, Erkay Savas	Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Evaluation.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
14	Raju Machupalli, Masum Hossain, Mrinal Kr. Mandal	Review of ASIC accelerators for deep neural network.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
14	Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma 0001	Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
14	Deepu S. P., M. Ramesh Kini, David S. Sumam	Design and implementation of a signal processing ASIC for digital hearing aids.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
14	Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthalaa, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva 0001, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão 0001	A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures.	IEEE Commun. Surv. Tutorials	2022	DBLP DOI BibTeX RDF
14	Ahmad Rezvanitabar, M. Sait Kilinc, Coskun Tekes, Evren F. Arkan, Maysam Ghovanloo, F. Levent Degertekin	An Adaptive Element-Level Impedance-Matched ASIC With Improved Acoustic Reflectivity for Medical Ultrasound Imaging.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Hyochan An, Samuel R. Nason-Tomaszewski, Jongyup Lim, Kyumin Kwon, Matthew S. Willsey, Parag G. Patil, Hun-Seok Kim, Dennis Sylvester, Cynthia A. Chestek, David T. Blaauw	A Power-Efficient Brain-Machine Interface System With a Sub-mw Feature Extraction and Decoding ASIC Demonstrated in Nonhuman Primates.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Jay V. Shah, Christopher J. Quinkert, Brett Collar, Michael T. Williams, Ethan N. Biggs, Pedro P. Irazoqui	A Highly Miniaturized, Chronically Implanted ASIC for Electrical Nerve Stimulation.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	Syed Muhammad Abubakar, Yue Yin, Songyao Tan, Hanjun Jiang, Zhihua Wang 0001	A 746 nW ECG Processor ASIC Based on Ternary Neural Network.	IEEE Trans. Biomed. Circuits Syst.	2022	DBLP DOI BibTeX RDF
14	B. Naresh Kumar Reddy, B. Seetharamulu, G. Siva Krishna, B. Veena Vani	An FPGA and ASIC Implementation of Cubing Architecture.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
14	Rohit B. Chaurasiya, Rahul Shrestha	Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network.	IEEE Trans. Consumer Electron.	2022	DBLP DOI BibTeX RDF
14	Ibrahim Farhat, Wassim Hamidouche, Adrien Grill, Daniel Ménard, Olivier Déforges	Adaptive Loop Filter Hardware Design for 4K ASIC VVC Decoders.	IEEE Trans. Consumer Electron.	2022	DBLP DOI BibTeX RDF
14	Ievgen Kabin, Zoya Dyka, Dan Klann, Peter Langendoerfer	Horizontal Attacks against ECC: from Simulations to ASIC.	CoRR	2022	DBLP BibTeX RDF
14	Ankit Wagle, Gian Singh, Sunil P. Khatri, Sarma B. K. Vrudhula	A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard Cells.	CoRR	2022	DBLP DOI BibTeX RDF
14	Ievgen Kabin, Zoya Dyka, Dan Klann, Nele Mentens, Lejla Batina, Peter Langendoerfer	Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves.	CoRR	2022	DBLP BibTeX RDF
14	Takaki Asanuma, Takanori Isobe 0001	A Proof of Work Based on Key Recovery Problem of Cascade Block Ciphers with ASIC Resistance.	IEICE Trans. Inf. Syst.	2022	DBLP DOI BibTeX RDF
14	Daniel Fallnich, Shutao Zhang, Tobias Gemmeke	Efficient ASIC Architectures for Low Latency Niederreiter Decryption.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
14	Jay V. Shah, Brett Collar, Ella Ditslear, Pedro P. Irazoqui	An ASIC System for Closed-Loop Blood Pressure Modulation Through Right Cervical Vagus Nerve Stimulation.	IEEE Trans. Biomed. Eng.	2022	DBLP DOI BibTeX RDF
14	Maolei Zhou, Chresten von der Heide, Andreas Dietzel	Four-Level Micro-Via Technology (4LµV) for ASIC Integration in Active Flexible Sensor Arrays.	Sensors	2022	DBLP DOI BibTeX RDF
14	Carlos Abellan Beteta, Dimitra Andreou, Marina Artuso, Andy Beiter, Steven Blusk, Roma Bugiel, Szymon Bugiel, Antonio Carbone, Ina Carli, Bo Chen, Nadim Conti, Federico De Benedetti, Shuchong Ding, Scott Ely, Miroslaw Firlej, Tomasz Fiutowski, Paolo Gandini, Danielle Germann, Nathan Grieser, Marek Idzik, Xiaojie Jiang, Wojciech Krupa, Yiming Li, Zhuoming Li, Xixin Liang, Shuaiyi Liu, Yu Lu, Lauren Mackey, Jakub Moron, Ray Mountain, Marco Petruzzo, Hang Pham, Burkhard Schmidt 0003, Shuqi Sheng, Elisabetta Spadaro Norella, Krzysztof Swientek, Tomasz Szumlak, Mark Tobin, Jianchun Wang, Michael Wilkinson, Hangyi Wu, Feihao Zhang, Quan Zou 0005	The SALT - Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment.	Sensors	2022	DBLP DOI BibTeX RDF
14	Silvia Tedesco	A Low-Power, Short Dead-Time ASIC for SiPMs Readout with 200 MS/s Sampling Rate.	PRIME	2022	DBLP DOI BibTeX RDF
14	Mohd. Tasleem Khan, Oscar Gustafsson	ASIC Implementation Trade-Offs for High-Speed LMS and Block LMS Adaptive Filters.	MWSCAS	2022	DBLP DOI BibTeX RDF
14	Meriem Bettayeb, Huruy Tekle Tesfai, Baker Mohammad, Hani H. Saleh	ASIC-Based Implementation of Random Spray Retinex Algorithm for Image Enhancement.	MWSCAS	2022	DBLP DOI BibTeX RDF
14	James D. Rosenthal, Arindam Mandal, Visvesh Sathe 0001, Matthew S. Reynolds	An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS.	RFID	2022	DBLP DOI BibTeX RDF
14	Francisco Rodrigues, João Santos 0007, Carla Rodrigues, António Luis Jesus Teixeira	Hybrid PIC+ASIC quasi-coherent receiver for TWDM-PON.	CSNDSP	2022	DBLP DOI BibTeX RDF
14	Tiago D. Perez, Marcio M. Gonçalves, Leonardo Gobatto, Marcelo Brandalero, José Rodrigo Azambuja, Samuel Pagliarini	G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators.	DATE	2022	DBLP DOI BibTeX RDF
14	Jiahui Shi, Hua Liao, Bowen Xing, Bin Zhou, Qi Wei 0001, Rong Zhang 0005	A Fully Integrated Miniatured Capacitive Angle Encoder based on MEMS Fabrication and ASIC Implementation.	IEEE SENSORS	2022	DBLP DOI BibTeX RDF
14	Marco Grassi, Alessandro Gemelli, Piero Malcovati, Filippo Mele, Irisa Dedolli, Massimo Gandola, Giuseppe Bertuccio, Ezequiel Marchesini, Enrico Virgilli, Riccardo Campana, Fabio Fuschino, Claudio Labanti, Lorenzo Amati	Experimental Characterization of the ORION ASIC: The Read-Out Circuit for X-γ-Ray Detection of the THESEUS Mission Spectrometer.	I2MTC	2022	DBLP DOI BibTeX RDF
14	Antti Rautakoura, Timo Hämäläinen 0001, Ari Kulmala, Tero Lehtinen, Mehdi Duman, Mohamed Ibrahim	Ballast: Implementation of a Large MP-SoC on 22nm ASIC Technology.	DSD	2022	DBLP DOI BibTeX RDF
14	Renzo Barraza, Angel Abusleme, Sergey Kuleshov	TISIRC: A multichannel ASIC with gain control for SiPM detectors.	LASCAS	2022	DBLP DOI BibTeX RDF
14	Maryam Habibollahi, Dai Jiang, Henry Lancashire, Andreas Demosthenous	A Bidirectional ASIC for Active Microchannel Neural Interfaces.	ICECS 2022	2022	DBLP DOI BibTeX RDF
14	Divyasree Tummalapalli, Kunapareddy Chiranjeevi, Vikas Akalwadi, Rahul Govindan, Balaji G	Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning.	ICECS 2022	2022	DBLP DOI BibTeX RDF
14	Marco Bestetti, Andrea Giovanni Bonfanti, Luca Falorni, Matteo Gianollo, Christian Padovani, Giacomo Langfelder	Full-digital output ASIC for Lissajous Frequency Modulated MEMS Gyroscopes.	ICECS 2022	2022	DBLP DOI BibTeX RDF
14	B. Bijelic, M. Hercog, Goran Horvat, Ivan Ostheimer, Marko Vukobratovic	Modeling Energy Aspects of ASIC Hardware for PoW Applications.	MIPRO	2022	DBLP DOI BibTeX RDF
14	L. Zupan, Ivan Ostheimer, F. Horvat, Marko Vukobratovic	Small Energy Prosumer Revenue Diversification with ASIC hardware.	MIPRO	2022	DBLP DOI BibTeX RDF
14	Shuenn-Yuh Lee, Hao-Yun Lee, Ding-Siang Ciou, Zhan-Xian Liao, Peng-Wei Huang, Yi-Ting Hsieh, Yi-Chieh Wei, Chia-Yu Lin, Meng-Dar Shieh, Ju-Yi Chen	A Wireless Urine Detection System and Platform with Power-Efficient Electrochemical Readout ASIC and ABTS-CNT Biosensor.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
14	Johannes Bastl, Zhihong Lei, Jonas Meier, Ralf Wunderlich, Stefan Heinen	A Design Flow and EDA-Tool for an Automated Implementation of ASIC Configuration Interfaces.	SMACD	2022	DBLP DOI BibTeX RDF
14	Ibrahim Farhat, Wassim Hamidouche, Adrien Grill, Daniel Ménard, Olivier Déforges	Efficient HW Design of Adaptive Loop Filter for 4k ASIC VVC Encoder.	PCS	2022	DBLP DOI BibTeX RDF
14	Guo-Ming Sung, Chao-Rong Chen, Mao-Hsun Tien, Chwan-Lu Tseng, Ching-Yin Lee, Chih-Ping Yu	Predictive Direct Torque Control ASIC of Three-Phase Induction Motor Using Speed-Sensorless Control and Neural Network Proportional-Integral-Derivative Controller.	SMC	2022	DBLP DOI BibTeX RDF
14	William Lemaire, Esmaeil Ranjbar Koleibi, Takwa Omrani, Maher Benhouria, Konin Koua, Charles Quesnel, Louis-Philippe Gauthier, Jérémy Ménard, Keven Gagnon, Sébastien Roy 0002, Réjean Fontaine	Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS.	NEWCAS	2022	DBLP DOI BibTeX RDF
14	Frederik Dreyer, Daniel Krüger, Sander Baas, Aldrik H. Velders, Jens Anders	A broadband transceiver ASIC for X-nuclei NMR spectroscopy in 0.13 µm BiCMOS.	NEWCAS	2022	DBLP DOI BibTeX RDF
14	Ardavan Javid, Chenyuan Zhao, Mehdi Kiani	A 16-Channel High-Voltage ASIC with Programmable Delay Lines for Image-Guided Ultrasound Neuromodulation.	BioCAS	2022	DBLP DOI BibTeX RDF
14	Ravi Kirschner, Amin Hazrati Marangalou, Yusuke Tsuno, Ulkuhan Guler 0001	Digitally Controllable ASIC for Tri-Color Wireless Photometry.	BioCAS	2022	DBLP DOI BibTeX RDF
14	Thomas Bos, Marian Verhelst, Wim Dehaene	A Flexible End-to-End Dual ASIC Transceiver for OFDM Ultrasound In-Body Communication.	BioCAS	2022	DBLP DOI BibTeX RDF
14	Namik Kocaman, Ullas Singh, Bharath Raghavan, Arvindh Iyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, Jaehun Jeong, Heng Zhang, Anand Vasani, Yonghyun Shim, Zhi Huang, Adesh Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, Mario Caresosa, Bo Zhang 0029, Afshin Momtaz	An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Yannick Hopf, Boudewine W. Ossenkoppele, Mehdi Soozande, Emile Noothout, Zu-Yao Chang, Chao Chen 0019, Hendrik J. Vos, Hans G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs	A Pitch-Matched ASIC with Integrated 65V TX and Shared Hybrid Beamforming ADC for Catheter-Based High-Frame-Rate 3D Ultrasound Probes.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Kwantae Kim, Chang Gao 0002, Rui Graça, Ilya Kiselev, Hoi-Jun Yoo, Tobi Delbrück, Shih-Chii Liu	A 23μW Solar-Powered Keyword-Spotting ASIC with Ring-Oscillator-Based Time-Domain Feature Extraction.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Vikram B. Suresh, Chandra S. Katta, Srinivasan Rajagopalan, Tao Z. Zhou, Amit Kumar Patel, Raju Rakha, Nikhil Krishna Gopalakrishna, Sanu Mathew, Ajat Hukkoo	Bonanza Mine: an Ultra-Low-Voltage Energy-Efficient Bitcoin Mining ASIC.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Peng Guo, Fabian Fool, Emile Noothout, Zu-Yao Chang, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jonq, Michiel A. P. Pertijs	A 1.2mW/channel 100µm-Pitch-Matched Transceiver ASIC with Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3D Ultrasound Imaging.	ISSCC	2022	DBLP DOI BibTeX RDF
14	Aikaterini Papadopoulou, John Hermiz, Carl Grace, Peter Denes	A 512-Channel Neural Signal Acquisition ASIC for High-Density Electrophysiology.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Zeinab Kashani, Mehdi Kiani	An Adaptive ASIC for Closed-Loop Low-Power Pulse-Based Ultrasonic Data Transmission.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Hesam Sadeghi Gougheri, Mehdi Kiani	A High-Voltage ASIC for Ultrasound Neuromodulation with a Piezoelectric Transducer.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Loïc Massin, Fabrice Seguin, Vincent Nourrit, Emmanuel Daniel, Camilla Kärnfelt	A 0.35-μm subthreshold CMOS ASIC for a Smart Contact Lens Eye-Tracker.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Yihe Zhao, Gian Luca Barbruni, Zhikang Li, Libo Zhao 0001, Zhuangde Jiang, Christian C. Enz, Sandro Carrara	An ASIC Interface for CMUTs-based Biosensors with High Voltage Boosting and Oscillator.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Kiran Puttegowda, Christian Lütkemeyer, Elvio Serrano, Damian Morero, Kishore Kota	Development of Low-power Coherent ASIC.	OFC	2022	DBLP BibTeX RDF
14	M. Imtiaz Rashid, Benjamin Carrion Schafer	Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration.	ACM Great Lakes Symposium on VLSI	2022	DBLP DOI BibTeX RDF
14	Avinash Ramachandran	How innovations in ASIC architectures and novel design approaches power tomorrow's video networks.	MHV	2022	DBLP DOI BibTeX RDF
14	Philip G. Neudeck, David J. Spry, Michael J. Krasowski, Liangyu Chen	The Path Towards Realistic ASIC Electronics Deployment Into Previously Impractical Extreme Application Environments.	DRC	2022	DBLP DOI BibTeX RDF
14	William F. Ellersick	How to Prevent a Sick ASIC.	HPEC	2022	DBLP DOI BibTeX RDF
14	Mariusz Jankowski, Jacek Nazdrowicz, Piotr Zajac, Piotr Amrozik, Michal Szermer, Cezary Maj, Grzegorz Jablonski	Observation of Readout Temperature Dependence and Its Variability for the MEMS and ASIC System Specimens and Their PCB Testbenches.	MIXDES	2022	DBLP DOI BibTeX RDF
14	Chiragkumar B. Patel, Ganesh A. Mulay, Himanshu N. Patel, Pooja Dhankher	Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-Borne RADAR.	VDAT	2022	DBLP DOI BibTeX RDF
14	Anuj Srivastava, Nishant Kumar, Nihar Ranjan Mohapatra, Hari Shankar Gupta	High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics.	VDAT	2022	DBLP DOI BibTeX RDF
14	Ramesh Kumar, Ajay Kumar Singh, Chiragkumar Patel, S. Vinay Kumar, Himanshu N. Patel, B. Saravana Kumar	Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC.	VDAT	2022	DBLP DOI BibTeX RDF
14	Sooyeob Jung, Mi-Kyung Oh, Sangjae Lee, Joon-Gyu Ryu	Terminal ASIC Structure for Satellite IoT transmission.	APCC	2022	DBLP DOI BibTeX RDF
14	Alberto Annovi, Alessandro Cerri, Pascal Corona, Francesco Crescioli, David Martin, Eric Pierre, Sebastian Dittmeier, Gunnar Föhner, Dirk Gottschalk, André Schöning, Luca Frontini, Valentino Liberali, Alberto Stabile, Kostas Kordas, Tommaso Lari, Matteo Monti, Erdem Motuk, Matt Warren, Andreas Vgenopoulos	The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology.	MOCAST	2022	DBLP DOI BibTeX RDF
14	William Lemaire, Maher Benhouria, Konin Koua, Marwan Besrour, Louis-Philippe Gauthier, Gabriel Martin-Hardy, Tommy Rossignol, Sébastien Roy 0002, Réjean Fontaine	Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Douwe van Willigen, Eunchul Kang, Jovana Janjic, Emile Noothout, Zu-Yao Chang, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs	A Transceiver ASIC for a Single-Cable 64-Element Intra-Vascular Ultrasound Probe.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Jihee Lee, Kyoung-Rog Lee, Benjamin E. Eovino, Jeong Hoan Park, Luna Yue Liang, Liwei Lin, Hoi-Jun Yoo, Jerald Yoo	A 36-Channel Auto-Calibrated Front-End ASIC for a pMUT-Based Miniaturized 3-D Ultrasound System.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
14	Netanel Klein, Eyal Harel, Itamar Levi	The Cost of a True Random Bit - On the Electronic Cost Gain of ASIC Time-Domain-Based TRNGs.	Cryptogr.	2021	DBLP DOI BibTeX RDF
14	Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh	Error Detection Architectures for Ring Polynomial Multiplication and Modular Reduction of Ring-LWE in $\boldsymbol{\frac{\mathbb{Z}/p\mathbb{Z}[x]}{x^{n}+1}}$ Benchmarked on ASIC.	IEEE Trans. Reliab.	2021	DBLP DOI BibTeX RDF
14	Mohamed Chentouf, Foffie Stevmelin, Zine El Abidine Alaoui Ismaili	Power-aware hold optimization for ASIC physical synthesis.	Integr.	2021	DBLP DOI BibTeX RDF
14	Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro	Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.	IEEE Access	2021	DBLP DOI BibTeX RDF
14	Paul Miresan, Marius Neag, Marina Dana Topa, István Kovács, Laurentiu Varzaru	Multipurpose Drivers for MEMS Devices Based on a Single ASIC Implemented in a Low-Cost HV CMOS Process without a Triple Well.	J. Sensors	2021	DBLP DOI BibTeX RDF
14	Rahul Shrestha	A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
14	Rakesh Palisetty, Amit Kumar Panda, Kailash Chandra Ray	ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
14	Mitsuru Shiozaki, Takeshi Fujino	Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF.	J. Cryptogr. Eng.	2021	DBLP DOI BibTeX RDF
14	Garima Thakur, Harsh Sohal, Shruti Jain	A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
14	Yehya Nasser, Jordane Lorandel, Jean-Christophe Prévotet, Maryline Hélard	RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
14	Shuenn-Yuh Lee, Hao-Yun Lee, Ding-Siang Ciou, Zhan-Xian Liao, Peng-Wei Huang, Yi-Ting Hsieh, Yi-Chieh Wei, Chia-Yu Lin, Meng-Dar Shieh, Ju-Yi Chen	A Portable Wireless Urine Detection System With Power-Efficient Electrochemical Readout ASIC and ABTS-CNT Biosensor for UACR Detection.	IEEE Trans. Biomed. Circuits Syst.	2021	DBLP DOI BibTeX RDF
14	Chunkyun Seok, Oluwafemi Joel Adelegan, Ali Önder Biliroglu, Feysel Yalcin Yamaner, Ömer Oralkan	A Wearable Ultrasonic Neurostimulator - Part II: A 2D CMUT Phased Array System With a Flip-Chip Bonded ASIC.	IEEE Trans. Biomed. Circuits Syst.	2021	DBLP DOI BibTeX RDF
14	Jebashini Ponnian, Senthil Pari, Uma Ramadass, Chee-Pun Ooi	A New Systematic GDI Circuit Synthesis Using MUX Based Decomposition Algorithm and Binary Decision Diagram for Low Power ASIC Circuit Design.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Nabihah Ahmad, S. M. Rezaul Hasan	A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
14	Ibrahim Farhat, Wassim Hamidouche, Adrien Grill, Daniel Ménard, Olivier Déforges	Lightweight Hardware Transform Design for the Versatile Video Coding 4K ASIC Decoders.	IEEE Trans. Consumer Electron.	2021	DBLP DOI BibTeX RDF
14	Giuseppe Di Guglielmo, Farah Fahim, Christian Herwig, Manuel Blanco Valentin, Javier M. Duarte, Cristian Gingu, Philip C. Harris, James Hirschauer, Martin Kwok, Vladimir Loncar, Yingyi Luo, Llovizna Miranda, Jennifer Ngadiuba, Daniel Noonan, Seda Ogrenci-Memik, Maurizio Pierini, Sioni Summers, Nhan Tran	A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC.	CoRR	2021	DBLP BibTeX RDF