Search results for "DRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Eugene Tam, Shenfei Jiang, Paul Duan, Shawn Meng, Yue Pang, Cayden Huang, Yi Han, Jacke Xie, Yuanjun Cui, Jinsong Yu, Minggui Lu	DRAM-Based Processor for Deep Neural Networks Without SRAM Cache.	SAI (2)	2021	DBLP DOI BibTeX RDF
13	Youngbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun	Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies.	DATE	2021	DBLP DOI BibTeX RDF
13	Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, Onur Mutlu	Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications.	MICRO	2021	DBLP DOI BibTeX RDF
13	Lois Orosa 0001, Abdullah Giray Yaglikçi, Haocong Luo, Ataberk Olgun, Jisung Park 0001, Hasan Hassan, Minesh Patel, Jeremie S. Kim, Onur Mutlu	A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chipsand Implications on Future Attacks and Defenses.	MICRO	2021	DBLP DOI BibTeX RDF
13	Michael B. Sullivan 0001, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai 0002, Siva Kumar Sastry Hari, Stephen W. Keckler	Characterizing and Mitigating Soft Errors in GPU DRAM.	MICRO	2021	DBLP DOI BibTeX RDF
13	Lee Baker, Robert Patti, Paul D. Franzon	Multi-ANN embedded system based on a custom 3D-DRAM.	3DIC	2021	DBLP DOI BibTeX RDF
13	Abdullah Giray Yaglikçi, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Olgun, Lois Orosa 0001, Hasan Hassan, Jisung Park 0001, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, Onur Mutlu	BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows.	HPCA	2021	DBLP DOI BibTeX RDF
13	Jian Chen, Xiaowei Jiang, Ying Zhang, Liyin Liu, Huifeng Xu, Qiang Liu	CARE: Coordinated Augmentation for Elastic Resilience on DRAM Errors in Data Centers.	HPCA	2021	DBLP DOI BibTeX RDF
13	Heesu Kim, Hanmin Park, Taehyun Kim, Kwanheum Cho, Eojin Lee, Soojung Ryu, Hyuk-Jae Lee, Kiyoung Choi, Jinho Lee	GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent.	HPCA	2021	DBLP DOI BibTeX RDF
13	Yuanhui Zhou, Taotao Sheng, Jiguang Wan	HBTree: an Efficient Index Structure Based on Hybrid DRAM-NVM.	NVMSA	2021	DBLP DOI BibTeX RDF
13	Mohammad Farmani, Mark M. Tehranipoor, Fahim Rahman	RHAT: Efficient RowHammer-Aware Test for Modern DRAM Modules.	ETS	2021	DBLP DOI BibTeX RDF
13	João Fabrício Filho, Isaías B. Felzmann, Lucas Francisco Wanner	Transparent Resilience for Approximate DRAM.	ARCS	2021	DBLP DOI BibTeX RDF
13	Chirag Sudarshan, Taha Soliman, Cecilia De la Parra, Christian Weis, Leonardo Ecco, Matthias Jung 0001, Norbert Wehn, Andre Guntoro	A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.	ASP-DAC	2021	DBLP DOI BibTeX RDF
13	Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella	A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems.	ISPASS	2021	DBLP DOI BibTeX RDF
13	Heba Salem, Nigel P. Topham	Detecting denial-of-service hardware Trojans in DRAM-based memory systems.	ICECS	2021	DBLP DOI BibTeX RDF
13	Robert Lasch, Robert Schulze, Thomas Legler, Kai-Uwe Sattler	Workload-Driven Placement of Column-Store Data Structures on DRAM and NVM.	DaMoN	2021	DBLP DOI BibTeX RDF
13	Faxian Shan, Yang Xiong, Chang-Ching Chen, Haibo Chen, James Cho, Xiong Li, Wenyong Jiang, Jengwei Huang	Anomalous NMOSFET hot carrier degradation on DRAM.	ICTA	2021	DBLP DOI BibTeX RDF
13	Hojun Yoon, Wonjoo Jung, Jaewoo Park, Jindo Byun, Hyungmin Jin, Hyunyoon Cho, Youngmin Kim, Baek-Jin Lim, Young-Chul Cho, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko, Changsik Yoo, Sang-Hyun Lee	A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.	ESSCIRC	2021	DBLP DOI BibTeX RDF
13	Reza Mirosanlou, Mohamed Hassan 0002, Rodolfo Pellizzoni	DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.	MEMSYS	2021	DBLP DOI BibTeX RDF
13	Thomas Vogelsang, Brent Haukness, Eric Linstadt, Torsten Partsch, James Tringali	DRAM Refresh with Master Wordline Granularity Control of Refresh Intervals: Position Paper.	MEMSYS	2021	DBLP DOI BibTeX RDF
13	Adar Zeitak, Adam Morrison 0001	Cuckoo Trie: Exploiting Memory-Level Parallelism for Efficient DRAM Indexing.	SOSP	2021	DBLP DOI BibTeX RDF
13	Madhava Krishnan Ramanathan, Wook-Hee Kim, Xinwei Fu, Sumit Kumar Monga, Hee Won Lee, Minsung Jang, Ajit Mathew, Changwoo Min	TIPS: Making Volatile Index Structures Persistent with DRAM-NVMM Tiering.	USENIX Annual Technical Conference	2021	DBLP BibTeX RDF
13	Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim 0003, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee	25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Young-Cheon Kwon, Suk Han Lee, Jaehoon Lee 0005, Sang-Hyuk Kwon, Je-Min Ryu, Jong-Pil Son, Seongil O, Hak-soo Yu, Haesuk Lee, Soo Young Kim, Youngmin Cho, Jin Guk Kim, Jongyoon Choi, Hyunsung Shin, Jin Kim, BengSeng Phuah, Hyoungmin Kim, Myeong Jun Song, Ahn Choi, Daeho Kim, Sooyoung Kim, Eun-Bong Kim, David Wang 0003, Shinhaeng Kang, Yuhwan Ro, Seungwoo Seo, Joon-Ho Song, Jaeyoun Youn, Kyomin Sohn, Nam Sung Kim	25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Timothy M. Hollis, Ronny Schneider, Martin Brox, Thomas Hein, Wolfgang Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanovic, Maksim Kuzmenka, Daniel Lauber, Juan Ocon Garrido, David Ovard, Karl Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Jörg Weller, Peter Mayer 0003, Michael Richter 0003, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong	25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim	Session 25 Overview: DRAM Memory Subcommittee.	ISSCC	2021	DBLP DOI BibTeX RDF
13	Siddhartha Balakrishna Rai, Anand Sivasubramaniam, Adithya Kumar, Prasanna Venkatesh Rengasamy, Vijaykrishnan Narayanan, Ameen Akel, Sean Eilert	Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads.	CF	2021	DBLP DOI BibTeX RDF
13	Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen	Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
13	Sangjin Kim, Juhyoung Lee, Dongseok Im, Hoi-Jun Yoo	PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
13	Zhengtao Li, Zhipeng Tan, Jianxi Chen	HASDH: A Hotspot-Aware and Scalable Dynamic Hashing for Hybrid DRAM-NVM Memory.	ICCD	2021	DBLP DOI BibTeX RDF
13	Gian Singh, Ankit Wagle, Sarma B. K. Vrudhula, Sunil P. Khatri	CIDAN: Computing in DRAM with Artificial Neurons.	ICCD	2021	DBLP DOI BibTeX RDF
13	Khaled Humood, Baker Mohammad, Heba Abunahla	DTRNG: Low Cost and Robust True Random Number Generator Using DRAM Weak Write Scheme.	ISCAS	2021	DBLP DOI BibTeX RDF
13	Dong-Wan Ko, Won-Young Lee	A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector.	ISCAS	2021	DBLP DOI BibTeX RDF
13	Yinchuan Gu, Chris Eom, Jake Jung, Brian Lee 0003, Edwin Kim, Kanyu Cao	A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface.	ASICON	2021	DBLP DOI BibTeX RDF
13	Xiong Li, Huangxia Zhu, Xiaolin Guo, Kejun Mu, Peng Feng, Qi-An Xu, Blacksmith Wu, Kanyu Cao	Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM.	ASICON	2021	DBLP DOI BibTeX RDF
13	Yanzhe Tang, Zhongming Liu, Weibing Shang, Fengqin Zhang, Bernard Wu, Zhong Kong, Hongwen Li, Hong Ma, Kanyu Cao	Pitch Device Design in 10nm-Class DRAM Process through DTCO.	ASICON	2021	DBLP DOI BibTeX RDF
13	Tanmay Goel, Divyansh Maura, Kaustav Goswami 0002, Shirshendu Das, Dip Sankar Banerjee	Towards Row Sensitive DRAM Refresh through Retention Awareness.	ISQED	2021	DBLP DOI BibTeX RDF
13	Hanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon, Ki-Seok Chung	Reducing Refresh Overhead with In-DRAM Error Correction Codes.	ISOCC	2021	DBLP DOI BibTeX RDF
13	Yihuan Qian, Songwen Pei, Jihong Yuan, Dianle Zhou, Tong Liu, Linghe Kong	DRAM: Dragonfly Routing Algorithm on Multi-objects by Optimal Thresholds.	ISPA/BDCloud/SocialCom/SustainCom	2021	DBLP DOI BibTeX RDF
13	Xingyi Wang, Yu Li 0007, Yiquan Chen, Shiwen Wang, Yin Du, Cheng He, Yuzhong Zhang, Pinan Chen, Xin Li, Wenjun Song, Qiang Xu 0001, Li Jiang 0002	On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers.	VTS	2021	DBLP DOI BibTeX RDF
13	Junhao Zhu, Kaixin Huang, Xiaomin Zou, Chenglong Huang, Nuo Xu, Liang Fang	HDNH: a read-efficient and write-optimized hashing scheme for hybrid DRAM-NVM memory.	ICPP	2021	DBLP DOI BibTeX RDF
13	Xiping Jiang, Fengguo Zuo, Song Wang, Xiaofeng Zhou, Bing Yu, Yubing Wang, Qi Liu, Ming Liu, Yi Kang, Qiwei Ren	A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration.	A-SSCC	2021	DBLP DOI BibTeX RDF
13	Gyu-hyeon Lee, Seongmin Na, Ilkwon Byun, Dongmoon Min, Jangwoo Kim	CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing.	ISCA	2021	DBLP DOI BibTeX RDF
13	Lingxi Wu, Rasool Sharifi, Marzieh Lenjani, Kevin Skadron, Ashish Venkat	Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching.	ISCA	2021	DBLP DOI BibTeX RDF
13	Adarsh Patil 0002, Vijay Nagarajan, Rajeev Balasubramonian, Nicolai Oswald	Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication.	ISCA	2021	DBLP DOI BibTeX RDF
13	Ataberk Olgun, Minesh Patel, Abdullah Giray Yaglikçi, Haocong Luo, Jeremie S. Kim, Nisa Bostanci, Nandita Vijaykumar, Oguz Ergin, Onur Mutlu	QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips.	ISCA	2021	DBLP DOI BibTeX RDF
13	Lois Orosa 0001, Yaohua Wang, Mohammad Sadrosadati, Jeremie S. Kim, Minesh Patel, Ivan Puddu, Haocong Luo, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Saugata Ghose, Onur Mutlu	CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations.	ISCA	2021	DBLP DOI BibTeX RDF
13	Suk Han Lee, Shinhaeng Kang, Jaehoon Lee 0005, Hyeonsu Kim, Eojin Lee, Seungwoo Seo, Hosang Yoon, Seungwon Lee, Kyounghwan Lim, Hyunsung Shin, Jinhyun Kim, Seongil O, Anand Iyer, David Wang 0003, Kyomin Sohn, Nam Sung Kim	Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.	ISCA	2021	DBLP DOI BibTeX RDF
13	Kurt B. Ferreira, Scott Levy, Victor Kuhns, Nathan DeBardeleben, Sean Blanchard	Understanding the Effects of DRAM Correctable Error Logging at Scale.	CLUSTER	2021	DBLP DOI BibTeX RDF
13	Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, João Dinis Ferreira, Nika Mansouri-Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu	SIMDRAM: a framework for bit-serial SIMD processing using DRAM.	ASPLOS	2021	DBLP DOI BibTeX RDF
13	Mihir Mody, Rajasekhar Allu, Gang Hua 0003, Brijesh Jadav, Niraj Nandan, Ankur, Mayank Mangla	DRAM Bandwidth Optimal Perspective Transform Engine.	Autonomous Vehicles and Machines	2021	DBLP DOI BibTeX RDF
13	Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001	SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM.	DAC	2021	DBLP DOI BibTeX RDF
13	Litong You, Tianxiao Gu, Shengan Zheng, Jianmei Guo, Sanhong Li, Yuting Chen, Linpeng Huang	JPDHeap: A JVM Heap Design for PM-DRAM Memories.	DAC	2021	DBLP DOI BibTeX RDF
13	Yichen Jiang, Huifeng Zhu, Dean Sullivan, Xiaolong Guo, Xuan Zhang 0001, Yier Jin	Quantifying Rowhammer Vulnerability for DRAM Security.	DAC	2021	DBLP DOI BibTeX RDF
13	Fan Zhang 0069, Shaahin Angizi, Deliang Fan	Max-PIM: Fast and Efficient Max/Min Searching in DRAM.	DAC	2021	DBLP DOI BibTeX RDF
13	Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi	Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs.	DAC	2021	DBLP DOI BibTeX RDF
13	Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin	ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training.	DAC	2021	DBLP DOI BibTeX RDF
13	Dongjae Shin, Hyunil Byun, Dongshik Shim, Jungho Cha, Yonghwack Shin, Changgyun Shin, Chang-Bum Lee, Eunkyung Lee, Jisan Lee, Inoh Hwang, Kyunghyun Son, Hyuck Choo, Kyoungho Ha	III/V-on-bulk-Si Platform: Born for DRAM, Transplanted to LiDAR.	ECOC	2021	DBLP DOI BibTeX RDF
13	Yu Zheng, Zhao Huang, Liang Li, Changjian Xie, Quan Wang 0006, Zili Wu	Implementation and Analysis of Hybrid DRAM PUFs on FPGA.	NaNA	2021	DBLP DOI BibTeX RDF
13	Seyed Armin Vakil-Ghahani, Mahmut Taylan Kandemir, Jagadish B. Kotra	DSM: A Case for Hardware-Assisted Merging of DRAM Rows with Same Content.	Proc. ACM Meas. Anal. Comput. Syst.	2020	DBLP DOI BibTeX RDF
13	Shang Li 0001, Zhiyuan Yang 0001, Dhiraj Reddy, Ankur Srivastava 0001, Bruce L. Jacob	DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator.	IEEE Comput. Archit. Lett.	2020	DBLP DOI BibTeX RDF
13	Reza Mirosanlou, Danlu Guo, Mohamed Hassan 0002, Rodolfo Pellizzoni	MCsim: An Extensible DRAM Memory Controller Simulator.	IEEE Comput. Archit. Lett.	2020	DBLP DOI BibTeX RDF
13	Zhiyuan Shao, Chenhao Liu, Ruoshi Li, Xiaofei Liao, Hai Jin 0001	Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms.	ACM Trans. Reconfigurable Technol. Syst.	2020	DBLP DOI BibTeX RDF
13	Tomohiro Korikawa, Akio Kawabata, Fujun He, Eiji Oki	Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM.	IEEE Access	2020	DBLP DOI BibTeX RDF
13	Ingab Kang, Eojin Lee, Jung Ho Ahn	CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention.	IEEE Access	2020	DBLP DOI BibTeX RDF
13	Minwoo Jang, Seungkyu Lee, Jaeha Kung, Daehoon Kim	Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache.	IEEE Access	2020	DBLP DOI BibTeX RDF
13	Ling Zhan, Kai Lu, Zhilong Cheng, Jiguang Wan	RangeKV: An Efficient Key-Value Store Based on Hybrid DRAM-NVM-SSD Storage Structure.	IEEE Access	2020	DBLP DOI BibTeX RDF
13	Anthony Agnesina, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim	A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
13	Mohamed Hassan 0002	Reduced latency DRAM for multi-core safety-critical real-time systems.	Real Time Syst.	2020	DBLP DOI BibTeX RDF
13	Supriya Karmakar	Three-state dynamic random-access memory (DRAM).	IET Circuits Devices Syst.	2020	DBLP DOI BibTeX RDF
13	Byeongho Kim, Jongwook Chung, Eojin Lee, Wonkyung Jung, Sunjung Lee, Jaewan Choi, Jaehyun Park 0006, Minbok Wi, Sukhan Lee 0002, Jung Ho Ahn	MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
13	Haerang Choi, Do-sun Hong, Jaesung Lee, Sungjoo Yoo	Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
13	Zhiyong Zhang, Zhaoyan Shen, Zhiping Jia, Zili Shao	UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Minxuan Zhou, Andreas Prodromou, Rui Wang 0014, Hailong Yang, Depei Qian, Dean M. Tullsen	Temperature-Aware DRAM Cache Management - Relaxing Thermal Constraints in 3-D Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Jack Miskelly, Máire O'Neill	Fast DRAM PUFs on Commodity Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón	Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories.	ACM Trans. Embed. Comput. Syst.	2020	DBLP DOI BibTeX RDF
13	Rajeswari Packianathan, Gobinath Arumugam	Performance Analysis of Microstriplines Interconnect Structure with Novel Guard Trace as Parallel Links for High Speed Dram Interfaces.	Wirel. Pers. Commun.	2020	DBLP DOI BibTeX RDF
13	Odem Harel, Yarden Nachum, Robert Giterman	Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
13	Yoonah Paik, Seon Wook Kim, Dongha Jung, Minseong Kim	Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
13	Yaohua Wang, Lois Orosa 0001, Xiangjun Peng, Yang Guo 0003, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan Gómez-Luna, Mohammad Sadrosadati, Nika Mansouri-Ghiasi, Onur Mutlu	FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching.	CoRR	2020	DBLP BibTeX RDF
13	Adarsh Patil 0002	TLB and Pagewalk Performance in Multicore Architectures with Large Die-Stacked DRAM Cache.	CoRR	2020	DBLP BibTeX RDF
13	Chao-Hsuan Huang, Ishan G. Thakkar	Mitigating the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration.	CoRR	2020	DBLP BibTeX RDF
13	Jeremie S. Kim, Minesh Patel, Abdullah Giray Yaglikçi, Hasan Hassan, Roknoddin Azizi, Lois Orosa 0001, Onur Mutlu	Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques.	CoRR	2020	DBLP BibTeX RDF
13	Karthikeyan Nagarajan, Asmit De, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh	TrappeD: DRAM Trojan Designs for Information Leakage and Fault Injection Attacks.	CoRR	2020	DBLP BibTeX RDF
13	Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001	DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks.	CoRR	2020	DBLP BibTeX RDF
13	Nastaran Hajinazar, Geraldo F. Oliveira, Sven Gregorio, João Dinis Ferreira, Nika Mansouri-Ghiasi, Minesh Patel, Mohammed Alser, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu	SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM.	CoRR	2020	DBLP BibTeX RDF
13	Tobi Delbrück, Shih-Chii Liu	Data-Driven Neuromorphic DRAM-based CNN and RNN Accelerators.	CoRR	2020	DBLP BibTeX RDF
13	Yinjin Fu	CARAM: A Content-Aware Hybrid PCM/DRAM Main Memory System Framework.	CoRR	2020	DBLP BibTeX RDF
13	Minghua Wang, Zhi Zhang 0001, Yueqiang Cheng, Surya Nepal	DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping.	CoRR	2020	DBLP BibTeX RDF
13	Lev Mukhanov, Konstantinos Tovletoglou, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Georgios Karakonstantis	Workload-Aware DRAM Error Prediction using Machine Learning.	CoRR	2020	DBLP BibTeX RDF
13	Dimitrios Stathis 0001, Chirag Sudarshan, Yu Yang, Matthias Jung 0001, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn	eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.	J. Signal Process. Syst.	2020	DBLP DOI BibTeX RDF
13	Mustafa Fayez Ali, Akhilesh Jaiswal 0001, Kaushik Roy 0001	In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2020	DBLP DOI BibTeX RDF
13	Xueyong Zhang, Vivek Mohan, Arindam Basu	CRAM: Collocated SRAM and DRAM With In-Memory Computing-Based Denoising and Filling for Neuromorphic Vision Sensors in 65 nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
13	Youngbog Yoon, Hyunsu Park, Chulwoo Kim	A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
13	Youngbog Yoon, Chulwoo Kim	An Area-Efficient and Wide-Range Inter-Signal Skew Compensation Scheme With the Embedded Bypass Control Register Operating as a Binary Search Algorithm for DRAM Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
13	Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni, Hao Sun	Fast cacheline-based data replacement for hybrid DRAM and STT-MRAM main memory.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
13	Rakesh Pandey, Aryabartta Sahu	Run-time adaptive data page mapping: A Comparison with 3D-stacked DRAM cache.	J. Syst. Archit.	2020	DBLP DOI BibTeX RDF
13	Yinjin Fu, Yang Wu	CARAM: A Content-Aware Hybrid PCM/DRAM Main Memory System Framework.	NPC	2020	DBLP DOI BibTeX RDF
13	Lukas Steiner, Matthias Jung 0001, Felipe S. Prado, Kirill Bykov, Norbert Wehn	DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator.	SAMOS	2020	DBLP DOI BibTeX RDF
13	Do-Yeon Kim, Kee-Won Kwon	Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC.	MWSCAS	2020	DBLP DOI BibTeX RDF