Search results for "ISCA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten	Microarchitectural mechanisms to exploit value structure in SIMT architectures.	ISCA	2013	DBLP DOI BibTeX RDF
1	Avi Mendelson (eds.)	The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013	ISCA	2013	DBLP DOI BibTeX RDF
1	Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu	An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms.	ISCA	2013	DBLP DOI BibTeX RDF
1	Rodolfo Azevedo, John D. Davis, Karin Strauss, Parikshit Gopalan, Mark S. Manasse, Sergey Yekhanin	Zombie memory: extending memory lifetime by reviving dead blocks.	ISCA	2013	DBLP DOI BibTeX RDF
1	Richard A. Muscat, Karin Strauss, Luis Ceze, Georg Seelig	DNA-based molecular architecture with spatially localized components.	ISCA	2013	DBLP DOI BibTeX RDF
1	Ziyi Liu, Jong-Hyuk Lee, Junyuan Zeng, Yuanfeng Wen, Zhiqiang Lin, Weidong Shi	CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM.	ISCA	2013	DBLP DOI BibTeX RDF
1	Canturk Isci, Suzanne McIntosh, Jeffrey O. Kephart, Rajarshi Das, James E. Hanson, Scott Piper, Robert R. Wolford, Thomas Brey, Robert Kantner, Allen Ng, James Norris, Abdoulaye Traore, Michael Frissora	Agile, efficient virtualization power management with low-latency server power states.	ISCA	2013	DBLP DOI BibTeX RDF
1	Reetuparna Das, Satish Narayanasamy, Sudhir Satpathy, Ronald G. Dreslinski	Catnap: energy proportional multiple network-on-chip.	ISCA	2013	DBLP DOI BibTeX RDF
1	Anys Bacha, Radu Teodorescu	Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors.	ISCA	2013	DBLP DOI BibTeX RDF
1	Daniel Kudrow, Kenneth Bier, Zhaoxia Deng, Diana Franklin, Yu Tomita, Kenneth R. Brown, Frederic T. Chong	Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers.	ISCA	2013	DBLP DOI BibTeX RDF
1	Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González 0001	Deconfigurable microprocessor architectures for silicon debug acceleration.	ISCA	2013	DBLP DOI BibTeX RDF
1	George Kurian, Omer Khan, Srinivas Devadas	The locality-aware adaptive cache coherence protocol.	ISCA	2013	DBLP DOI BibTeX RDF
1	Ruirui C. Huang, Erik Halberg, G. Edward Suh	Non-race concurrency bug detection through order-sensitive critical sections.	ISCA	2013	DBLP DOI BibTeX RDF
1	Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Emile Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas	QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs.	ISCA	2013	DBLP DOI BibTeX RDF
1	Hongzhou Zhao, Arrvindh Shriraman, Snehasish Kumar, Sandhya Dwarkadas	Protozoa: adaptive granularity cache coherence.	ISCA	2013	DBLP DOI BibTeX RDF
1	Hassan M. G. Wassel, Ying Gao 0001, Jason Oberg, Ted Huffmire, Ryan Kastner, Frederic T. Chong, Timothy Sherwood	SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip.	ISCA	2013	DBLP DOI BibTeX RDF
1	Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn	Reducing memory access latency with asymmetric DRAM bank organizations.	ISCA	2013	DBLP DOI BibTeX RDF
1	Daniel Sánchez 0003, Christos Kozyrakis	ZSim: fast and accurate microarchitectural simulation of thousand-core systems.	ISCA	2013	DBLP DOI BibTeX RDF
1	Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer 0001, Chita R. Das	Orchestrated scheduling and prefetching for GPGPUs.	ISCA	2013	DBLP DOI BibTeX RDF
1	Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker	Flicker: a dynamically adaptive architecture for power limited multicore systems.	ISCA	2013	DBLP DOI BibTeX RDF
1	Minsoo Rhu, Mattan Erez	Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation.	ISCA	2013	DBLP DOI BibTeX RDF
1	Kristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout	Criticality stacks: identifying critical threads in parallel programs using synchronization behavior.	ISCA	2013	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Steven Swanson	QuickSAN: a storage area network for fast, distributed, solid state disks.	ISCA	2013	DBLP DOI BibTeX RDF
1	Jingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi	GPUWattch: enabling energy optimizations in GPGPUs.	ISCA	2013	DBLP DOI BibTeX RDF
1	Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang	An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.	ISCA	2013	DBLP DOI BibTeX RDF
1	Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, José F. Martínez	Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems.	ISCA	2013	DBLP DOI BibTeX RDF
1	Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer	Triggered instructions: a control paradigm for spatially-programmed architectures.	ISCA	2013	DBLP DOI BibTeX RDF
1	John Demme, Matthew Maycock, Jared Schmitz, Adrian Tang, Adam Waksman, Simha Sethumadhavan, Salvatore J. Stolfo	On the feasibility of online malware detection with performance counters.	ISCA	2013	DBLP DOI BibTeX RDF
1	Ting Cao, Stephen M. Blackburn, Tiejun Gao, Kathryn S. McKinley	The Yin and Yang of power and performance for asymmetric hardware and managed software.	ISCA	2012	DBLP DOI BibTeX RDF
1	Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing	Managing distributed UPS energy for effective power capping in data centers.	ISCA	2012	DBLP DOI BibTeX RDF
1	Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu	A case for exploiting subarray-level parallelism (SALP) in DRAM.	ISCA	2012	DBLP DOI BibTeX RDF
1	Minsoo Rhu, Mattan Erez	CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh 0001	Revisiting hardware-assisted page walks for virtualized systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Zhe Wang 0023, Samira Manabi Khan, Daniel A. Jiménez	Improving writeback efficiency with decoupled last-write prediction.	ISCA	2012	DBLP DOI BibTeX RDF
1	Abhayendra Singh, Satish Narayanasamy, Daniel Marino, Todd D. Millstein, Madanlal Musuvathi	End-to-end sequential consistency.	ISCA	2012	DBLP DOI BibTeX RDF
1	Joseph Devietti, Benjamin P. Wood, Karin Strauss, Luis Ceze, Dan Grossman, Shaz Qadeer	RADISH: Always-on sound and complete race detection in software and hardware.	ISCA	2012	DBLP DOI BibTeX RDF
1	Nadathur Satish, Changkyu Kim, Jatin Chhugani, Hideki Saito 0001, Rakesh Krishnaiyer, Mikhail Smelyanskiy, Milind Girkar, Pradeep Dubey	Can traditional programming bridge the Ninja performance gap for parallel computing applications?	ISCA	2012	DBLP DOI BibTeX RDF
1	Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu	VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Yi Xu, Jun Yang 0002, Rami G. Melhem	Tolerating process variations in nanophotonic on-chip networks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan	BOOM: Enabling mobile memory based low-power server DIMMs.	ISCA	2012	DBLP DOI BibTeX RDF
1	Olivier Temam	A defect-tolerant accelerator for emerging high-performance applications.	ISCA	2012	DBLP DOI BibTeX RDF
1	Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John	A first-order mechanistic model for architectural vulnerability factor.	ISCA	2012	DBLP DOI BibTeX RDF
1	Santosh Nagarakatte, Milo M. K. Martin, Steve Zdancewic	Watchdog: Hardware for safe and secure manual memory management and full memory safety.	ISCA	2012	DBLP DOI BibTeX RDF
1	Arkaprava Basu, Mark D. Hill, Michael M. Swift	Reducing memory reference energy with opportunistic virtual caching.	ISCA	2012	DBLP DOI BibTeX RDF
1	Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu	Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Aaron Carpenter, Jianyun Hu, Övünç Kocabas, Michael C. Huang 0001, Hui Wu	Enhancing effective throughput for transmission line-based bus.	ISCA	2012	DBLP DOI BibTeX RDF
1	Myoungsoo Jung, Ellis Herbert Wilson, Mahmut T. Kandemir	Physically Addressed Queueing (PAQ): Improving parallelism in Solid State Disks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jamie Liu, Ben Jaiyen, Richard Veras, Onur Mutlu	RAIDR: Retention-aware intelligent DRAM refresh.	ISCA	2012	DBLP DOI BibTeX RDF
1	Chao Li 0009, Amer Qouneh, Tao Li 0006	iSwitch: Coordinating and optimizing renewable energy powered server clusters.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jaikrishnan Menon, Marc de Kruijf, Karthikeyan Sankaralingam	iGPU: Exception support and speculative execution on GPUs.	ISCA	2012	DBLP DOI BibTeX RDF
1	Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer	Scheduling heterogeneous multi-cores through performance impact estimation (PIE).	ISCA	2012	DBLP DOI BibTeX RDF
1	David Wentzlaff, Christopher J. Jackson, Patrick Griffin, Anant Agarwal	Configurable fine-grain protection for multicore processor virtualization.	ISCA	2012	DBLP DOI BibTeX RDF
1	Nicolas Brunie, Caroline Collange, Gregory Frederick Diamos	Simultaneous branch and warp interweaving for sustained GPU performance.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jonathan Valamehr, Melissa Chase, Seny Kamara, Andrew Putnam, Daniel Shumow, Vinod Vaikuntanathan, Timothy Sherwood	Inspection resistant memory: Architectural support for security from physical examination.	ISCA	2012	DBLP DOI BibTeX RDF
1	Mahdi Nazm Bojnordi, Engin Ipek	PARDIS: A programmable memory controller for the DDRx interfacing standards.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jason Mars, Naveen Kumar 0002	BlockChop: Dynamic squash elimination for hybrid processor architecture.	ISCA	2012	DBLP DOI BibTeX RDF
1	R. Manikantan, Kaushik Rajan, R. Govindarajan	Probabilistic Shared Cache Management (PriSM).	ISCA	2012	DBLP DOI BibTeX RDF
1	Evgeni Krimer, Patrick Chiang 0001, Mattan Erez	Lane decoupling for improving the timing-error resiliency of wide-SIMD architectures.	ISCA	2012	DBLP DOI BibTeX RDF
1	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova	A case for random shortcut topologies for HPC interconnects.	ISCA	2012	DBLP DOI BibTeX RDF
1	Mehmet Kayaalp 0001, Meltem Ozsoy, Nael B. Abu-Ghazaleh, Dmitry Ponomarev 0001	Branch regulation: Low-overhead protection from code reuse attacks.	ISCA	2012	DBLP DOI BibTeX RDF
1	John Demme, Robert Martin, Adam Waksman, Simha Sethumadhavan	Side-channel vulnerability factor: A metric for measuring information leakage.	ISCA	2012	DBLP DOI BibTeX RDF
1	Robert Martin, John Demme, Simha Sethumadhavan	TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks.	ISCA	2012	DBLP DOI BibTeX RDF
1	Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim	FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.	ISCA	2012	DBLP DOI BibTeX RDF
1	Gaurang Upasani, Xavier Vera, Antonio González 0001	Setting an error detection infrastructure with low cost acoustic wave detectors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Min Kyu Jeong, Michael B. Sullivan 0001, Mattan Erez	The dynamic granularity memory system.	ISCA	2012	DBLP DOI BibTeX RDF
1		39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA	ISCA	2012	DBLP BibTeX RDF
1	Ioannis Doudalis, Milos Prvulovic	Euripus: A flexible unified hardware memory checkpointing accelerator for bidirectional-debugging and reliability.	ISCA	2012	DBLP DOI BibTeX RDF
1	José-María Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis	Boosting mobile GPU performance with a decoupled access/execute fragment processor.	ISCA	2012	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Krishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz	Towards energy-proportional datacenter memory with mobile DRAM.	ISCA	2012	DBLP DOI BibTeX RDF
1	Melanie Kambadur, Kui Tang, Martha A. Kim	Harmony: Collection and analysis of parallel block vectors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Yusuf Onur Koçberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Ozer 0001, Babak Falsafi	Scale-out processors.	ISCA	2012	DBLP DOI BibTeX RDF
1	Pranay Koka, Michael O. McCracken, Herb Schwetman, Chia-Hsin Owen Chen, Xuezhe Zheng, Ron Ho, Kannan Raj, Ashok V. Krishnamoorthy	A micro-architectural analysis of switched photonic multi-chip interconnects.	ISCA	2012	DBLP DOI BibTeX RDF
1	Andrea Pellegrini, Joseph L. Greathouse, Valeria Bertacco	Viper: Virtual pipelines for enhanced reliability.	ISCA	2012	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis A. Lastras	PreSET: Improving performance of phase change memories by exploiting asymmetry in write times.	ISCA	2012	DBLP DOI BibTeX RDF
1	Elliott Cooper-Balis, Paul Rosenfeld, Bruce L. Jacob	Buffer-on-board memory systems.	ISCA	2012	DBLP DOI BibTeX RDF
1	Doe Hyun Yoon, Min Kyu Jeong, Mattan Erez	Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput.	ISCA	2011	DBLP DOI BibTeX RDF
1	Binzhang Fu, Yinhe Han 0001, Jun Ma, Huawei Li 0001, Xiaowei Li 0001	An abacus turn model for time/space-efficient reconfigurable routing.	ISCA	2011	DBLP DOI BibTeX RDF
1	Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, Karthikeyan Sankaralingam	Sampling + DMR: practical and low-overhead permanent fault detection.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sriram Govindan, Anand Sivasubramaniam, Bhuvan Urgaonkar	Benefits and limitations of tapping into stored energy for datacenters.	ISCA	2011	DBLP DOI BibTeX RDF
1	Ravi R. Iyer 0001, Qing Yang 0001, Antonio González 0001 (eds.)	38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA	ISCA	2011	DBLP DOI BibTeX RDF
1	Kai Ma, Xue Li, Ming Chen 0002, Xiaorui Wang	Scalable power control for many-core architectures running multi-threaded applications.	ISCA	2011	DBLP DOI BibTeX RDF
1	Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic	Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators.	ISCA	2011	DBLP DOI BibTeX RDF
1	Blas Cuesta, Alberto Ros 0001, María Engracia Gómez, Antonio Robles, José Duato	Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks.	ISCA	2011	DBLP DOI BibTeX RDF
1	Siddhartha Chhabra, Yan Solihin	i-NVMM: a secure non-volatile main memory system with incremental encryption.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	A case for heterogeneous on-chip interconnects for CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Xiangyu Dong, Guangyu Sun 0003, Yuan Xie 0001, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Lingjia Tang, Jason Mars, Neil Vachharajani, Robert Hundt, Mary Lou Soffa	The impact of memory subsystem resource sharing on datacenter applications.	ISCA	2011	DBLP DOI BibTeX RDF
1	Neal Clayton Crago, Sanjay J. Patel	OUTRIDER: efficient memory latency tolerance with decoupled strands.	ISCA	2011	DBLP DOI BibTeX RDF
1	Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi	Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau	Releasing efficient beta cores to market early.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron	Energy-efficient mechanisms for managing thread context in throughput processors.	ISCA	2011	DBLP DOI BibTeX RDF
1	Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang 0003	DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mohit Tiwari, Jason Oberg, Xun Li 0001, Jonathan Valamehr, Timothy E. Levin, Ben Hardekopf, Ryan Kastner, Frederic T. Chong, Timothy Sherwood	Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security.	ISCA	2011	DBLP DOI BibTeX RDF
1	Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramoney	Bypass and insertion algorithms for exclusive last-level caches.	ISCA	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Prefetch-aware shared resource management for multi-core systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Joseph L. Greathouse, Zhiqiang Ma, Matthew I. Frank, Ramesh Peri, Todd M. Austin	Demand-driven software race detection using hardware performance counters.	ISCA	2011	DBLP DOI BibTeX RDF
1	Wing-Kei S. Yu, Ruirui C. Huang, Sarah Q. Xu, Sung-En Wang, Edwin Kan, G. Edward Suh	SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.	ISCA	2011	DBLP DOI BibTeX RDF
1	Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu 0024, Chris Wilkerson, Shih-Lien Lu	Energy-efficient cache design using variable-strength error-correcting codes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Thomas W. Barr, Alan L. Cox, Scott Rixner	SpecTLB: a mechanism for speculative address translation.	ISCA	2011	DBLP DOI BibTeX RDF

Publications at "ISCA"( http://dblp.L3S.de/Venues/ISCA )