Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Martin Lukac, Marek A. Perkowski |
Quantum Finite State Machines as Sequential Quantum Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 92-97, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Yuichi Baba, Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki |
Multiple-Valued Constant-Power Adder for Cryptographic Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 239-244, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama |
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 233-238, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Claudio Moraga |
Generalized Discrete Hartley Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 185-190, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Zeljko Zilic |
Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 268-273, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Manabu Nii, Takafumi Yamaguchi, Yutaka Takahashi 0002, Atsuko Uchinuno, Reiko Sakashita |
Fuzzy Rule Extraction from Nursing-Care Texts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 30-35, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Mitsuo Kawato |
Computational Neuroscience and Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 157-160, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Bambang A. B. Sarif, Mostafa I. H. Abd-El-Barr |
The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 145-150, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Claudio Moraga, Radomir S. Stankovic, Jaakko Astola |
On Periodic Patterns and their Spectra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 179-184, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Ramón Béjar, Alba Cabiscol, Felip Manyà, Jordi Planes |
Generating Hard Instances for MaxSAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 191-195, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba |
Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 318-323, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Claudio Moraga, Michio Sugeno, Enric Trillas |
Optimization of Fuzzy If-Then Rule Bases by Evolutionary Tuning of the Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 221-226, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Ali Sheikholeslami |
Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 203-207, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson |
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 256-261, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Koki Nishizawa |
Multi-valued Modal Fixed Point Logics for Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 109-113, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Josep Argelich, Alba Cabiscol, Inês Lynce, Felip Manyà |
Regular Encodings from Max-CSP into Partial Max-SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 196-202, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler |
Equivalence Checking of Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 324-330, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai |
Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 337-342, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Lucien Haddad |
Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 173-178, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Md. Mahmud Muntakim Khan, Ayan Kumar Biswas, Shuvro Chowdhury, Masud Hasan, Asif Islam Khan |
Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 98-102, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Masaki Murozuka, Kazumasa Ikeura, Fumiyuki Adachi, Kazuya Machida, Takao Waho |
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 245-249, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Hajime Machida, Jovanka Pantovic |
Hyperclones Determined by Total-Parts of Hyper-relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 161-166, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu |
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 60-65, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Mozammel H. A. Khan |
Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 103-108, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi |
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 250-255, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Masini, Luca Viganò 0001, Margherita Zorzi |
A Qualitative Modal Representation of Quantum Register Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 131-137, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quantum registers, modal logic, quantum logic |
1 | Victor Chepoi, Nadia Creignou, Miki Hermann, Gernot Salzer |
Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 100-105, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Helly property, complexity, satisfiability, many-valued logic, propositional logic |
1 | Mozammel H. A. Khan |
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 208-213, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu |
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 70-75, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Verilog-AMS, Static timing analysis, Look-up table |
1 | Martin Lukac, Marek A. Perkowski |
Projective Measurement-Based Logic Synthesis of Quantum Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 191-196, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Projective Measurement, Logic Synthesis, Quantum Circuits |
1 | Hirokatsu Shirahama, Takahiro Hanyu |
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 8-13, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit |
1 | Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler |
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 220-225, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Benchmarks, Synthesis, Reversible Logic |
1 | Claudio Moraga, Suzana Stojkovic, Radomir S. Stankovic |
On Fixed Points and Cycles in the Reed Muller Domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 82-87, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
spectral diversity, cycles, Eigenvectors, Reed Muller transform |
1 | John A. Chandy, Faquir C. Jain |
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 186-190, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multiple-valued logic, quantum dots |
1 | David W. Matula |
Foundations of Higher Radix Numeric Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 124, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu |
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 14-19, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
differential-pair circuit, radix-2 signed-digit adder, reliability |
1 | Kazuki Akutagawa, Kazuya Machida, Takao Waho |
A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 174-179, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algorithmic, redundancy, analog-to-digital converter, multiple-valued |
1 | Bogdan J. Falkowski, Cheng Fu |
Classification of Fastest Quaternary Linearly Independent Arithmetic Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 169-173, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
arithmetic transforms, Spectral techniques |
1 | Dan A. Simovici |
Betweenness, Metrics and Entropies in Lattices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 26-31, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
compatible metric, sub-modularity, modular lattices |
1 | Theodore W. Manikas, Dale Teeters |
Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 197-201, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
electrochemical cells, memory, nanotechnology, multiple-valued logic |
1 | Nobuaki Okada, Michitaka Kameyama |
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 180-185, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Field-programmable VLSI, Multiple-valued source-coupled logic, Differential-Pair circuit, Bit-serial architecture |
1 | Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller |
Quantum Logic Implementation of Unary Arithmetic Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 202-207, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multiple-Valued Quantum Gate, Inheritance Principle, Arithmetic Circuits, Quantum Logic |
1 | Masahiro Miyakawa, Maurice Pouzet, Ivo G. Rosenberg, Hisayuki Tatsumi |
Semirigid Equivalence Relations on a Finite Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 118-123, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
semirigid, lattice, clone, universal algebra, equivalence relation |
1 | |
38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![IEEE Computer Society, 978-0-7695-3155-7 The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
1 | Daniel Stamate |
Default Reasoning with Imperfect Information in Multivalued Logics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 163-168, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multivalued logics, default reasoning, imperfect information, bilattices |
1 | Raul Cruz-Cano, Igor N. Aizenberg |
Soft Computing Methods for Prediction of Replication Origins in Caudoviruses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 156-162, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Replication Origins, Caudoviruses, multilayer feedforward neural network with multi-valued neurons, least-squares support vector machine |
1 | Hosam A. Aleem, Ferda Mavituna, David H. Green |
A Galois Field Approach to Modelling Gene Expression Regulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 88-93, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Gene Expression, Galois Field, Genetic Code, Reed-Muller Expansion |
1 | Craig M. Files, Mark H. Nodine |
MDD with Added Null-Value and All-Value Edges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 64-69, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Multi-valued, Synthesis, MDD, Logic, Domino Logic |
1 | Susanna Minasyan, Jaakko Astola, Karen O. Egiazarian, Radomir S. Stankovic |
Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 232-237, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Hajime Machida, Jovanka Pantovic |
On Maximal Hyperclones on {0, 1} - A New Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 32-37, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
maximal clones, hyperoperations, clones |
1 | David J. Rosenbaum 0001, Marek A. Perkowski |
Superposed Quantum State Initialization Using Disjoint Prime Implicants (SQUID). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 144-149, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Superposed, Quantum Computing, Superposition |
1 | Doina Logofatu, Rolf Drechsler |
Comparative Study by Solving the Test Compaction Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 44-49, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Backtracking, Multi-Valued Logic, Test Compaction, Set Cover Problem, Greedy, Don't Cares |
1 | Tsutomu Sasao |
On the Complexity of Classification Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 57-63, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sum-of-products expression, Internet, packet classification, CAM |
1 | Thomas W. Williams |
EDA to the Rescue of the Silicon Roadmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 1, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Saoussen Bel Hadj Kacem, Amel Borgi, Khaled Ghédira |
Generalized Modus Ponens Based on Linguistic Modifiers in a Symbolic Multi-Valued Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 150-155, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Generalized Modus Ponens, linguistic modifiers, symbolic multi-valued logic, Approximate reasoning |
1 | Mark H. Nodine, Craig M. Files |
A Mature Methodology for Implementing Multi-Valued Logic in Silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 2-7, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
one-hot encoding, 1-of-N encoding, domino logic, null value |
1 | David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller |
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 138-143, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Quantum Logic Decision Diagrams, Quantum Computing, Multiple-valued Logic, Reversible Logic |
1 | Radomir S. Stankovic, Jaakko Astola |
Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 238-243, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sampling theorem, spectral coefficients, multiple-valued logic, non-Abelian groups |
1 | Hajime Machida, Tamás Waldhauser |
Majority and Other Polynomials in Minimal Clones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 38-43, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
minimal clone, polynomial, clone, Galois field |
1 | Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001 |
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 112-117, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multiple-valued logic circuits, arithmetic circuits, high-level design, circuit synthesis |
1 | Claudio Moraga |
Permutations under Spectral Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 76-81, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Vilenkin-Chrestenson transform, permutation preservation, Reed Muller transform |
1 | Josep Argelich, Alba Cabiscol, Inês Lynce, Felip Manyà |
Encoding Max-CSP into Partial Max-SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 106-111, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Minimal Support, Max-CSP, Partial Max-SAT, Encodings |
1 | Stephan Eggersglüß, Rolf Drechsler |
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 94-99, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Boolean Encodings, ATPG, SAT, Path Delay Faults |
1 | Mozammel H. A. Khan, Nafisa K. Siddika, Marek A. Perkowski |
Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 125-130, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Shinobu Nagayama, Tsutomu Sasao |
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 50-56, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
EVMDD, EVBDD, two-variable elementary functions, l-restricted Mp-monotone increasing functions, function generators |
1 | Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba |
Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 226-231, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
quaternary transforms, Spectral techniques, fast transforms |
1 | Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 214-219, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Synthesis, Boolean Satisfiability, Reversible Logic |
1 | Yasushi Yuminaka, Yasunori Takahashi |
Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 20-25, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pre-emphasis, High-speed interface, Equalizer, Multi-valued logic |
1 | Bogdan J. Falkowski, Shixing Yan |
Properties and Fast Algorithms for Ternary Walsh Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 47, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Vasilios Lirigis, Elena Dubrova |
Evaluation and Comparison of Threshold Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 52, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Lucien Haddad, Hajime Machida, Ivo G. Rosenberg |
Monoidal Intervals of Partial Clones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 9, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Shinobu Nagayama, Tsutomu Sasao |
Representations of Elementary Functions Using Edge-Valued MDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 5, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Yoshinori Yamamoto |
Power Indexes in Voting Systems and Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 35, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Martin Lukac, Marek A. Perkowski |
Quantum Mechanical Model of Emotional Robot Behaviors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 19, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura |
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 32, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Claudio Moraga, Milena Stankovic, Suzana Stojkovic |
Spectral Analysis of Special Properties of Ternary Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 4, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Mozammel H. A. Khan, Marek A. Perkowski |
GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 11, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Radomir S. Stankovic, Jaakko Astola |
Reading the Sampling Theorem in Multiple-Valued Logic: A Journey from the (Shannong) Sampling Theorem to the Shannon Decomposition Rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 2, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Motoi Inaba |
Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 58, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Akira Mochizuki, Masatomo Miura, Takahiro Hanyu |
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 57, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Donglin Li, Otmane Aït Mohamed, Sa'ed Abed |
Towards First-Order Symbolic Trajectory Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 53, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Patrik Eklund, Maria A. Galán |
The Rough Powerset Monad. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 27, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel |
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 6, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Nobuaki Okada, Michitaka Kameyama |
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 25, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet |
Fault Tolerant CMOS Logic Using Ternary Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 38, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Krzysztof S. Berezowski, Sarma B. K. Vrudhula |
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 24, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001 |
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 31, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Tasuku Ito, Michitaka Kameyama |
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 39, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Yale Fan |
A Generalization of the Deutsch-Jozsa Algorithm to Multi-Valued Quantum Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 12, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | |
37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![IEEE Computer Society, 978-0-7695-2831-1 The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
1 | Tomoki Tanoue, Munehiko Nagatani, Takao Waho |
A Ternary Analog-to-Digital Converter System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 36, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif |
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 48, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | André Sülflow, Rolf Drechsler |
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 42, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba |
Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 23, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Radomir S. Stankovic, Jaakko Astola |
A Note on Possible Applications of Fourier Representations in Circuit Design over Reprogrammable Technological Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 55, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Renè Jensen, Yngvar Berg |
Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 37, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Carlos Ansótegui, Maria Luisa Bonet, Jordi Levy, Felip Manyà |
A Complete Resolution Calculus for Signed Max-SAT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 22, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga |
Exploiting Homogeneous Dual Polarity Routes in Implementation of Algorithms for Optimization of Galois Field Expressions for Ternary Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 28, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto |
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 49, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
1 | Nabil Abu-Khader, Pepe Siy |
Inversion/Division in Galois Field Using Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 16, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|