| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Even Låte, Trond Ytterdal, Snorre Aunet |
A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology.  |
Integr.  |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheldon X.-D. Tan, Hussam Amrouch, Taeyoung Kim 0001, Zeyu Sun 0001, Chase Cook, Jörg Henkel |
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited). |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuotian Liao, Lihong Zhang |
Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang Liu 0019, Xu He, Bin Liang, Yang Guo 0003 |
Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Austin Lancaster, Manish Keswani |
Integrated circuit packaging review with an emphasis on 3D packaging. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Safa Berrima, Yves Blaquière, Yvon Savaria |
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Armineh Arasteh, Mohammad Hossein Moaiyeri, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
An energy and area efficient 4: 2 compressor based on FinFETs. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohamed Khairy Bahry, Mohamed El-Nozahi, Emad Hegazi |
An all-digital low ripples capacitive DC-DC converter with load tracking controller. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta |
Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee |
Contention free delayed keeper for high density large signal sensing memory compiler. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Alireza Ghorbani, M. B. Ghaznavi-Ghoushchi |
A low-area, 43.5% PAE, 0.9 W, Class-E differential power amplifier in 2.4 GHz for IoT applications. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Karimi, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani |
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sameh Attia, Hossam A. H. Fahmy, Yehea Ismail, Hassan Mostafa |
Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Paria Jamshidi, Mohammad Maymandi-Nejad |
Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Govinda Sannena, Bishnu Prasad Das |
Metastability immune and area efficient error masking flip-flop for timing error resilient designs. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Xiang, Sudeep Pasricha |
Mixed-criticality scheduling on heterogeneous multicore systems powered by energy harvesting. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Hari Mohan Gaur, Ashutosh Kumar Singh 0001, Umesh Ghanekar |
Offline Testing of Reversible Logic Circuits: An Analysis. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Naci Pekcokguler, Günhan Dündar, Hamdi Torun, Arda D. Yalcinkaya |
A novel equivalent circuit model for split ring resonator with an application of low phase noise reference oscillator. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Francesca Stradolini, Abuduwaili Tuoheti, Tugba Kilic, Danilo Demarchi, Sandro Carrara |
Raspberry-Pi based system for propofol monitoring. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Danaie, Esmaeel Ranjbar, Mojtaba Ahmadieh Khanesar |
MOSCAP compensation of three-stage operational amplifiers: Sensitivity and robustness, modeling and analysis. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Larry Pearlstein, Skyler Maxwell, Alex Aved |
Adaptive prediction resolution video coding for reduced DRAM bandwidth. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Cuauhtémoc R. Aguilera-Galicia, Omar Longoria-Gandara, Luis Pizano-Escalante, Javier Vázquez Castillo, Manuel Salim Maza |
On-chip implementation of a low-latency bit-accurate reciprocal square root unit. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Kiruba, V. Sumathy |
Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim |
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari |
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Sadeghi, Hooman Nikmehr |
Aging mitigation of L1 cache by exchanging instruction and data caches. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake |
Analog perceptron circuit with DAC-based multiplier. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarang Kazeminia, Khayrollah Hadidi |
A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Zhao, Yongqing Wang, Liyuan Dong |
Super current recycling folded cascode amplifier with ultra-high current efficiency. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Mohamed Asan Basiri, Sandeep K. Shukla |
Low power hardware implementations for network packet processing elements. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Philipp Tertel, Lars Hedrich |
Real-time emulation of block-based analog circuits on an FPGA. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Mehdi Panahi, Omid Hashemipour, Keivan Navi |
A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismail Bayram, Yiran Chen 0001 |
NV-TCAM: Alternative designs with NVM devices. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mitesh Limachia, Rajesh Amratlal Thakker, Nikhil Kothari |
A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Baixin Chen, Cheng Zhuo, Yiyu Shi 0001 |
A physics-aware methodology for equivalent circuit model extraction of TSV-inductors. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr Hassan, Hassan Mostafa, Hossam A. H. Fahmy |
NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Roberto Giorgio Rizzo, Andrea Calimera, Jun Zhou 0017 |
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jui-Hung Hsieh, Rong-Choi Lee, King-Chu Hung, Meng-Ju Shih |
Rapid and coding-efficient SPIHT algorithm for wavelet-based ECG data compression. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen 0001 |
Lagrangian relaxation-based routing path allocation for application-specific network-on-chips. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Farzaneh Nakhaee, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Sied Mehdi Fakhraie, Hamed Dorosti |
Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Roberto Sanchez Correa, Jean-Pierre David |
Ultra-low latency communication channels for FPGA-based HPC cluster. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Ershad Ahmed, Ch. Santosh Varma, M. B. Srinivas |
Improved designs of digit-by-digit decimal multiplier. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Hitesh Pahuja, Mintu Tyagi, Sudhakar Panday, Balwinder Singh |
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Balobas, Nikos Konofaos |
High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay |
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Aili Wang 0002, Chuanjin Richard Shi |
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay |
Reliability-aware application mapping onto mesh based Network-on-Chip. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Umberto Garlando, Fabrizio Riente, Giovanna Turvani, A. Ferrara, Giulia Santoro, Marco Vacca, Mariagrazia Graziano |
Architectural exploration of perpendicular Nano Magnetic Logic based circuits. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Federica Resta, Simone Gerardin, S. Mattiazzo, Alessandro Paccagnella, Marcello De Matteis, Christian C. Enz, Andrea Baschirotto |
1GigaRad TID impact on 28 nm HEP analog circuits. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Fábio Passos, Ricardo Martins 0003, Nuno Lourenço 0003, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández 0001 |
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Valerio Tenace, Andrea Calimera |
Quasi-exact logic functions through classification trees. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Etienne Lepercq, Yves Blaquière, Yvon Savaria |
A pattern-based routing algorithm for a novel electronic system prototyping platform. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ailin Zhang, Guoyong Shi |
A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Abdel-Majeed, Waleed Dweik |
Low overhead online periodic testing for GPGPUs. |
Integr. |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Aiman H. El-Maleh |
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Keith A. Campbell, Wei Zuo, Deming Chen |
New advances of high-level synthesis for efficient and reliable hardware design. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández 0001 |
An inductor modeling and optimization toolbox for RF circuit design. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Aaron Stillmaker, Bevan M. Baas |
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho, Baris Taskin |
Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria |
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Varun Venkatesan, Swamy D. Ponpandi, Akhilesh Tyagi |
Shaping data for application performance and energy optimization in dynamic data view framework. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001 |
Giant Spin-Hall assisted STT-RAM and logic design. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya |
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue |
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yibo Lin, Bei Yu 0001, Yi Zou, Zhuo Li 0001, Charles J. Alpert, David Z. Pan |
Stitch aware detailed placement for multiple E-beam lithography. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Navid Khoshavi, Rizwan A. Ashraf, Ronald F. DeMara, Saman Kiamehr, Fabian Oboril, Mehdi Baradaran Tahoori |
Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Weijing Shi, Mohamed Baker Alawieh, Xin Li 0001, Huafeng Yu |
Algorithm and hardware implementation for visual perception system in autonomous vehicle: A survey. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Olufemi Akindele Olumodeji, Massimo Gottardi |
Arduino-controlled HP memristor emulator for memristor circuit applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohsen Shahghasemi, Mohammad Yavari |
MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hala Hamadeh, Soma Chaudhuri, Akhilesh Tyagi |
Area, energy, and time assessment for a distributed TPM for distributed trust in IoT clusters. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael A. Turi, José G. Delgado-Frias |
Full-VDD and near-threshold performance of 8T FinFET SRAM cells. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Szu Huat Goh, Y. H. Chan, Zhao Lin, Jeffrey Lam |
Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Niranjan Kumar Ray 0001, Ashok Kumar Turuk |
A framework for post-disaster communication using wireless ad hoc networks. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, Nor Hisham Hamid |
Bio-inspired fault tolerant network on chip. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyajit Mukherjee, Santanu Chattopadhyay |
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li 0002 |
Revisiting 3DIC benefit with multiple tiers. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi 0001 |
A routing framework for technology migration with bump encroachment. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Bibhas Ghoshal, Chittaranjan Mandal 0002, Indranil Sengupta 0001 |
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad T. Sheikh, Aiman H. El-Maleh |
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Chen, Benqing Guo, Boyang Zhang, Guangjun Wen |
An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
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| 1 | Tiansong Cui, Shuang Chen 0001, Yanzhi Wang, Qi Zhu 0002, Shahin Nazarian, Massoud Pedram |
An optimal energy co-scheduling framework for smart buildings. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Javier Lemus-López, Alejandro Díaz-Sánchez, José Miguel Rocha-Pérez, Carlos Muñiz-Montero, Jaime Ramírez-Angulo |
High gain amplifier with feedforward compensation based on quasi-floating gate transistors. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Huyen Thi Pham, Sabooh Ajaz, Hanho Lee |
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiajun Zhang, Haining Fan |
Low space complexity CRT-based bit-parallel GF(2n) polynomial basis multipliers for irreducible trinomials. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gan Feng, Lan Yao, Song Chen 0001 |
AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos |
Run-time management of systems with partially reconfigurable FPGAs. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ricardo Martins 0003, Nuno Lourenço 0003, António Canelas, Nuno Horta |
Stochastic-based placement template generator for analog IC layout-aware synthesis. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Mohamed Asan Basiri, Sandeep K. Shukla |
Flexible VLSI architectures for Galois field multipliers. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner 0003 |
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Kalyan S. Perumalla |
Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Riccardo Bernardini, Roberto Rinaldo |
A very stable diode-based physically unclonable constant. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Huang 0003, Valeriy Sukharev, Taeyoung Kim 0001, Sheldon X.-D. Tan |
Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yalçin Balcioglu, Günhan Dündar |
A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL). |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu |
Cluster-based delta-QMC technique for fast yield analysis. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo |
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Achira Pal, Atal Chaudhuri, Rajat Kumar Pal, Alak Kumar Datta |
Hardness of crosstalk minimization in two-layer channel routing. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ons Lahiouel, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar |
Exploiting bounds optimization for the semi-formal verification of analog circuits. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Siraj Fulum Mossa, Syed Rafay Hasan, Omar S. Elkeelany |
Hardware trojans in 3-D ICs due to NBTI effects and countermeasure. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rickard Ewetz, Cheng-Kok Koh |
Fast clock scheduling and an application to clock tree synthesis. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhamita Mukherjee, Indrajit Pan, Tuhina Samanta |
Pareto optimization technique in actuation control for error minimization and reliability analysis in an operational pin-constrained digital microfluidic biochip. |
Integr. |
2017 |
DBLP DOI BibTeX RDF |
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