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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Carlos Moratelli, Ramão Tiago Tiburski, Sergio Johann Filho, Emanuel Moura, Everton de Matos, Fabiano Hessel |
MIPS and RISC-V: Evaluating Virtualization Trade-off for Edge Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WF-IoT ![In: 8th IEEE World Forum on Internet of Things, WF-IoT 2022, Yokohama, Japan, October 26 - Nov. 11, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9153-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer |
Static Hardware Partitioning on RISC-V: Shortcomings, Limitations, and Prospects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WF-IoT ![In: 8th IEEE World Forum on Internet of Things, WF-IoT 2022, Yokohama, Japan, October 26 - Nov. 11, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9153-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ahmed Kamaleldin, Diana Göhringer |
A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 32nd International Conference on Field-Programmable Logic and Applications, FPL 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022, pp. 300-306, 2022, IEEE, 978-1-6654-7390-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Luca Bertaccini, Gianna Paulin, Tim Fischer 0001, Stefan Mach, Luca Benini |
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 29th IEEE Symposium on Computer Arithmetic, ARITH 2022, Lyon, France, September 12-14, 2022, pp. 1-8, 2022, IEEE, 978-1-6654-7827-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías |
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 29th IEEE Symposium on Computer Arithmetic, ARITH 2022, Lyon, France, September 12-14, 2022, pp. 66, 2022, IEEE, 978-1-6654-7827-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jonas Gava, Guilherme Dorneles, Ricardo Reis 0001, Rafael Garibotti, Luciano Ost |
Soft Error Assessment of CNN Inference Models Running on a RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS 2022 ![In: 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-8823-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hailong Wu, Jindong Li, Xiang Chen |
Implementation of CNN Heterogeneous Scheme Based on Domestic FPGA with RISC-V Soft Core CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 158-159, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu |
Hardware Based RISC-V Instruction Set Randomization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTA ![In: 2022 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2022, Xi'an, China, October 28-30, 2022, pp. 96-97, 2022, IEEE, 978-1-6654-9269-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Liu Lu |
Design of A Programmable PCI-E Encryption System Based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCSIC ![In: 6th International Symposium on Computer Science and Intelligent Control, ISCSIC 2022, Beijing, China, November 11-13, 2022, pp. 368-373, 2022, IEEE, 978-1-6654-5488-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Konrad-Felix Krentz, Thiemo Voigt |
Reducing Trust Assumptions with OSCORE, RISC-V, and Layer 2 One-Time Passwords. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPS ![In: Foundations and Practice of Security - 15th International Symposium, FPS 2022, Ottawa, ON, Canada, December 12-14, 2022, Revised Selected Papers, pp. 389-405, 2022, Springer, 978-3-031-30121-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Mao-Hsu Yen, Cheng-Hao Tsou, Ssu-Chi Lin, Che-Wei Chang, Yih-Hsia Lin, Yuan-Fu Ku, Chi-Lin Chiang |
VLSI Implementation of RISC MCU with In-Circuit Debugger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICKII ![In: 5th IEEE International Conference on Knowledge Innovation and Invention, ICKII 2022, Hualien, Taiwan, July 22-24, 2022, pp. 63-68, 2022, IEEE, 978-1-6654-7929-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti 0001 |
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, September 19-22, 2022, pp. 273-276, 2022, IEEE, 978-1-6654-8494-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri |
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ApplePies ![In: Applications in Electronics Pervading Industry, Environment and Society - APPLEPIES 2022, Genoa, Italy, 26-27 September 2022., pp. 300-306, 2022, Springer, 978-3-031-30332-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy |
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 68-69, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Daniel S. Truesdell, Xinjian Liu, Jacob Breiholz, Shourya Gupta, Shuo Li 0008, Benton H. Calhoun |
NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 210-211, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zhongpan Wu, Karim Hammad, Abel Beyene, Yunus Dawji, Ebrahim Ghafar-Zadeh, Sebastian Magierowski |
An FPGA Implementation of A Portable DNA Sequencing Device Based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 20th IEEE Interregional NEWCAS Conference, NEWCAS 2022, Quebec City, QC, Canada, June 19-22, 2022, pp. 417-420, 2022, IEEE, 978-1-6654-0105-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Felix Böseler, Jörg Walter 0001, Behnam Razi Perjikolaei |
A Comparison of Virtual Platform Simulation Solutions for Timing Prediction of Small RISC-V Based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on Specification & Design Languages, FDL 2022, Linz, Austria, September 14-16, 2022, pp. 1-8, 2022, IEEE, 978-1-6654-7332-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Tobias Cloosters, David Paaßen, Jianqiang Wang, Oussama Draissi, Patrick Jauernig, Emmanuel Stapf, Lucas Davi, Ahmad-Reza Sadeghi |
RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAID ![In: 25th International Symposium on Research in Attacks, Intrusions and Defenses, RAID 2022, Limassol, Cyprus, October 26-28, 2022, pp. 30-42, 2022, ACM, 978-1-4503-9704-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jean-Michel Gorius, Simon Rokicki, Steven Derrien |
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5336-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Antonov |
Superscalar Out-of-Order RISC-V ASIP Based on Programmable Hardware Generator with Decoupled Computations and Flow Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 11th Mediterranean Conference on Embedded Computing, MECO 2022, Budva, Montenegro, June 7-10, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-6828-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 11th Mediterranean Conference on Embedded Computing, MECO 2022, Budva, Montenegro, June 7-10, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-6828-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Tatsuya Tsuchiya, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima |
Assembly code translation from ARM64 to RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SNPD-Summer ![In: 23rd ACIS International Summer Virtual Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2022 - Summer, Kyoto City, Japan, July 4-7, 2022, pp. 68-73, 2022, IEEE, 979-8-3503-9637-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Bobby D. Birrer, Carlos Salazar |
Improving Student Comprehension with Logisim-based RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIE ![In: IEEE Frontiers in Education Conference, FIE 2022, Uppsala, Sweden, October 8-11, 2022, pp. 1-5, 2022, IEEE, 978-1-6654-6244-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hung-Ming Lai, Jenq-Kuen Lee |
Efficient Support of the Scan Vector Model for RISC-V Vector Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: Workshop Proceedings of the 51st International Conference on Parallel Processing, ICPP Workshops 2022, Bordeaux, France, 29 August 2022 - 1 September 2022, pp. 15:1-15:8, 2022, ACM, 978-1-4503-9445-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Xiao Hu, Yaohua Wang, Xuan Gao |
Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2022, Shanghai, China, October 7-14, 2022, pp. 31-32, 2022, IEEE, 978-1-6654-7296-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler |
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: IEEE International Workshop on Rapid System Prototyping, RSP 2022, Shanghai, China, October 13, 2022, pp. 22-28, 2022, IEEE, 979-8-3503-9851-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jorge Reis, Jarbas Silveira, César A. M. Marcon |
Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LADC ![In: Proceedings of the 11th Latin-American Symposium on Dependable Computing, LADC 2022, Fortaleza/CE, Brazil, November 21-24, 2022, pp. 29-34, 2022, ACM, 978-1-4503-9737-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zahra Azad, Guowei Yang, Rashmi Agrawal 0001, Daniel Petrisko, Michael B. Taylor, Ajay Joshi |
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022, pp. 13:1-13:6, 2022, ACM, 978-1-4503-9354-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Eleonora Vacca, Corrado De Sio, Sarah Azimi |
Layout-oriented radiation effects mitigation in RISC-V soft processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022, pp. 215-220, 2022, ACM, 978-1-4503-9338-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Gheorghe Pojoga, Kostas Papagiannopoulos |
Low-latency implementation of the GIFT cipher on RISC-V architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022, pp. 287-295, 2022, ACM, 978-1-4503-9338-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Federico Ficarelli, Andrea Bartolini, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini |
Meet Monte Cimone: exploring RISC-V high performance compute clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17 - 22, 2022, pp. 207-208, 2022, ACM, 978-1-4503-9338-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Simon Tollec, Mihail Asavoae, Damien Couroussé, Karine Heydemann, Mathieu Jan |
Exploration of Fault Effects on Formal RISC-V Microarchitecture Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDTC ![In: Workshop on Fault Detection and Tolerance in Cryptography, FDTC 2022, Virtual Event / Italy, September 16, 2022, pp. 73-83, 2022, IEEE, 978-1-6654-5442-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Cosmin-Andrei Popovici, Andrei Stan |
Extending a RISC-V Core with a CAN-FD Communication Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSTCC ![In: 26th International Conference on System Theory, Control and Computing , ICSTCC 2022, Sinaia, Romania, October 19-21, 2022, pp. 31-36, 2022, IEEE, 978-1-6654-6746-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Junwei Wu, Xin Zheng 0001, Shaofen Zeng, Huaien Gao, Xiaoming Xiong |
High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HP3C ![In: HP3C 2022: 6th International Conference on High Performance Compilation, Computing and Communications, Virtual Event, China, June 23-25, 2022, pp. 84-90, 2022, ACM, 978-1-4503-9629-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Vladimir Ushakov, Sampo Sovio, Qingchao Qi, Vijayanand Nayani, Valentin Manea, Philip Ginzboorg, Jan-Erik Ekberg |
Trusted Hart for Mobile RISC-V Security. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TrustCom ![In: IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2022, Wuhan, China, December 9-11, 2022, pp. 1587-1596, 2022, IEEE, 978-1-6654-9425-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Ingo Hoyer, Alexander Utz, André Lüdecke, Mike Richter, Felix Wichum, Pierre Gembaczka, Kerstin Köhler, Maurice Rohr, Christoph Hoog Antink, Karsten Seidl |
Detection of atrial fibrillation with an optimized neural network on a RISC-V-based microcontroller for efficient integration into ECG patches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MeMeA ![In: IEEE International Symposium on Medical Measurements and Applications, MeMeA 2022, Messina, Italy, June 22-24, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8299-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Tian Zheng, Gang Cai, Zhihong Huang |
A Soft RISC-V Processor IP with High-performance and Low-resource consumption for FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2538-2541, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman |
A RISC-V-based Research Platform for Rapid Design Cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2614-2615, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Endri Taka, George Lentaris, Dimitrios Soudris |
Improving the performance of RISC-V softcores on FPGA by exploiting PVT variability and DVFS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 1595-1599, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
Spectre attack detection with Neutral Network on RISC-V processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 2467-2471, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jonas Kühne, Michele Magno, Luca Benini |
Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 301-305, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao 0001, Fan Yang 0001 |
An Automated Compiler for RISC-V Based DNN Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 3097-3101, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Siu Hong Loh, You Hong Liew, Jia Jia Sim |
VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSCE ![In: 12th IEEE International Conference on Control System, Computing and Engineering, ICCSCE 2022, Penang, Malaysia, October 21-22, 2022, pp. 7-12, 2022, IEEE, 978-1-6654-8339-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle |
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-7355-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Fernando Fernandes dos Santos, Angeliki Kritikakou, Olivier Sentieys |
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-7355-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Andrea Bartolini, Federico Ficarelli, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini |
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOCC ![In: 35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5985-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Fabian Kempf, Julian Höfer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker 0001 |
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOCC ![In: 35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5985-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Riku Takayama, Jubee Tada |
An Implementation of a Pattern Matching Accelerator on a RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDARW ![In: 2022 Tenth International Symposium on Computing and Networking, CANDAR 2022 - Workshops, Himeji, Japan, November 21-24, 2022, pp. 273-275, 2022, IEEE, 978-1-6654-7532-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Kari Hepola, Joonas Multanen, Pekka Jääskeläinen |
OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2022, Gothenburg, Sweden, July 12-14, 2022, pp. 161-165, 2022, IEEE, 978-1-6654-8308-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini |
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2022, Gothenburg, Sweden, July 12-14, 2022, pp. 43-51, 2022, IEEE, 978-1-6654-8308-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Lucas Klemmer, Manfred Schlägl, Daniel Große |
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 183-187, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Pascal Pieper, Vladimir Herdt, Rolf Drechsler |
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 193-197, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Gaëtan Leplus, Olivier Savry, Lilian Bossuet |
Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2022, McLean, VA, USA, June 27-30, 2022, pp. 81-84, 2022, IEEE, 978-1-6654-8532-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Edian B. Annink, Gerard K. Rauwerda, Edwin A. Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi |
Preventing Soft Errors and Hardware Trojans in RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi 0001, Marco Ottavi |
Is RISC-V ready for Space? A Security Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Douglas A. dos Santos, André Martins Pio de Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo |
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jonathas Silveira, Lucas Castro, Victor Araújo, Rodrigo Zeli, Daniel Lazari, Marcelo Guedes, Rodolfo Azevedo, Lucas Wanner 0001 |
Prof5: A RISC-V profiler tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Bordeaux, France, November 2-5, 2022, pp. 201-210, 2022, IEEE, 978-1-6654-5155-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Guillaume Soulard, Gabriel P. Lachance, Élodie Boisselier, Mounir Boukadoum, Amine Miled 0001 |
RISC-V Based Processor Architecture for an Embedded Visible Light Spectrophotometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2022, Halifax, NS, Canada, September 18-20, 2022, pp. 360-363, 2022, IEEE, 978-1-6654-8432-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Dexing Qin, Xue Bai, Yiliang Wu, Yendo Hu |
Design and Implementation of Neural Network Accelerated SOC Based on Small RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EITCE ![In: Proceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering, EITCE 2022, Xiamen, China, October 21-23, 2022., pp. 1867-1872, 2022, ACM, 978-1-4503-9714-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Nicholas Gordon, Kevin T. Pedretti, John R. Lange |
Porting the Kitten Lightweight Kernel Operating System to RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ROSS ![In: IEEE/ACM International Workshop on Runtime and Operating Systems for Supercomputers, ROSS 2022, Dallas, TX, USA, November 13-18, 2022, pp. 1-7, 2022, IEEE, 978-1-6654-7566-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | M. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J. |
Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 86-91, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Asmit De, Swaroop Ghosh |
HeapSafe: Securing Unprotected Heaps in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 120-125, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | V. Naveen Chander, Kuruvilla Varghese |
A Soft RISC-V Vector Processor for Edge-AI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, VLSID 2022, Bangalore, India, February 26 - March 2, 2022, pp. 263-268, 2022, IEEE, 978-1-6654-8505-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Daniel Vázquez, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre |
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5950-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals |
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5950-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González 0004, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria 0001, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández 0001, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio 0001, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa |
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5950-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías |
Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCIS ![In: 37th Conference on Design of Circuits and Integrated Systems, DCIS 2022, Pamplona, Spain, November 16-18, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5950-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Alexander Dörflinger, Benedikt Kleinbeck, Mark Albers, Harald Michalik, Martin Moya |
A Framework for Fault Tolerance in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC/PiCom/CBDCom/CyberSciTech ![In: IEEE Intl. Conf. on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress, DASC/PiCom/CBDCom/CyberSciTech 2022, Falerna, Italy, September 12-15, 2022, pp. 1-8, 2022, IEEE, 978-1-6654-6297-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | M. K. Aparna Nair, Vishwas Vasuki Gautam, Abhishek Revinipati, J. Soumya |
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 515-526, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Jun Liu, Ting Chong, Liang Liu, Xige Zhang |
Software Solution of Secure Debug Based on RISC-V CPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSIE ![In: Proceedings of the 7th International Conference on Cyber Security and Information Engineering, ICCSIE 2022, Brisbane, QLD, Australia, September 23-25, 2022, pp. 19-23, 2022, ACM, 978-1-4503-9741-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Srikrishna Vasudev, Kartickraj K, Anuj Grover |
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 222-225, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Honglin Kuang, Yifan Zhao, Jun Han 0003 |
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, pp. 592-595, 2022, IEEE, 978-1-6654-5073-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Lucas Klemmer, Daniel Große |
Waveform-based performance analysis of RISC-V processors: late breaking results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1404-1405, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Hsu-Kang Dow, Tuo Li 0001, Sri Parameswaran |
HWST128: complete memory safety accelerator on RISC-V with metadata compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 709-714, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hongyi Lu, Fengwei Zhang |
Raven: a novel kernel debugging tool on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 1039-1044, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Huimin Li 0004, Nele Mentens, Stjepan Picek |
A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 733-738, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Mihaela Damian, Julian Oppermann, Christoph Spang 0001, Andreas Koch 0001 |
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 169-174, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Muhammet Cihat Mumcu, Ihsan Çiçek, Salih Bayar |
Performance Evaluation of Lightweight Cryptographic Algorithms on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIU ![In: 30th Signal Processing and Communications Applications Conference, SIU 2022, Safranbolu, Turkey, May 15-18, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-5092-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Alejandra Sanchez-Flores, Lluc Alvarez, Bartomeu Alorda-Ladaria |
A review of CNN accelerators for embedded systems based on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COINS ![In: IEEE International Conference on Omni-layer Intelligent Systems, COINS 2022, Barcelona, Spain, August 1-3, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-8356-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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13 | Stefano Di Mascio |
Spin-in of RISC-V Processors in Space Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2022 |
RDF |
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13 | Marco Cococcioni, Federico Rossi 0003, Emanuele Ruffaldi, Sergio Saponara |
Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 33(16), pp. 10575-10585, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Latif Akçay, Siddika Berna Örs |
Comparison of RISC-V and transport triggered architectures for a postquantum cryptography application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 29(1), pp. 321-333, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler |
Toward RISC-V CSR Compliance Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 13(4), pp. 202-205, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Florian Zaruba, Fabian Schuiki, Luca Benini |
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 41(2), pp. 36-42, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ralf Hemmecke |
RISC Ph.D. studies program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Commun. Comput. Algebra ![In: ACM Commun. Comput. Algebra 55(4), pp. 135, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Pietro Nannipieri, Stefano Di Matteo, Luca Zulberti, Francesco Albicocchi, Sergio Saponara, Luca Fanucci |
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 150798-150808, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 164597-164612, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 151993-152014, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Kuniyasu Suzaki, Kenta Nakajima, Tsukasa Oi, Akira Tsukamoto |
TS-Perf: General Performance Measurement of Trusted Execution Environment and Rich Execution Environment on Intel SGX, Arm TrustZone, and RISC-V Keystone. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 133520-133530, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Seung-Yeong Lee, Jae-Hyoung Lee, Woojoo Lee |
Developing a Multicore Platform Utilizing Open RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 120010-120023, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini |
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(4), pp. 677-690, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Gianna Paulin, Renzo Andri, Francesco Conti 0001, Luca Benini |
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 29(9), pp. 1624-1637, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 9(3), pp. 1489-1505, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu |
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(9), pp. 3153-3157, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Satyajit Bora, Roy Paily |
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 68(6), pp. 2132-2136, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini |
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 70(2), pp. 212-227, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone |
Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Sci. Rev. ![In: Comput. Sci. Rev. 39, pp. 100349, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti 0001 |
PERI: A Configurable Posit Enabled RISC-V Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 18(3), pp. 25:1-25:26, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Vladimir A. Frolov, Vladimir A. Galaktionov, Vadim V. Sanzharov |
Investigation of RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Program. Comput. Softw. ![In: Program. Comput. Softw. 47(7), pp. 493-504, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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13 | Shuenn-Yuh Lee, Yi-Wen Hung, Yao-Tse Chang, Chou-Ching K. Lin, Gia-Shing Shieh |
RISC-V CNN Coprocessor for Real-Time Epilepsy Detection in Wearable Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 15(4), pp. 679-691, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
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