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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Carlos Moratelli, Ramão Tiago Tiburski, Sergio Johann Filho, Emanuel Moura, Everton de Matos, Fabiano Hessel |
MIPS and RISC-V: Evaluating Virtualization Trade-off for Edge Devices. |
WF-IoT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ralf Ramsauer, Stefan Huber, Konrad Schwarz, Jan Kiszka, Wolfgang Mauerer |
Static Hardware Partitioning on RISC-V: Shortcomings, Limitations, and Prospects. |
WF-IoT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ahmed Kamaleldin, Diana Göhringer |
A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems. |
FPL |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Luca Bertaccini, Gianna Paulin, Tim Fischer 0001, Stefan Mach, Luca Benini |
MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores. |
ARITH |
2022 |
DBLP DOI BibTeX RDF |
|
13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías |
PERCIVAL: Open-Source Posit RISC-V Core With Quire Capability. |
ARITH |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jonas Gava, Guilherme Dorneles, Ricardo Reis 0001, Rafael Garibotti, Luciano Ost |
Soft Error Assessment of CNN Inference Models Running on a RISC-V Processor. |
ICECS 2022 |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hailong Wu, Jindong Li, Xiang Chen |
Implementation of CNN Heterogeneous Scheme Based on Domestic FPGA with RISC-V Soft Core CPU. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Sheng Zuo, Junjie Zhuang, Yao Liu, Mingyu Wang, Zhiyi Yu |
Hardware Based RISC-V Instruction Set Randomization. |
ICTA |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Liu Lu |
Design of A Programmable PCI-E Encryption System Based on RISC-V. |
ISCSIC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Konrad-Felix Krentz, Thiemo Voigt |
Reducing Trust Assumptions with OSCORE, RISC-V, and Layer 2 One-Time Passwords. |
FPS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Mao-Hsu Yen, Cheng-Hao Tsou, Ssu-Chi Lin, Che-Wei Chang, Yih-Hsia Lin, Yuan-Fu Ku, Chi-Lin Chiang |
VLSI Implementation of RISC MCU with In-Circuit Debugger. |
ICKII |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti 0001 |
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. |
ESSCIRC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri |
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. |
ApplePies |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy |
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Daniel S. Truesdell, Xinjian Liu, Jacob Breiholz, Shourya Gupta, Shuo Li 0008, Benton H. Calhoun |
NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Zhongpan Wu, Karim Hammad, Abel Beyene, Yunus Dawji, Ebrahim Ghafar-Zadeh, Sebastian Magierowski |
An FPGA Implementation of A Portable DNA Sequencing Device Based on RISC-V. |
NEWCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Felix Böseler, Jörg Walter 0001, Behnam Razi Perjikolaei |
A Comparison of Virtual Platform Simulation Solutions for Timing Prediction of Small RISC-V Based SoCs. |
FDL |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Tobias Cloosters, David Paaßen, Jianqiang Wang, Oussama Draissi, Patrick Jauernig, Emmanuel Stapf, Lucas Davi, Ahmad-Reza Sadeghi |
RiscyROP: Automated Return-Oriented Programming Attacks on RISC-V and ARM64. |
RAID |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jean-Michel Gorius, Simon Rokicki, Steven Derrien |
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. |
FPT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Antonov |
Superscalar Out-of-Order RISC-V ASIP Based on Programmable Hardware Generator with Decoupled Computations and Flow Control. |
MECO |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Uzair Sharif, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
COMPAS: Compiler-assisted Software-implemented Hardware Fault Tolerance for RISC-V. |
MECO |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Tatsuya Tsuchiya, Kanemitsu Ootsu, Takashi Yokota, Shun Kojima |
Assembly code translation from ARM64 to RISC-V. |
SNPD-Summer |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Bobby D. Birrer, Carlos Salazar |
Improving Student Comprehension with Logisim-based RISC Processors. |
FIE |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hung-Ming Lai, Jenq-Kuen Lee |
Efficient Support of the Scan Vector Model for RISC-V Vector Extension. |
ICPP Workshops |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Xiao Hu, Yaohua Wang, Xuan Gao |
Work-in-Progress: RISC-V Based Low-cost Embedded Trace Processing System. |
CASES |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler |
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. |
RSP |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jorge Reis, Jarbas Silveira, César A. M. Marcon |
Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA. |
LADC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Zahra Azad, Guowei Yang, Rashmi Agrawal 0001, Daniel Petrisko, Michael B. Taylor, Ajay Joshi |
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation. |
ISLPED |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Eleonora Vacca, Corrado De Sio, Sarah Azimi |
Layout-oriented radiation effects mitigation in RISC-V soft processor. |
CF |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Gheorghe Pojoga, Kostas Papagiannopoulos |
Low-latency implementation of the GIFT cipher on RISC-V architectures. |
CF |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Federico Ficarelli, Andrea Bartolini, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini |
Meet Monte Cimone: exploring RISC-V high performance compute clusters. |
CF |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Simon Tollec, Mihail Asavoae, Damien Couroussé, Karine Heydemann, Mathieu Jan |
Exploration of Fault Effects on Formal RISC-V Microarchitecture Models. |
FDTC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Cosmin-Andrei Popovici, Andrei Stan |
Extending a RISC-V Core with a CAN-FD Communication Unit. |
ICSTCC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Junwei Wu, Xin Zheng 0001, Shaofen Zeng, Huaien Gao, Xiaoming Xiong |
High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP. |
HP3C |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Vladimir Ushakov, Sampo Sovio, Qingchao Qi, Vijayanand Nayani, Valentin Manea, Philip Ginzboorg, Jan-Erik Ekberg |
Trusted Hart for Mobile RISC-V Security. |
TrustCom |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Ingo Hoyer, Alexander Utz, André Lüdecke, Mike Richter, Felix Wichum, Pierre Gembaczka, Kerstin Köhler, Maurice Rohr, Christoph Hoog Antink, Karsten Seidl |
Detection of atrial fibrillation with an optimized neural network on a RISC-V-based microcontroller for efficient integration into ECG patches. |
MeMeA |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Tian Zheng, Gang Cai, Zhihong Huang |
A Soft RISC-V Processor IP with High-performance and Low-resource consumption for FPGA. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman |
A RISC-V-based Research Platform for Rapid Design Cycle. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Endri Taka, George Lentaris, Dimitrios Soudris |
Improving the performance of RISC-V softcores on FPGA by exploiting PVT variability and DVFS. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
Spectre attack detection with Neutral Network on RISC-V processor. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jonas Kühne, Michele Magno, Luca Benini |
Parallelizing Optical Flow Estimation on an Ultra-Low Power RISC-V Cluster for Nano-UAV Navigation. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao 0001, Fan Yang 0001 |
An Automated Compiler for RISC-V Based DNN Accelerator. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Siu Hong Loh, You Hong Liew, Jia Jia Sim |
VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM). |
ICCSCE |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Valentin Martinoli, Yannick Teglia, Abdellah Bouagoun, Régis Leveugle |
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel. |
IOLTS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Fernando Fernandes dos Santos, Angeliki Kritikakou, Olivier Sentieys |
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform. |
IOLTS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Andrea Bartolini, Federico Ficarelli, Emanuele Parisi, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, Luca Benini |
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers. |
SOCC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Fabian Kempf, Julian Höfer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker 0001 |
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. |
SOCC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Riku Takayama, Jubee Tada |
An Implementation of a Pattern Matching Accelerator on a RISC-V Processor. |
CANDARW |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Kari Hepola, Joonas Multanen, Pekka Jääskeläinen |
OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. |
ASAP |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini |
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. |
ASAP |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Lucas Klemmer, Manfred Schlägl, Daniel Große |
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V. |
ACM Great Lakes Symposium on VLSI |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Pascal Pieper, Vladimir Herdt, Rolf Drechsler |
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. |
ACM Great Lakes Symposium on VLSI |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Gaëtan Leplus, Olivier Savry, Lilian Bossuet |
Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor. |
HOST |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Edian B. Annink, Gerard K. Rauwerda, Edwin A. Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi |
Preventing Soft Errors and Hardware Trojans in RISC-V Cores. |
DFT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Luca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi 0001, Marco Ottavi |
Is RISC-V ready for Space? A Security Perspective. |
DFT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Douglas A. dos Santos, André Martins Pio de Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo |
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip. |
DFT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jonathas Silveira, Lucas Castro, Victor Araújo, Rodrigo Zeli, Daniel Lazari, Marcelo Guedes, Rodolfo Azevedo, Lucas Wanner 0001 |
Prof5: A RISC-V profiler tool. |
SBAC-PAD |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Guillaume Soulard, Gabriel P. Lachance, Élodie Boisselier, Mounir Boukadoum, Amine Miled 0001 |
RISC-V Based Processor Architecture for an Embedded Visible Light Spectrophotometer. |
CCECE |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Dexing Qin, Xue Bai, Yiliang Wu, Yendo Hu |
Design and Implementation of Neural Network Accelerated SOC Based on Small RISC-V Processor. |
EITCE |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Nicholas Gordon, Kevin T. Pedretti, John R. Lange |
Porting the Kitten Lightweight Kernel Operating System to RISC-V. |
ROSS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | M. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J. |
Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Asmit De, Swaroop Ghosh |
HeapSafe: Securing Unprotected Heaps in RISC-V. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
13 | V. Naveen Chander, Kuruvilla Varghese |
A Soft RISC-V Vector Processor for Edge-AI. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Vázquez, Alfonso Rodríguez 0002, Andrés Otero, Eduardo de la Torre |
Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals |
peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Guillem Cabo, Gerard Candón, Xavier Carril, Max Doblas, Marc Domínguez, Alberto González 0004, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Francesco Minervini, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Víctor Soria 0001, Alejandro Suanes, Iván Vargas, Roger Figueras, Pau Fontova, Joan Marimon, Víctor Montabes, Adrián Cristal, Carles Hernández 0001, Ricardo Martínez, Miquel Moretó, Francesc Moll, Oscar Palomar, Marco A. Ramírez, Antonio Rubio 0001, Jordi Sacristán, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luís Villa |
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías |
Customizing the CVA6 RISC-V Core to Integrate Posit and Quire Instructions. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Dörflinger, Benedikt Kleinbeck, Mark Albers, Harald Michalik, Martin Moya |
A Framework for Fault Tolerance in RISC-V. |
DASC/PiCom/CBDCom/CyberSciTech |
2022 |
DBLP DOI BibTeX RDF |
|
13 | M. K. Aparna Nair, Vishwas Vasuki Gautam, Abhishek Revinipati, J. Soumya |
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture. |
VDAT |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Jun Liu, Ting Chong, Liang Liu, Xige Zhang |
Software Solution of Secure Debug Based on RISC-V CPU. |
ICCSIE |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Srikrishna Vasudev, Kartickraj K, Anuj Grover |
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Honglin Kuang, Yifan Zhao, Jun Han 0003 |
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Lucas Klemmer, Daniel Große |
Waveform-based performance analysis of RISC-V processors: late breaking results. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hsu-Kang Dow, Tuo Li 0001, Sri Parameswaran |
HWST128: complete memory safety accelerator on RISC-V with metadata compression. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Hongyi Lu, Fengwei Zhang |
Raven: a novel kernel debugging tool on RISC-V. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Huimin Li 0004, Nele Mentens, Stjepan Picek |
A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Mihaela Damian, Julian Oppermann, Christoph Spang 0001, Andreas Koch 0001 |
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Muhammet Cihat Mumcu, Ihsan Çiçek, Salih Bayar |
Performance Evaluation of Lightweight Cryptographic Algorithms on RISC-V. |
SIU |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Alejandra Sanchez-Flores, Lluc Alvarez, Bartomeu Alorda-Ladaria |
A review of CNN accelerators for embedded systems based on RISC-V. |
COINS |
2022 |
DBLP DOI BibTeX RDF |
|
13 | Stefano Di Mascio |
Spin-in of RISC-V Processors in Space Embedded Systems. |
|
2022 |
RDF |
|
13 | Marco Cococcioni, Federico Rossi 0003, Emanuele Ruffaldi, Sergio Saponara |
Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE. |
Neural Comput. Appl. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Latif Akçay, Siddika Berna Örs |
Comparison of RISC-V and transport triggered architectures for a postquantum cryptography application. |
Turkish J. Electr. Eng. Comput. Sci. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler |
Toward RISC-V CSR Compliance Testing. |
IEEE Embed. Syst. Lett. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Florian Zaruba, Fabian Schuiki, Luca Benini |
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing. |
IEEE Micro |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Ralf Hemmecke |
RISC Ph.D. studies program. |
ACM Commun. Comput. Algebra |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Pietro Nannipieri, Stefano Di Matteo, Luca Zulberti, Francesco Albicocchi, Sergio Saponara, Luca Fanucci |
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Ba-Anh Dao, Trong-Thuc Hoang, Anh-Tien Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
Correlation Power Analysis Attack Resisted Cryptographic RISC-V SoC With Random Dynamic Frequency Scaling Countermeasure. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Kuniyasu Suzaki, Kenta Nakajima, Tsukasa Oi, Akira Tsukamoto |
TS-Perf: General Performance Measurement of Trusted Execution Environment and Rich Execution Environment on Intel SGX, Arm TrustZone, and RISC-V Keystone. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee, Seung-Yeong Lee, Jae-Hyoung Lee, Woojoo Lee |
Developing a Multicore Platform Utilizing Open RISC-V Cores. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini |
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Gianna Paulin, Renzo Andri, Francesco Conti 0001, Luca Benini |
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes. |
IEEE Trans. Emerg. Top. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, Zhiyi Yu |
A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. |
IEEE Trans. Circuits Syst. II Express Briefs |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Satyajit Bora, Roy Paily |
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications. |
IEEE Trans. Circuits Syst. II Express Briefs |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Fabian Schuiki, Florian Zaruba, Torsten Hoefler, Luca Benini |
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores. |
IEEE Trans. Computers |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Stefano Di Mascio, Alessandra Menicucci, Eberhard K. A. Gill, Gianluca Furano, Claudio Monteleone |
Open-source IP cores for space: A processor-level perspective on soft errors in the RISC-V era. |
Comput. Sci. Rev. |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sugandha Tiwari, Neel Gala, Chester Rebeiro, V. Kamakoti 0001 |
PERI: A Configurable Posit Enabled RISC-V Core. |
ACM Trans. Archit. Code Optim. |
2021 |
DBLP DOI BibTeX RDF |
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13 | Vladimir A. Frolov, Vladimir A. Galaktionov, Vadim V. Sanzharov |
Investigation of RISC-V. |
Program. Comput. Softw. |
2021 |
DBLP DOI BibTeX RDF |
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13 | Shuenn-Yuh Lee, Yi-Wen Hung, Yao-Tse Chang, Chou-Ching K. Lin, Gia-Shing Shieh |
RISC-V CNN Coprocessor for Real-Time Epilepsy Detection in Wearable Application. |
IEEE Trans. Biomed. Circuits Syst. |
2021 |
DBLP DOI BibTeX RDF |
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