Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Hideo Okawara |
Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 322, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Jia Li 0022, Yu Huang, Dong Xiang |
Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 297-302, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Sreenivas Gangadhar, Spyros Tragoudas |
An analytical method for estimating SET propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, pp. 197-202, 2011, IEEE Computer Society, 978-1-61284-657-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
1 | Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly |
Evaluating yield and testing impact of sub-wavelength lithography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 200-205, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz, Sudhakar M. Reddy |
Forming multi-cycle tests for delay faults by concatenating broadside tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 51-56, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li 0001 |
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 21-26, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja |
Selecting the most relevant structural Fmax for system Fmax correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 99-104, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kyriakos Christou, Maria K. Michael, Stelios Neophytou |
Identification of critical primitive path delay faults without any path enumeration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 9-14, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Michael Keating |
The roadblocks to broad adoption of high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 251, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nourredine Akkouche, Salvador Mir, Emmanuel Simeu |
Ordering of analog specification tests based on parametric defect level estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 301-306, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Takahiro Hanyu |
Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 258, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato |
Path clustering for adaptive test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 15-20, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marcello Coppola |
3D self testing with Spidergon STNoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 327, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sreejit Chakravarty |
Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 350, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Rubin A. Parekhji |
Innovative practices session 1C: Innovative practices in RF test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 39, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Irith Pomeranz, Sudhakar M. Reddy |
On multiple bridging faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 221-226, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yiwen Shi, Wan-Chan Hu, Jennifer Dworak |
Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 319-324, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zhen Chen, Dong Xiang |
Low-capture-power at-speed testing using partial launch-on-capture test scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 141-146, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Michail Maniatakos, Yiorgos Makris |
Workload-driven selective hardening of control state elements in modern microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 159-164, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Saeed Shamshiri, Kwang-Ting Cheng |
Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 194-199, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Xuan-Lun Huang, Jiun-Lang Huang |
An ADC/DAC loopback testing methodology by DAC output offsetting and scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 289-294, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Arani Sinha |
Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 259, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis 0001, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira 0001 |
Low-sensitivity to process variations aging sensor for automotive safety-critical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 238-243, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sandra Irobi, Zaid Al-Ars, Said Hamdioui |
Bit line coupling memory tests for single-cell fails in SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 27-32, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Salvador Mir, Haralampos-G. D. Stratigopoulos, Ahcène Bounceur |
Density estimation for analog/RF test problem solving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 41, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jose G. Mena, Richard Deken, James E. Coker, Mark S. Johnstone, Sergio R. Ramirez, Peter Frey |
High level synthesis of a Front End filter and DSP engine for analog to digital conversion - a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 252, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Shyam Kumar Devarakond, Shreyas Sen, Soumendu Bhattacharya, Abhijit Chatterjee |
Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 337-342, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Szu-Pang Mu, Mango Chia-Tso Chao |
Theoretical analysis for low-power test decompression using test-slice duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 147-152, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kee Sup Kim |
Panel 12C: Apprentice - VTS edition judging session. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 355, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jupiter Hu |
Overview of flexible electronics from ITRI's viewpoint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 84, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Viktor Froese, Rüdiger Ibers, Sybille Hellebrand |
Reusing NoC-infrastructure for test data compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 227-231, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
Detecting NBTI induced failures in SRAM core-cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 75-80, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Bozena Kaminska, I. L. McWalter |
Special session 9B: New topic test facilities and infrastructure in Canada. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 281, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Fahad Ahmed, Linda Milor |
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 63-68, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty |
Board-level fault diagnosis using Bayesian inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 244-249, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kwang-Ting Cheng |
Innovative practices session 2C: Design, fabrication and test of flexible electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 81, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kwang-Ting Cheng, Tsung-Ching Huang |
Design, analysis, and test of low-power and reliable flexible electronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 82, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ke Peng, Jason Thibodeau, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
A novel hybrid method for SDD pattern grading and selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 45-50, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li |
CSER: BISER-based concurrent soft-error resilience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 153-158, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 188-193, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zijian He, Tao Lv 0001, Huawei Li 0001, Xiaowei Li 0001 |
Fast path selection for testing of small delay defects considering path correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 3-8, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Young Moon Kim, Tze Wee Chen, Yoshio Kameda, Masayuki Mizuno, Subhasish Mitra |
Gate-oxide early-life failure identification using delay shifts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 69-74, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Haralampos-G. D. Stratigopoulos |
Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 257, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Haralampos-G. D. Stratigopoulos |
Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 353, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai |
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 263-268, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Abhijit Chatterjee, Friedrich Taenzler |
Low cost test and tuning of RF circuits and systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 42, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Haralampos-G. D. Stratigopoulos |
Special session 4C: Thesis research poster session. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 131, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | William S. Wong 0001 |
Fabrication and testing of large-area flexible electronics for displays and sensor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 83, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Nitin Yogi, Vishwani D. Agrawal |
Application of signal and noise theory to digital VLSI testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 215-220, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Adit D. Singh, Chao Han, Xi Qian |
An output compression scheme for handling X-states from over-clocked delay tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 57-62, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sarveswara Tammali |
Industrial practices of test cost reduction: Perspective, current design practices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 124, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Cihan Tunc, Mehdi Baradaran Tahoori |
On-the-fly variation tolerant mapping in crossbar nano-architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 105-110, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Karim Arabi |
Special session 6C: New topic mixed-signal test impact to SoC commercialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 212, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo |
Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 33-38, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yang Zhao 0001, Krishnendu Chakrabarty |
Pin-count-aware online testing of digital microfluidic biochips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 111-116, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Christopher J. Clark |
iMajik: Making 1149.1 TAPs disappear and reappear in SoCs and 3D packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 117-122, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Suriyaprakash Natarajan |
Innovative practices session 9C: Implications of power delivery network for validation and testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 282, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kee Sup Kim |
Panel 4A: Apprentice - VTS edition: Season 3. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 129, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sandip Ray, Jayanta Bhadra |
Innovative practices session 7C: Verification and testing challenges in high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 250, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Ilia Polian |
Special session 4B: Panel low-power test and noise-aware test: Foes or friends? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 130, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Chien-Chih Yu, John P. Hayes |
Scalable and accurate estimation of probabilistic behavior in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 165-170, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Dongok Kim, Irith Pomeranz, M. Enamul Amyeen, Srikanth Venkataraman |
Defect diagnosis based on DFM guidelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 206-211, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mingjing Chen, Alex Orailoglu |
VDDmin test optimization for overscreening minimization through adaptive scan chain masking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 313-318, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab |
At-speed scan test with low switching activity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 177-182, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi 0001, Rubin A. Parekhji |
A generic low power scan chain wrapper for designs using scan compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 135-140, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Yanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra |
Concurrent autonomous self-test for uncore components in system-on-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 232-237, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mokhtar Hirech |
Test cost and test power conflicts: EDA perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 126, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji |
Test time reduction using parallel RF test techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 40, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Smriti Gupta |
Innovative practices session 5C: Post-silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 171, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Karim Arabi |
Power noise and its impact on production test and validation of SoC devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 285, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Vishwanath Natarajan, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee |
A holistic approach to accurate tuning of RF systems for large and small multiparameter perturbations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 331-336, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | K. Arnold |
Adaptive test delivers wide range of sophisticated test solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 125, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Swarup Bhunia, Anand Raghunathan |
Special session 11B: Hot topic hardware security: Design, test and verification issues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 349, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Hsiu-Ming Chang 0001, Kuan-Yu Lin, Kwang-Ting Cheng |
Calibration-assisted production testing for digitally-calibrated ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 295-300, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Marcelo Lubaszewski, Érika F. Cota |
Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 354, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sean H. Wu, Sreejit Chakravarty, Li-C. Wang |
Impact of multiple input switching on delay test under process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 87-92, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | D. Varma, D. Mackay, P. Thiruchelvam |
Easing the verification bottleneck using high level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 253-254, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Zhen Chen, Sharad C. Seth, Dong Xiang |
A novel hybrid delay testing scheme with low test power, volume, and time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 307-312, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sarveswara Tammali |
Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 123, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Sandeep Bhatia |
Low power compression architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 183-187, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | |
28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![IEEE Computer Society, 978-1-4244-6648-1 The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
1 | Eli Chiprout |
Power delivery dynamics and its impact on silicon validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 283, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham |
Multitone digital signal based test for RF receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 343-348, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Christian G. Zoellin, Hans-Joachim Wunderlich |
Low-power test planning for arbitrary at-speed delay-test clock schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 93-98, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg |
A structured and scalable test access architecture for TSV-based 3D stacked ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA, pp. 269-274, 2010, IEEE Computer Society, 978-1-4244-6648-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
1 | Kun Young Chung, Sandeep K. Gupta 0001 |
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 103-110, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Keith A. Jenkins, Lionel Li |
A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 185-188, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Joon-Sung Yang, Nur A. Touba |
Automated Selection of Signals to Observe for Efficient Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 79-84, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Tao Lv 0001, Huawei Li 0001, Xiaowei Li 0001 |
Automatic Selection of Internal Observation Signals for Design Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 203-208, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia |
Effective and Efficient Test Pattern Generation for Small Delay Defect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 111-116, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz |
Restrict Encoding for Mixed-Mode BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 179-184, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Pankaj Pant, Joshua Zelman |
Understanding Power Supply Droop during At-Speed Scan Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 227-232, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Andrew Piziali |
Panel: Functional Verification Planning and Management - Are Good Intentions Good Enough? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 338, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Sunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang 0001 |
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 152-157, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Bernard Courtois, Ali Shakouri |
Microscale and Nanoscale Thermal Characterization of Integrated Circuit Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 241, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li 0001 |
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 15-20, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | A. Hakan Baba, Subhasish Mitra |
Testing for Transistor Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 215-220, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker 0001 |
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 21-26, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu |
Multiple-Fault Diagnosis Using Faulty-Region Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 123-128, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi |
Soft-Error Hardening Designs of Nanoscale CMOS Latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 41-46, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|