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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19541 occurrences of 5230 keywords
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Results
Found 53773 publication records. Showing 53773 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | M. M. Adams, Philip B. Clayton |
ClawZ: Cost-Effective Formal Verification for Control Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 7th International Conference on Formal Engineering Methods, ICFEM 2005, Manchester, UK, November 1-4, 2005, Proceedings, pp. 465-479, 2005, Springer, 3-540-29797-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
industrial formal verification, ProofPower, Eurofighter Typhoon, Ada, refinement, Z, control systems, safety-critical software, Simulink, real-time software, formal proof |
23 | Farn Wang |
Symbolic Verification of Distributed Real-Time Systems with Complex Synchronizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 7th International Conference on Formal Engineering Methods, ICFEM 2005, Manchester, UK, November 1-4, 2005, Proceedings, pp. 300-314, 2005, Springer, 3-540-29797-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
model-checking, verification, real-time, synchronization, distributed |
23 | Jens Oehlerking, Abhishek Dhama, Oliver E. Theel |
Towards Automatic Convergence Verification of Self-stabilizing Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Self-Stabilizing Systems ![In: Self-Stabilizing Systems, 7th International Symposium, SSS 2005, Barcelona, Spain, October 26-27, 2005, Proceedings, pp. 198-213, 2005, Springer, 3-540-29814-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Verification, Distributed Algorithms, Convergence, Hybrid Systems, Self-Stabilization, Lyapunov Functions, Piecewise Affine Systems |
23 | Lester O. Lobo, James D. Arthur |
Local and global analysis: complementary activities for increasing the effectiveness of requirements verification and validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference (2) ![In: Proceedings of the 43nd Annual Southeast Regional Conference, 2005, Kennesaw, Georgia, Alabama, USA, March 18-20, 2005, Volume 2, pp. 256-261, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification, validation, requirements, analysis |
23 | Nikolai Kosmatov |
Constraint Solving for Sequences in Software Validation and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INAP ![In: Declarative Programming for Knowledge Management, 16th International Conference on Applications of Declarative Programming and Knowledge Management, INAP 2005, Fukuoka, Japan, October 22-24, 2005, Revised Selected Papers, pp. 25-37, 2005, Springer, 3-540-69233-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
verification, validation, sequences, constraint solver |
23 | Youngsik Kim, Parija Sule, Nazanin Mansouri |
Exploiting PSL standard assertions in a theorem-proving-based verification environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 400-403, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
assertion-based design, modeling, verification, theorem-proving, formal semantics, PSL |
23 | Sadik Ezer, Scott Johnson |
Smart diagnostics for configurable processor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 789-794, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded test-bench control, coverage, functional verification, diagnostics, configurable processors |
23 | Josep Domingo-Ferrer |
On the Synergy Between Certificate Verification Trees and PayTree-like Micropayments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroPKI ![In: Public Key Infrastructure, First European PKIWorkshop: Research and Applications, EuroPKI 2004, Samos Island, Greece, June 25-26, 2004, Proceedings, pp. 180-190, 2004, Springer, 3-540-22216-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
PKI and eCommerce, Certificate Directories, Coin-Based Payments, PayTree, Certificate Verification Trees, Protocols, Micropayments |
23 | Pao-Ann Hsiung, Shang-Wei Lin 0001 |
Formal Design and Verification of Real-Time Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APLAS ![In: Programming Languages and Systems: Second Asian Symposium, APLAS 2004, Taipei, Taiwan, November 4-6, 2004. Proceedings, pp. 382-397, 2004, Springer, 3-540-23724-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scheduling, formal verification, code generation, software components, application framework, UML modeling, real-time embedded software, formal synthesis |
23 | Pao-Ann Hsiung, Shang-Wei Lin 0001 |
Automatic Synthesis and Verification of Real-Time Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 12-21, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scheduling, formal verification, code generation, software components, Application framework, UML modeling, real-time embedded software |
23 | Nirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar |
An Efficient Method to Generate Test Vectors for Combinational Cell Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 769-772, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
combinational cell verification, Gray-code, vector generation, Euler tour |
23 | Fang Yu 0001, Bow-Yaw Wang |
Toward Unbounded Model Checking for Region Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 20-33, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Region automata, Real-time systems, Model checking, Verification, Induction, BMC |
23 | Theo C. Ruys, Ed Brinksma |
Managing the verification trajectory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(2), pp. 246-259, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Model checking, Software configuration management, Computer-aided verification |
23 | Luca Durante, Riccardo Sisto, Adriano Valenzano |
Automatic testing equivalence verification of spi calculus specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Softw. Eng. Methodol. ![In: ACM Trans. Softw. Eng. Methodol. 12(2), pp. 222-284, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
equivalence verification, Cryptographic protocols, state space exploration |
23 | Eva Rose |
Lightweight Bytecode Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Autom. Reason. ![In: J. Autom. Reason. 31(3-4), pp. 303-334, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
data flow analysis, proof-carrying code, bytecode verification |
23 | Xiaodong Yi 0002, Xuejun Yang |
A Security Verification Method for Information Flow Security Policies Implemented in Operating Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 5th International Conference, ICICS 2003, Huhehaote, China, October 10-13, 2003, Proceedings, pp. 280-291, 2003, Springer, 3-540-20150-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Information Flow Security Policy, Security Verification, Secure Operating System |
23 | Vamsi Krishna Madasu, Mohd. Hafizuddin Mohd. Yusof, Madasu Hanmandlu, Kurt Kubik |
Off-Line Signature Verification and Forgery Detection System Based on Fuzzy Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Conference on Artificial Intelligence ![In: AI 2003: Advances in Artificial Intelligence, 16th Australian Conference on Artificial Intelligence, Perth, Australia, December 3-5, 2003, Proceedings, pp. 1003-1013, 2003, Springer, 3-540-20646-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Box-Method, Fuzzy Modeling, Signature Verification, Forgery detection |
23 | Vlad Rusu |
Verification Using Test Generation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FME ![In: FME 2002: Formal Methods - Getting IT Right, International Symposium of Formal Methods Europe, Copenhagen, Denmark, July 22-24, 2002, Proceedings, pp. 252-271, 2002, Springer, 3-540-43928-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
electronic purse, Formal verification, conformance testing |
23 | Steven Shapiro, Yves Lespérance, Hector J. Levesque |
The cognitive agents specification language and verification environment for multiagent systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAMAS ![In: The First International Joint Conference on Autonomous Agents & Multiagent Systems, AAMAS 2002, July 15-19, 2002, Bologna, Italy, Proceedings, pp. 19-26, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
agent specification languages, theorem proving, proof assistants, verification tools |
23 | Marieke Huisman, Bart Jacobs 0001, Joachim van den Berg |
A case study in class library verification: Java's vector class. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(3), pp. 332-352, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Java, Specification, Program verification, Invariant |
23 | Philip W. L. Fong, Robert D. Cameron |
Proof linking: modular verification of mobile programs in the presence of lazy, dynamic linking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Softw. Eng. Methodol. ![In: ACM Trans. Softw. Eng. Methodol. 9(4), pp. 379-409, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
correctness conditions, proof linking, verification protocol, virtual machine architecture, Java, modularity, safety, mobile code, dynamic linking |
23 | Jörg Fischer 0002, Stefan Conrad 0001 |
Formalizing Timing Diagrams as Causal Dependencies for Verification Purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFM ![In: Integrated Formal Methods, Second International Conference, IFM 2000, Dagstuhl Castle, Germany, November 1-3, 2000, Proceedings, pp. 45-60, 2000, Springer, 3-540-41196-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hardware and software design, relational semantics, formal semantics, dynamic logic, timing diagrams, integrated verification, causal dependencies |
23 | Marinés Puig-Medina, Gülbin Ezer, Pavlos Konas |
Verification of configurable processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 426-431, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
configurable processor cores, system-on-chip, test generation, design verification, co-simulation, coverage analysis |
23 | Arne Borälv |
Case Study: Formal Verification of a Computerized Railway Interlocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 10(4), pp. 338-360, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Stålmarck's method, Formal verification, Railway interlocking |
23 | Eric Y. T. Juan, Jeffrey J. P. Tsai, Tadao Murata |
Compositional Verification of Concurrent Systems Using Petri-Net-Based Condensation Rules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 20(5), pp. 917-979, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
deadlock states, reachable markings, Petri nets, reachability analysis, compositional verification, boundedness, reachability graphs |
23 | Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton |
Combinational Verification based on High-Level Functional Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 803-808, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Combinational verification, Domain transformations, BDDs |
23 | Fong Pong, Michel Dubois 0001 |
Verification Techniques for Cache Coherence Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 29(1), pp. 82-126, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
state representation and expansion, finite state machine, shared-memory multiprocessors, cache coherence, protocol verification |
23 | Matteo Golfarelli, Dario Maio, Davide Maltoni |
On the Error-Reject Trade-Off in Biometric Verification Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 19(7), pp. 786-796, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Biometric verification systems, rejection error rate, statistical pattern recognition, human face, hand geometry, Bayes error rate |
23 | Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee |
VERILAT: verification using logic augmentation and transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 88-95, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
VERILAT, formal logic verification, implication-based methods, logic augmentation, logic transformations, logic testing |
23 | Fong Pong, Michel Dubois 0001 |
A New Approach for the Verification of Cache Coherence Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(8), pp. 773-787, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
symbolic expansion, formal verification, finite state machine, shared-memory multiprocessor, Cache coherence protocol |
23 | Oriol Roig, Jordi Cortadella, Enric Pastor |
Hierarchical gate-level verification of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 128-137, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hierarchical gate-level verification, state signals, computational complexity, logic testing, time complexity, asynchronous circuits, speed-independent circuits, complex gates |
23 | Xuhua Yang, Takeshi Furuhashi, Kenzo Obata, Yoshiki Uchikawa |
Constructing a High Performance Signature Verification System Using a GA Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANNES ![In: 2nd New Zealand Two-Stream International Conference on Artificial Neural Networks and Expert Systems (ANNES '95), November 20-23, 1995, Dunedin, New Zealand, pp. 170-173, 1995, IEEE Computer Society, 0-8186-7174-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Fuzzy Network, Feature Selection, GA, Signature Verification |
23 | Robert M. O'Keefe, Daniel E. O'Leary |
Expert system verification and validation: a survey and tutorial. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Rev. ![In: Artif. Intell. Rev. 7(1), pp. 3-42, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
ACM Categories and Subject Descriptors D.2.4 [Software Engineering] Program Verification - Validation, D.2.5 [Software Engineering] Testing and Debugging, 1.2 [Artificial Intelligence] Applications and Expert Systems, K.6.1 [Management of Computers and Information System] Project and People Management - Life Cycle |
22 | Manfred Broy |
Architecture Based Specification and Verification of Embedded Software Systems (Work in Progress). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISoLA ![In: Leveraging Applications of Formal Methods, Verification and Validation, Third International Symposium, ISoLA 2008, Porto Sani, Greece, October 13-15, 2008. Proceedings, pp. 1-13, 2008, Springer, 978-3-540-88478-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Large Scale Embedded Software Systems, Comprehensive Architecture, Verification, Specification |
22 | Patrice Chalin, Perry R. James, George Karabotsos |
An integrated verification environment for JML: architecture and early results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAVCBS ![In: Proceedings of the 2007 Conference Specification and Verification of Component-Based Systems, SAVCBS 2007, Dubrovnik, Croatia, September 3-4, 2007, pp. 47-53, 2007, ACM, 978-1-59593-721-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
JML4, integrated verification environment, Eclipse, java modeling language |
22 | Prosenjit Chatterjee |
Streamline verification process with formal property verification to meet highly compressed design cycle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 674-677, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
formal verification |
22 | Wen-Kui Chang, Chun-Yuan Chen |
Integrity-Enhanced Verification Scheme for Software-Intensive Organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis: Second International Conference, ATVA 2004, Taipei, Taiwan, ROC, October 31-November 3, 2004. Proceedings, pp. 402-414, 2004, Springer, 3-540-23610-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Software Capability Level, Software Integrity Level, ISO 9001:2000, Software Process Improvement (SPI), CMMI, Software Verification and Validation |
22 | Farn Wang |
Efficient Verification of Timed Automata with BDD-Like Data-Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VMCAI ![In: Verification, Model Checking, and Abstract Interpretation, 4th International Conference, VMCAI 2003, New York, NY, USA, January 9-11, 2002, Proceedings, pp. 189-205, 2003, Springer, 3-540-00348-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
model-checking, verification, data-structures, timed automata, BDD |
22 | Ricky W. Butler |
Formal Methods at NASA Langley. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 15th International Conference, TPHOLs 2002, Hampton, VA, USA, August 20-23, 2002, Proceedings, pp. 1-2, 2002, Springer, 3-540-44039-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Naoki Kobayashi 0001 |
Types and higher-order recursion schemes for verification of higher-order programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POPL ![In: Proceedings of the 36th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2009, Savannah, GA, USA, January 21-23, 2009, pp. 416-428, 2009, ACM, 978-1-60558-379-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
model checking, type system, higher-order recursion scheme |
22 | Alin Deutsch, Richard Hull 0001, Fabio Patrizi, Victor Vianu |
Automatic verification of data-centric business processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDT ![In: Database Theory - ICDT 2009, 12th International Conference, St. Petersburg, Russia, March 23-25, 2009, Proceedings, pp. 252-267, 2009, ACM, 978-1-60558-423-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Victor Vianu |
Automatic verification of database-driven systems: a new frontier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDT ![In: Database Theory - ICDT 2009, 12th International Conference, St. Petersburg, Russia, March 23-25, 2009, Proceedings, pp. 1-13, 2009, ACM, 978-1-60558-423-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Tarvo Raudvere, Ingo Sander, Axel Jantsch |
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6), pp. 1091-1103, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Jan B. Freuer, Göran Jerke, Joachim Gerlach, Wolfgang Nebel |
On the Verification of High-Order Constraint Compliance in IC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 26-31, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Katharina Weinberger, Slava Bulach, Robert P. Bosch Jr. |
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 937-938, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Alex X. Liu |
Formal Verification of Firewall Policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 1494-1498, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Gwo Giun Lee, He-Yuan Lin, Ming-Jiun Wang, Bo-Han Chen, Yuan-Long Cheng |
On the verification of multi-standard SoC'S for reconfigurable video coding based on algorithm/architecture co-exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, pp. 170-175, 2008, IEEE, 978-1-4244-2924-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad Talal Ibrahim, Ling Guan |
On-line signature verification by using most discriminating points. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR ![In: 19th International Conference on Pattern Recognition (ICPR 2008), December 8-11, 2008, Tampa, Florida, USA, pp. 1-4, 2008, IEEE Computer Society, 978-1-4244-2175-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Dipankar Das 0002, P. P. Chakrabarti 0001, Rajeev Kumar 0004 |
Functional verification of task partitioning for multiprocessor embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(4), pp. 44, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Containment checking, state space reduction, UML activity diagrams, multiprocessor embedded systems |
22 | Shuicheng Yan, Jianzhuang Liu, Xiaoou Tang, Thomas S. Huang |
Formulating Face Verification With Semidefinite Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Image Process. ![In: IEEE Trans. Image Process. 16(11), pp. 2802-2810, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Chien-Lin Huang, Chung-Hsien Wu |
Spoken Document Retrieval Using Multilevel Knowledge and Semantic Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Speech Audio Process. ![In: IEEE Trans. Speech Audio Process. 15(8), pp. 2551-2560, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Yu Qiao 0001, Jianzhuang Liu, Xiaoou Tang |
Offline Signature Verification Using Online Handwriting Registration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 18-23 June 2007, Minneapolis, Minnesota, USA, 2007, IEEE Computer Society, 1-4244-1179-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Alon Flaisher, Alon Gluska, Eli Singerman |
Case study: Integrating FV and DV in the Verification of the Intel CoreTM 2 Duo Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 7th International Conference, FMCAD 2007, Austin, Texas, USA, November 11-14, 2007, Proceedings, pp. 192-195, 2007, IEEE Computer Society, 0-7695-3023-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Holger Giese, Stefan Henkler, Martin Hirsch 0001 |
Combining Formal Verification and Testing for Correct Legacy Component Integration in Mechatronic UML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WADS ![In: Architecting Dependable Systems V [the book is a result from the WADS 2007 and the Third Workshop on the Role of Software Architecture for Testing and Analysis], pp. 248-272, 2007, Springer, 978-3-540-85570-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Jacob A. Abraham, Daniel G. Saab |
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 6, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Praveen Tiwari, Raj S. Mitra, Manu Chopra, Alok Jain |
Tutorial T4B: Formal Assertion-Based Verification in Industrial Setting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 7, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Fei Xie, Guowu Yang, Xiaoyu Song |
Component-based hardware/software co-verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 27-36, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | G. Zarri, Federico Colucci, F. Dupuis, Riccardo Mariani, Mario Pasquariello, G. Risaliti, C. Tibaldi |
On the verification of automotive protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 195-200, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Irem Aktug, Dilian Gurov |
State Space Representation for Verification of Open Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMAST ![In: Algebraic Methodology and Software Technology, 11th International Conference, AMAST 2006, Kuressaare, Estonia, July 5-8, 2006, Proceedings, pp. 5-20, 2006, Springer, 3-540-35633-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Fei Xie, James C. Browne |
Verification of Component-Based Software Application Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CBSE ![In: Component-Based Software Engineering, 9th International Symposium, CBSE 2006, Västerås, Sweden, June 29 - July 1, 2006, Proceedings, pp. 50-66, 2006, Springer, 3-540-35628-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Stefan Andrei, Albert Mo Kim Cheng |
Faster Verification of RTL-Specified Systems via Decomposition and Constraint Extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 5-8 December 2006, Rio de Janeiro, Brazil, pp. 67-76, 2006, IEEE Computer Society, 0-7695-2761-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Integrated Verification Approach during ADL-Driven Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 110-118, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler |
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings, pp. 3-10, 2006, IEEE Computer Society, 0-7695-2707-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna |
Post-reboot Equivalence and Compositional Verification of Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings, pp. 11-18, 2006, IEEE Computer Society, 0-7695-2707-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dejan Desovski, Bojan Cukic |
A Component-Based Approach to Verification and Validation of Formal Software Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WADS ![In: Architecting Dependable Systems IV [the book is a result of DSN 2006 workshops, Philadelphia, PA, USA], pp. 89-114, 2006, Springer, 978-3-540-74033-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Dejan Desovski, Bojan Cukic |
A Strategy for Verification of Decomposable SCR Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 11-18, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Fei Xie, Xiaoyu Song, Haera Chung, Ranajoy Nandi |
Translation-based co-verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 11-14 July 2005, Verona, Italy, Proceedings, pp. 111-120, 2005, IEEE Computer Society, 0-7803-9227-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Aysu Betin-Can, Tevfik Bultan, Xiang Fu 0001 |
Design for verification for asynchronously communicating Web services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WWW ![In: Proceedings of the 14th international conference on World Wide Web, WWW 2005, Chiba, Japan, May 10-14, 2005, pp. 750-759, 2005, ACM, 1-59593-046-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
design patterns, BPEL, asynchronous communication, composite web services |
22 | Tsung-Hsi Chiang, Lan-Rong Dung, Ming-Feng Yaung |
Modeling and formal verification of dataflow graph in system-level design using Petri net. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5674-5677, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Pao-Ann Hsiung, Yen-Hung Lin |
Modeling and Verification of Safety-Critical Systems Using Safecharts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE ![In: Formal Techniques for Networked and Distributed Systems - FORTE 2005, 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October 2-5, 2005, Proceedings, pp. 290-304, 2005, Springer, 3-540-29189-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Aysu Betin-Can, Tevfik Bultan, Mikael Lindvall, Benjamin Lux, Stefan Topp |
Application of design for verification with concurrency controllers to air traffic control software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 20th IEEE/ACM International Conference on Automated Software Engineering (ASE 2005), November 7-11, 2005, Long Beach, CA, USA, pp. 14-23, 2005, ACM, 1-58113-993-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
model checking, synchronization, design patterns, interfaces, concurrent programming |
22 | Nick Feamster |
Practical verification techniques for wide-area routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Commun. Rev. ![In: Comput. Commun. Rev. 34(1), pp. 87-92, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ying-Tsai Chang, Kwang-Ting Cheng |
Self-referential verification for gate-level implementations of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7), pp. 1102-1112, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Wei Zhang 0004, Haiyan Zhao, Hong Mei 0001 |
A Propositional Logic-Based Method for Verification of Feature Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 6th International Conference on Formal Engineering Methods, ICFEM 2004, Seattle, WA, USA, November 8-12, 2004, Proceedings, pp. 115-130, 2004, Springer, 3-540-23841-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Gerard J. Holzmann, Rajeev Joshi |
Model-Driven Software Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 11th International SPIN Workshop, Barcelona, Spain, April 1-3, 2004, Proceedings, pp. 76-91, 2004, Springer, 3-540-21314-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Isao Nakanishi, Naoto Nishiguchi, Yoshio Itoh, Yutaka Fukui |
On-Line Signature Verification Based on Discrete Wavelet Domain Adaptive Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICBA ![In: Biometric Authentication, First International Conference, ICBA 2004, Hong Kong, China, July 15-17, 2004, Proceedings, pp. 584-591, 2004, Springer, 3-540-22146-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Reiner Hähnle, Wojciech Mostowski |
Verification of Safety Properties in the Presence of Transactions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASSIS ![In: Construction and Analysis of Safe, Secure, and Interoperable Smart Devices, International Workshop, CASSIS 2004, Marseille, France, March 10-14, 2004, Revised Selected Papers, pp. 151-171, 2004, Springer, 3-540-24287-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Giorgio Delzanno |
Constraint-Based Verification of Parameterized Cache Coherence Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 23(3), pp. 257-301, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
constraints, abstractions, symbolic model checking, cache coherence protocols |
22 | Fady Copty, Amitai Irron, Osnat Weissberg, Nathan P. Kropp, Gila Kamhi |
Efficient debugging in a formal verification environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 4(3), pp. 335-348, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Counter-example, Model checking, Counterexample |
22 | Jun-Su Jang, Kuk-Hyun Han, Jong-Hwan Kim 0001 |
Quantum-Inspired Evolutionary Algorithm-Based Face Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation - GECCO 2003, Genetic and Evolutionary Computation Conference, Chicago, IL, USA, July 12-16, 2003. Proceedings, Part II, pp. 2147-2156, 2003, Springer, 3-540-40603-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Shaz Qadeer, Serdar Tasiran |
Promising Directions in Hardware Design Verification (invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 381-387, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan 0001, Gunnar Stålmarck, Curt Widdoes |
Formal verification methods: getting around the brick wall. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 576-577, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Ed Brinksma |
Verification is experimentation! ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 3(2), pp. 107-111, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Fumitaka Hoshino, Masayuki Abe, Tetsutaro Kobayashi |
Lenient/Strict Batch Verification in Several Groups. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 4th International Conference, ISC 2001, Malaga, Spain, October 1-3, 2001, Proceedings, pp. 81-94, 2001, Springer, 3-540-42662-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Byeong Min, Gwan Choi |
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 17-19 December 2001, Seoul, Korea, pp. 183-190, 2001, IEEE Computer Society, 0-7695-1414-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan |
VERILAT: verification using logic augmentation and transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9), pp. 1041-1051, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Brian D. Winters, Alan J. Hu |
Source-Level Transformations for Improved Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 599-602, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Ed Brinksma |
Verification Is Experimentation! ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR 2000 - Concurrency Theory, 11th International Conference, University Park, PA, USA, August 22-25, 2000, Proceedings, pp. 17-24, 2000, Springer, 3-540-67897-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Yonit Kesten, Amit Klein 0001, Amir Pnueli, Gil Raanan |
A Perfect Verification: Combining Model Checking with Deductive Analysis to Verify Real-Life Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Formal Methods ![In: FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume I, pp. 173-194, 1999, Springer, 3-540-66587-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Enrico Macii, Bernard Plessier, Fabio Somenzi |
Formal verification of digital systems by automatic reduction of data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1136-1156, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Bernd Finkbeiner, Zohar Manna, Henny Sipma |
Deductive Verification of Modular Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPOS ![In: Compositionality: The Significant Difference, International Symposium, COMPOS'97, Bad Malente, Germany, September 8-12, 1997. Revised Lectures, pp. 239-275, 1997, Springer, 3-540-65493-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Brian A. A. Antao, Arthur J. Brodersen |
Behavioral simulation for analog system design verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(3), pp. 417-429, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
22 | David K. Probst, Hon Fung Li |
Partial-Order Model Checking: A Guide for the Perplexed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 3rd International Workshop, CAV '91, Aalborg, Denmark, July, 1-4, 1991, Proceedings, pp. 322-331, 1991, Springer, 3-540-55179-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
delay-insensitive system, partial-order representation, recurrence structure, model checking, state explosion, state encoding |
22 | Nam Ling, Magdy A. Bayoumi |
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8), pp. 804-820, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Sriram K. Rajamani |
Verification, Testing and Statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 9th International Workshop, RV 2009, Grenoble, France, June 26-28, 2009. Selected Papers, pp. 25, 2009, Springer, 978-3-642-04693-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Ariel Cohen 0002, Amir Pnueli, Lenore D. Zuck |
Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings, pp. 121-134, 2008, Springer, 978-3-540-70543-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Sagar Chaki, Christian Schallhart, Helmut Veith |
Verification Across Intellectual Property Boundaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 19th International Conference, CAV 2007, Berlin, Germany, July 3-7, 2007, Proceedings, pp. 82-94, 2007, Springer, 978-3-540-73367-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Cindy Eisner |
PSL for Runtime Verification: Theory and Practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 7th International Workshop, RV 2007, Vancouver, Canada, March 13, 2007, Revised Selected Papers, pp. 1-8, 2007, Springer, 978-3-540-77394-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Eric Bodden, Laurie J. Hendren, Patrick Lam 0001, Ondrej Lhoták, Nomair A. Naeem |
Collaborative Runtime Verification with Tracematches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 7th International Workshop, RV 2007, Vancouver, Canada, March 13, 2007, Revised Selected Papers, pp. 22-37, 2007, Springer, 978-3-540-77394-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Huu Hai Nguyen, Cristina David, Shengchao Qin, Wei-Ngan Chin |
Automated Verification of Shape and Size Properties Via Separation Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VMCAI ![In: Verification, Model Checking, and Abstract Interpretation, 8th International Conference, VMCAI 2007, Nice, France, January 14-16, 2007, Proceedings, pp. 251-266, 2007, Springer, 978-3-540-69735-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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