Search results for "floorplanning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Sanjiv Taneja	DFT Aware Layout - Layout Aware DFT.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
10	Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz	The ISPD2005 placement contest and benchmark suite.	ISPD	2005	DBLP DOI BibTeX RDF	VLSI placement, benchmarks, physical design
10	Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie 0004	mPL6: a robust multilevel mixed-size placement engine.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-size placement, legalization, helmholtz equation, force-directed placement, multilevel optimization
10	Peng Li 0001, Yangdong Deng, Lawrence T. Pileggi	Temperature-Dependent Optimization of Cache Leakage Power Dissipation.	ICCD	2005	DBLP DOI BibTeX RDF
10	Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee	Wire-driven microarchitectural design space exploration.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
10	Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen 0001	A New Buffer Planning Algorithm Based on Room Resizing.	EUC	2005	DBLP DOI BibTeX RDF
10	S. A. Moghaddam, Nasser Masoumi, Caro Lucas	A Stochastic Power-Supply Noise Reduction Technique Using Max-Flow Algorithm and Decoupling Capacitance.	IWSOC	2005	DBLP DOI BibTeX RDF
10	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	Floorplan-aware automated synthesis of bus-based communication architectures.	DAC	2005	DBLP DOI BibTeX RDF	systems-on-chip, communication synthesis
10	Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001	Incremental exploration of the combined physical and behavioral design space.	DAC	2005	DBLP DOI BibTeX RDF	high-level synthesis, floorplan, incremental
10	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
10	Stelian Alupoaei, Srinivas Katkoori	Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	net clustering, macro-cell placement, cluster growth, wirelength optimization, simulated annealing
10	Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke	Wirelength Reduction Using 3-D Physical Design.	PATMOS	2004	DBLP DOI BibTeX RDF
10	Thomas Brandtner, Robert Weigel	SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level.	DATE	2004	DBLP DOI BibTeX RDF
10	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	A buffer planning algorithm with congestion optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen 0001, Yici Cai, Chung-Kuan Cheng, Jun Gu	Buffer allocation algorithm with consideration of routing congestion.	ASP-DAC	2004	DBLP DOI BibTeX RDF
10	Monica Donno, Enrico Macii, Luca Mazzoni	Power-aware clock tree planning.	ISPD	2004	DBLP DOI BibTeX RDF	clock tree synthesis and routing, physical design and optimization, low-power design, digital design
10	Md. Saidur Rahman 0001, Kazuyuki Miura, Takao Nishizeki	Octagonal Drawings of Plane Graphs with Prescribed Face Areas.	WG	2004	DBLP DOI BibTeX RDF
10	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze	Accurate estimation of global buffer delay within a floorplan.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Ruiming Chen, Hai Zhou 0001	A Flexible Data Structure for Efficient Buffer Insertion.	ICCD	2004	DBLP DOI BibTeX RDF
10	Madhubanti Mukherjee, Ranga Vemuri	Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.	ICCD	2004	DBLP DOI BibTeX RDF
10	P. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala	Package-silicon co-design - Experiment with an SOC design.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Srinivasan Murali, Giovanni De Micheli	SUNMAP: a tool for automatic topology selection and generation for NoCs.	DAC	2004	DBLP DOI BibTeX RDF	systems on chip, mapping, networks on chip, topology, SystemC
10	David S. Kung 0001	Timing closure for low-FO4 microprocessor design.	DAC	2004	DBLP DOI BibTeX RDF	FO4, synthesis, placement, high performance
10	Frank Schmiedle, Rolf Drechsler, Bernd Becker 0001	Exact Routing with Search Space Reduction.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	forced cells, MDDs, Detailed routing, fixed point iteration
10	Zion Cien Shen, Chris C. N. Chu	Bounds on the number of slicing, mosaic, and general floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen	Twin binary sequences: a nonredundant representation for general nonslicing floorplan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Floorplan representations: Complexity and connections.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Baxter permutation, Floorplan representation, O-tree, mosaic floorplan, number of combinations, twin binary trees
10	Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo	An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.	FPL	2003	DBLP DOI BibTeX RDF
10	Scott Hauck	APHYDS: The Academic Physical Design Skeleton.	MSE	2003	DBLP DOI BibTeX RDF
10	Jyh Perng Fang, Sao-Jie Chen	Tile-graph-based power planning.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Enrico Macii, Massimo Poncino, Sabino Salerno	Combining wire swapping and spacing for low-power deep-submicron buses.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	low-power design, physical design, crosstalk, bus encoding
10	Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal	A novel ultra-fast heuristic for VLSI CAD steiner trees.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	routing, steiner trees, interconnect estimation
10	Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier 0002, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda	Optical and Electrical Testing of Latchup in I/O Interface Circuits.	ITC	2003	DBLP DOI BibTeX RDF
10	Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis	Microarchitecture evaluation with physical planning.	DAC	2003	DBLP DOI BibTeX RDF	microarchitecture evaluation, physical planning
10	Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang	Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen	A layout synthesis methodology for array-type analog blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
10	Russell Tessier	Fast placement approaches for FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	field-programmable gate arrays, synthesis, layout, Computer-aided design of VLSI
10	Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin	An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees.	DATE	2002	DBLP DOI BibTeX RDF
10	Juan de Vicente, Juan Lanchares, Román Hermida	FPGA Placement by Thermodynamic Combinatorial Optimization.	DATE	2002	DBLP DOI BibTeX RDF
10	Chunhong Chen	Physical design with multiple on-chip voltages.	ISPD	2002	DBLP DOI BibTeX RDF
10	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen	Twin binary sequences: a non-redundant representation for general non-slicing floorplan.	ISPD	2002	DBLP DOI BibTeX RDF
10	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
10	Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong	A Massively Parallel RC4 Key Search Engine.	FCCM	2002	DBLP DOI BibTeX RDF
10	Steven L. Teig	The X architecture: not your father's diagonal wiring.	SLIP	2002	DBLP DOI BibTeX RDF
10	Silke Salewski, Erich Barke	An Upper Bound for 3D Slicing Floorplans.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
10	Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong	Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap	RC delay metrics for performance optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Probir Sarkar, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centricfloorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
10	Chris C. N. Chu, D. F. Wong 0001	Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	buffer insertion, buffer sizing, closed form solution, interconnect optimization, wire sizing
10	Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	ECBL: an extended corner block list with solution space including optimum placement.	ISPD	2001	DBLP DOI BibTeX RDF
10	Rodolfo Castelló, Rym Mili, Ioannis G. Tollis	ViSta.	GD	2001	DBLP DOI BibTeX RDF
10	Josef Schmid, Timo Schüring, Christoph Smalla	Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow.	ISQED	2001	DBLP DOI BibTeX RDF
10	Dirk Stroobandt, Peter Verplaetse, Jan M. Van Campenhout	Generating synthetic benchmark circuits for evaluating CAD tools.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
10	Rodolfo Castelló, Rym Mili, Ioannis G. Tollis	An Algorithmic Framework for Visualizing Statecharts.	GD	2000	DBLP DOI BibTeX RDF
10	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
10	Erik A. McShane, Krishna Shenai	Correct-by-Design CAD Enhancement for EMI Signal Integrity.	ISQED	2000	DBLP DOI BibTeX RDF
10	Helvio P. Peixoto, Margarida F. Jacome, Ander Royo	A Tight Area Upper Bound for Slicing Floorplans.	VLSI Design	2000	DBLP DOI BibTeX RDF	Early area estimation, slicing floorplan, system level design
10	Sidney E. Benda	Physical Design of CMOS Chips in Six Easy Steps.	SOFSEM	2000	DBLP DOI BibTeX RDF
10	David M. Brooks, Vivek Tiwari, Margaret Martonosi	Wattch: a framework for architectural-level power analysis and optimizations.	ISCA	2000	DBLP DOI BibTeX RDF
10	William J. Dally, Andrew Chang 0001	The role of custom design in ASIC Chips.	DAC	2000	DBLP DOI BibTeX RDF
10	Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky	On wirelength estimations for row-based placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Amir H. Salek, Jinan Lou, Massoud Pedram	An integrated logical and physical design flow for deep submicron circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang	Slicing floorplans with boundary constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
10	Fung Yu Young, D. F. Wong 0001	Slicing Floorplans with Boundary Constraint.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Jason Cong, David Zhigang Pan	Interconnect Delay Estimation Models for Synthesis and Design Planning.	ASP-DAC	1999	DBLP DOI BibTeX RDF
10	Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran	An Incremental Floorplanner.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
10	Xiao Quan Li, Marwan A. Jabri	Machine learning-based VLSI cells shape function estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
10	Jörn Stohmann, Klaus Harbich, Markus Olbrich, Erich Barke	An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping.	FPL	1998	DBLP DOI BibTeX RDF
10	Andrew B. Kahng	Futures for partitioning in physical design (tutorial).	ISPD	1998	DBLP DOI BibTeX RDF
10	Ajay J. Daga, Peter Suaris	Interface Timing Verification Drives System Design.	DAC	1997	DBLP DOI BibTeX RDF
10	Joseph L. Ganley, James P. Cohoon	Rectilinear Steiner trees on a checkerboard.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	full-set decomposition, routing, exact algorithms, rectilinear Steiner tree
10	Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya	Geometric bipartitioning problem and its applications to VLSI.	VLSI Design	1996	DBLP DOI BibTeX RDF	geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
10	Peichen Pan, C. L. Liu 0001	Area minimization for floorplans.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu	A replication cut for two-way partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
10	Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone	Optimal and heuristic algorithms for solving the binding problem.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
10	Panagiotis Takis Metaxas, Grammati E. Pantziou, Antonios Symvonis	Parallel h-v Drawings of Binary Trees.	ISAAC	1994	DBLP DOI BibTeX RDF
10	Youssef Saab, Vasant B. Rao	Fast effective heuristics for the graph bisectioning problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
10	Christian Masson, Denis Barbier, Remy Escassut, Daniel Winer, Gregory Chevallier, Pierre François Zeegers	CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP.	EURO-DAC	1990	DBLP DOI BibTeX RDF
10	Noritake Yonezawa, Nobuyuki Nishiguchi, Atsushi Etani, Fumiaki Tsukuda, Ryuichi Hashishita	A VLSI floorplanner based on "balloon" expansion.	EURO-DAC	1990	DBLP DOI BibTeX RDF
10	Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa	A macrocell approach for VLSI processor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
10	Yen-Tai Lai, Sany M. Leinwand	Algorithms for floorplan design via rectangular dualization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
10	Marwan A. Jabri	Automatic Building of Graphs for Rectangular Dualisation.	DAC	1988	DBLP BibTeX RDF
10	Wayne H. Wolf	An object-oriented, procedural database for VLSI chip planning.	DAC	1986	DBLP DOI BibTeX RDF