Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
21	Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu	A power-driven multiplication instruction-set design method for ASIPs.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
21	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding.	ASAP	2005	DBLP DOI BibTeX RDF
21	Dipankar Das 0002, Rajeev Kumar 0004, P. P. Chakrabarti 0001	Dictionary Based Code Compression for Variable Length Instruction Encodings.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Jean-Pierre Georgé, Marie-Pierre Gleizes, Pierre Glize	Basic Approach to Emergent Programming: Feasibility Study for Engineering Adaptive Systems Using Self-organizing Instruction-Agents.	Engineering Self-Organising Systems	2005	DBLP DOI BibTeX RDF
21	Peter Petrov, Alex Orailoglu	Low-power instruction bus encoding for embedded processors.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
21	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Reducing instruction cache energy consumption using a compiler-based strategy.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	compiler optimizations, Leakage power, cache design
21	Nathan Clark, Manjunath Kudlur, Hyunchul Park 0001, Scott A. Mahlke, Krisztián Flautner	Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.	MICRO	2004	DBLP DOI BibTeX RDF
21	Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose, Oguz Ergin	Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.	PACS	2004	DBLP DOI BibTeX RDF
21	Jia Chen, Shengyuan Wang, Yuan Dong, Guilan Dai, Yang Yang	A Functionality Based Instruction Level Software Power Estimation Model for Embedded RISC Processors.	ICESS	2004	DBLP DOI BibTeX RDF
21	Duckki Kim, Youngsong Mun	An Experiment and Design of Web-Based Instruction Model for Collaboration Learning.	ICCSA (1)	2004	DBLP DOI BibTeX RDF
21	Kenneth W. Batcher, Robert A. Walker 0001	Cluster miss prediction for instruction caches in embedded networking applications.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	compulsory cache misses, hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch
21	David Jackson 0001	Automatic Synthesis of Instruction Decode Logic by Genetic Programming.	EuroGP	2004	DBLP DOI BibTeX RDF
21	Elena Gabriela Barrantes, David H. Ackley, Trek S. Palmer, Darko Stefanovic, Dino Dai Zovi	Randomized instruction set emulation to disrupt binary code injection attacks.	CCS	2003	DBLP DOI BibTeX RDF	automated diversity, language randomization, security, emulation, information hiding, obfuscation
21	Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.	ISVLSI	2003	DBLP DOI BibTeX RDF
21	Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel	Instruction Set Emulation for Rapid Prototyping of SoCs .	DATE	2003	DBLP DOI BibTeX RDF
21	Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke	LLVA: A Low-level Virtual Instruction Set Architecture.	MICRO	2003	DBLP DOI BibTeX RDF
21	Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir	Exploiting program hotspots and code sequentiality for instruction cache leakage management.	ISLPED	2003	DBLP DOI BibTeX RDF	leakage power, cache design
21	Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi	xLIW - a scaleable long instruction word.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Toshinori Sato	Exploiting Instruction Redundancy for Transient Fault Tolerance.	DFT	2003	DBLP DOI BibTeX RDF
21	Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Compiler-directed instruction cache leakage optimization.	MICRO	2002	DBLP DOI BibTeX RDF
21	Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung	Run-Time Adaptive Flexible Instruction Processors.	FPL	2002	DBLP DOI BibTeX RDF
21	Jean-Luc Gaudiot	Parallel Computer Architecture and Instruction-Level Parallelism.	Euro-Par	2002	DBLP DOI BibTeX RDF
21	Bengu Li, Rajiv Gupta 0001	Bit section instruction set extension of ARM for embedded applications.	CASES	2002	DBLP DOI BibTeX RDF	bit section operations, multimedia data, network processing
21	Adeel Abbas, Arslan Ahmed, Affan Ahmed, Waheed Uz Zaman Bajwa, Ahtasham Anwar, Sohail Abbasi	A retargetable tool-suite for the design of application specific instruction set processors using a machine description language.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
21	Francisco Rodríguez 0003, José Carlos Campelo, Juan José Serrano	A Memory Overhead valuation of the Interleaved Signature Instruction Stream.	DFT	2002	DBLP DOI BibTeX RDF
21	Martin Bravenboer, Eelco Visser	Rewriting Strategies for Instruction Selection.	RTA	2002	DBLP DOI BibTeX RDF
21	Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck	Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	coarse grained logic, code generation, software pipelining, vliw, reconfigurable processor, spatial computation
21	Pierre Michaud, André Seznec	Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors.	HPCA	2001	DBLP DOI BibTeX RDF
21	Soner Önder, Rajiv Gupta 0001	Instruction Wake-Up in Wide Issue Superscalars.	Euro-Par	2001	DBLP DOI BibTeX RDF
21	Apan Qasem, David B. Whalley, Xin Yuan 0001, Robert van Engelen	Using a Swap Instruction to Coalesce Loads and Stores.	Euro-Par	2001	DBLP DOI BibTeX RDF
21	Juan E. Gilbert, Dale-Marie Wilson	Domain Instruction Server (DIS).	ICALT	2001	DBLP DOI BibTeX RDF
21	Mike J. G. Lewis, L. E. M. Brackenbury	An Instruction Buffer for a Low-Power DSP.	ASYNC	2000	DBLP DOI BibTeX RDF
21	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Instruction-level power estimation for embedded VLIW cores.	CODES	2000	DBLP DOI BibTeX RDF
21	Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai	Compiler Optimization on Instruction Scheduling for Low Power.	ISSS	2000	DBLP DOI BibTeX RDF
21	Neophytos G. Michael, Andrew W. Appel	Machine Instruction Syntax and Semantics in Higher Order Logic.	CADE	2000	DBLP DOI BibTeX RDF
21	Kent D. Wilken, Jack Liu, Mark Heffernan	Optimal instruction scheduling using integer programming.	PLDI	2000	DBLP DOI BibTeX RDF
21	Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis	Counter Based Superscalar Instruction Issuing.	EUROMICRO	2000	DBLP DOI BibTeX RDF
21	Yul Chu, Mabo Robert Ito	A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages.	ICCD	2000	DBLP DOI BibTeX RDF
21	Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto	An instruction-level functionally-based energy estimation model for 32-bits microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
21	Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack	Instruction Set Extensions for MPEG-4 Video.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
21	Chaitali Chakrabarti, Dinesh Gaitonde	Instruction level power model of microcontrollers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki	Instruction buffering to reduce power in processors for signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
21	Michael J. Wirthlin, Brad L. Hutchings	A dynamic instruction set computer.	FCCM	1995	DBLP DOI BibTeX RDF
21	Jack L. Lo, Susan J. Eggers	Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism.	PLDI	1995	DBLP DOI BibTeX RDF
21	Dennis Lee 0001, Jean-Loup Baer, Brad Calder, Dirk Grunwald	Instruction Cache Fetch Policies for Speculative Execution.	ISCA	1995	DBLP DOI BibTeX RDF	C++
21	Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel	Optimization of Instruction Fetch Mechanisms for High Issue Rates.	ISCA	1995	DBLP DOI BibTeX RDF
21	Phillip J. Windley	Specifying Instruction-Set Architectures in HOL: A Primer.	TPHOLs	1994	DBLP DOI BibTeX RDF
21	Uma Mahadevan, Sridhar Ramakrishnan	Instruction Schedulimg over Regions: A Framework for Scheduling Across Basic Blocks.	CC	1994	DBLP DOI BibTeX RDF
21	Robert F. Cmelik, David Keppel	Shade: A Fast Instruction-Set Simulator for Execution Profiling.	SIGMETRICS	1994	DBLP DOI BibTeX RDF	SPARC
21	M. Anton Ertl, Andreas Krall	Optimal Instruction Scheduling using Constraint Logic Programming.	PLILP	1991	DBLP DOI BibTeX RDF
21	Peter Steenkiste	The Impact of Code Density on Instruction Cache Performance.	ISCA	1989	DBLP DOI BibTeX RDF
21	Robert Cohn, Thomas R. Gross, Monica Lam 0001, P. S. Tseng	Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor.	ASPLOS	1989	DBLP DOI BibTeX RDF
21	Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas	Translating systolic arrays into instruction systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE
21	Douglas W. Clark, Henry M. Levy	Measurement and analysis of instruction use in the VAX-11/780.	ISCA	1982	DBLP BibTeX RDF	VAX
21	Richard E. Sweet, James G. Sandman Jr.	Empirical Analysis of the Mesa Instruction Set.	ASPLOS	1982	DBLP DOI BibTeX RDF	MESA
21	John Nations, Stanley Y. W. Su	Some DML Instruction Sequences for Application Program Analysis and Conversion.	SIGMOD Conference	1978	DBLP DOI BibTeX RDF	application program conversion, database conversion, program analysis and synthesis, database management, data manipulation language, schema change
21	Catherine P. Breen	Computer-assisted instruction in industry.	AFIPS National Computer Conference	1974	DBLP DOI BibTeX RDF
21	Michael E. Tarter, T. S. Hauser, Raymond L. Holcomb	Evaluation and development techniques for computer assisted instruction programs.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
21	Jared Freeman, Webb Stacy, Jean MacMillan, Georgiy Levchuk	Capturing and Building Expertise in Virtual Worlds.	HCI (16)	2009	DBLP DOI BibTeX RDF	Adaptive instruction, knowledge engineering, Markov Decision Process, Constraint Logic Programming
21	Hovav Shacham	The geometry of innocent flesh on the bone: return-into-libc without function calls (on the x86).	CCS	2007	DBLP DOI BibTeX RDF	return-into-libc, instruction set, turing completeness
21	Stefan Tillich, Christoph Herbst, Stefan Mangard	Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis.	ACNS	2007	DBLP DOI BibTeX RDF	software countermeasures, implementation security, Advanced Encryption Standard, side-channel attacks, DPA, power analysis, instruction set extensions
21	Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen	A unified processor architecture for RISC & VLIW DSP.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	dual-core processor, register organization, variable-length instruction encoding, digital signal processor
21	Eunhee Choi, Woochun Jun, Suk-Ki Hong, Young-Cheol Bang	An Interaction Model for Web-Based Learning: Cooperative Project.	ICCSA (2)	2004	DBLP DOI BibTeX RDF	Interaction, Web-based Instruction
21	Wlodzimierz M. Zuberek	Modeling and Analysis of Dual Block Multithreading.	FORTE Workshops	2004	DBLP DOI BibTeX RDF	instruction issuing, event–driven simulation, performance analysis, timed Petri nets, pipelined processors, Block multithreading
21	Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton	Continual flow pipelines.	ASPLOS	2004	DBLP DOI BibTeX RDF	CFP, non-blocking, latency tolerance, instruction window
21	Murali Annavaram, Jignesh M. Patel, Edward S. Davidson	Call graph prefetching for database applications.	ACM Trans. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Instruction cache prefetching, database, call graph
21	Mark G. Arnold	A VLIW Architecture for Logarithmic Arithmetic.	DSD	2003	DBLP DOI BibTeX RDF	Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System
21	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
21	Matt Duckham, Lars Kulik	"Simplest" Paths: Automated Route Selection for Navigation.	COSIT	2003	DBLP DOI BibTeX RDF	instruction complexity, Navigation, shortest path, wayfinding, route selection
21	Sang Jeong Lee, Pen-Chung Yew	On Augmenting Trace Cache for High-Bandwidth Value Prediction.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Instruction Level Parallelism, data dependences, Value prediction, trace cache, dynamic classification
21	Sebastian Unger, Frank Mueller 0001	Handling irreducible loops: optimized node splitting versus DJ-graphs.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting
21	Sunghyun Jee, Kannappan Palaniappan	Performance evaluation for a compressed-VLIW processor.	SAC	2002	DBLP DOI BibTeX RDF	CVLIW processor, individual instruction scheduling, VLIW, ILP
21	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	A High-Bandwidth Memory Pipeline for Wide Issue Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality
21	Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen	eXtended Block Cache.	HPCA	2000	DBLP DOI BibTeX RDF	fetch bandwidth, instruction cache, trace cache, Front-end
21	Nicola Zingirian, Massimo Maresca	Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs.	HPCN	2000	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization
21	Toshinori Sato, Itsujiro Arita	Table size reduction for data value predictors by exploiting narrow width values.	ICS	2000	DBLP DOI BibTeX RDF	narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation
21	Kai Wang, Manoj Franklin	Highly Accurate Data Value Prediction Using Hybrid Predictors.	MICRO	1997	DBLP DOI BibTeX RDF	Instruction-level parallel (ILP) processing Speculative execution, Stride-based prediction, Two-level prediction, Data speculation
21	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
21	Keizo Saisho, Takeshi Sano, Keniti Iwata, Akira Fukuda	The Architecture of OCMP and its Evaluation.	ISPAN	1997	DBLP DOI BibTeX RDF	on chip multiprocessor, instruction level dispatch, fork-join type parallel processing, evaluation using simulation, shared cache, private cache
21	Brian A. Malloy, Errol L. Lloyd, Mary Lou Soffa	Scheduling DAG's for Asynchronous Multiprocessor Execution.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	asynchronous multiprocessor execution, sequential instructionstream, execution costs, datadependencies, Data General shared memory multiprocessor system, scheduling, scheduling, parallel programming, parallelism, concurrency, shared memory systems, DAG, communication costs, instruction sets, multiprocessing programs, fine grained parallelism
21	Rahul Razdan, Michael D. Smith 0001	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
20	Aneesh Aggarwal	Complexity Effective Bypass Networks.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF
20	Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Francky Catthoor, Diederik Verkest	Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
20	Martin Thuresson, Magnus Själander, Per Stenström	A Flexible Code Compression Scheme Using Partitioned Look-Up Tables.	HiPEAC	2009	DBLP DOI BibTeX RDF
20	Jack Whitham, Neil C. Audsley	Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures.	IEEE Real-Time and Embedded Technology and Applications Symposium	2008	DBLP DOI BibTeX RDF	wcet, reduction, trace, hard real-time, scratchpads
20	Anish Muttreja, Anand Raghunathan, Srivaths Ravi 0001, Niraj K. Jha	Hybrid Simulation for Energy Estimation of Embedded Software.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
20	Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau	A predictive decode filter cache for reducing power consumption in embedded processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Cache, embedded processors, power optimization
20	Hung-Chuan Lai, Shi-Jinn Horng, Yong-Yuan Chen, Pingzhi Fan, Yi Pan 0001	A New Concurrent Detection of Control Flow Errors Based on DCT Technique.	PRDC	2007	DBLP DOI BibTeX RDF
20	Shuming Chen, Xiao Hu, Biwei Liu, Jihua Chen	An On-Line Control Flow Checking Method for VLIW Processor.	PRDC	2007	DBLP DOI BibTeX RDF
20	Michele Co, Dee A. B. Weikle, Kevin Skadron	Evaluating trace cache energy efficiency.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	fetch engine energy efficiency, Trace cache
20	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley	Dataflow Predication.	MICRO	2006	DBLP DOI BibTeX RDF
20	Sumeet Kumar, Aneesh Aggarwal	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
20	Changpeng Fang, Steve Carr 0001, Soner Önder, Zhenlin Wang	Path-Based Reuse Distance Analysis.	CC	2006	DBLP DOI BibTeX RDF
20	Yasunori Yanai, Minoru Okada	A study on a geometry transformation method for a geometry and scene modeler by a verbal interface.	GRAPHITE	2006	DBLP DOI BibTeX RDF	geometry transformation, modeler, animation, computer graphics, natural language
20	John D. Davis, Cong Fu 0010, James Laudon	The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
20	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
20	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw	A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.	CASES	2005	DBLP DOI BibTeX RDF	sensor network, energy efficiency, microprocessor, memory organization
20	Bita Gorjiara, Daniel D. Gajski	Custom Processor Design Using NISC: A Case-Study on DCT algorithm.	ESTIMedia	2005	DBLP DOI BibTeX RDF
20	Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Jun Xu 0003	An Architectural Framework for Providing Reliability and Security Support.	DSN	2004	DBLP DOI BibTeX RDF