Search results for "lithography"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
12	Mehdi Baradaran Tahoori	Application-independent defect tolerance of reconfigurable nanoarchitectures.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, nanotechnology, Defect tolerance
12	Tohru Furuyama	Deep Sub-100 nm Design Challenges.	DSD	2006	DBLP DOI BibTeX RDF
12	Jean-Pierre Schoellkopf	ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
12	Hai Li 0001, Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
12	Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai	Efficient process-hotspot detection using range pattern matching.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Kenneth L. Shepard, Daniel N. Maynard	Variability and yield improvement: rules, models, and characterization.	ICCAD	2006	DBLP DOI BibTeX RDF
12	Louis Scheffer	An overview of on-chip interconnect variation.	SLIP	2006	DBLP DOI BibTeX RDF	causes of variability, on-chip variation, design rules
12	Shu-Hsing Chung, Chun-Ying Huang, Amy Hsin-I Lee	Using Constraint Satisfaction Approach to Solve the Capacity Allocation Problem for Photolithography Area.	ICCSA (3)	2006	DBLP DOI BibTeX RDF
12	Behzad Esfandyarpour, Ebrahim Asl Soleimani	Fast Response Microgas Sensors Based on Platinum Nanoclusters Sputtered on Nanocrystalline tin Oxide Thin Films.	CCECE	2006	DBLP DOI BibTeX RDF
12	Ajay Khoche, Peter Muhmenthaler	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
12	James W. Tschanz	Session Abstract.	VTS	2006	DBLP DOI BibTeX RDF
12	Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles C. Chiang	An IC manufacturing yield model considering intra-die variations.	DAC	2006	DBLP DOI BibTeX RDF	random variation, systematic variation, CMP, spatial correlation, manufacturing yield
12	Jie Yang 0010, Ethan Cohen, Cyrus Tabery, Norma Rodriguez, Mark Craig	An up-stream design auto-fix flow for manufacturability enhancement.	DAC	2006	DBLP DOI BibTeX RDF	layout, DFM, OPC, design flow
12	Shekhar Borkar	Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Hardware Computer System Organization
12	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng	Compressible area fill synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Rafael Escovar, Salvador Ortiz 0002, Roberto Suaya	An improved long distance treatment for mutual inductance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
12	Puneet Gupta 0001, Andrew B. Kahng, Chul-Hong Park	Detailed placement for improved depth of focus and CD control.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Thomas W. Williams	Design for Testability: The Path to Deep Submicron.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
12	Zhen Ma, David M. Klymyshyn, Sven Achenbach	LIGA Cavity Resonator for K-Band Applications.	ICMENS	2005	DBLP DOI BibTeX RDF
12	Stav Zaitsev, Ronen Almog, Oleg Shtempluck, Eyal Buks	Nonlinear Dynamics in Nanomechanical Oscillators.	ICMENS	2005	DBLP DOI BibTeX RDF
12	Karina Grundke, Astrid Drechsler, Nicole Petong, Cornelia Bellmann, Manfred Stamm, Odo Wunnicke, Jens Reichelt, Iris Mäge, B. Pinter, T. Pearce, M. Voigt	On the Effect of Cationic Surfactants in the Rinse to Reduce Pattern Collapse in High Aspect Ratio Patterning of Photoresists.	ICMENS	2005	DBLP DOI BibTeX RDF
12	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
12	Srinivas Raghvendra, Philippe Hurat	DFM: Linking Design and Manufacturing.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Azzouz Nezar, Michael Creighton	System on Chip: Challenges and Design for Manufacturing, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
12	Guangyi Shi, Qiang Huang 0002, Wen J. Li, Wenqian Huang, Gengchen Shi, Kejie Li	Towards Automated Micromachining of PMMA Micro Channels using CO/Sub 2/ Laser and Sacrificial Mask Process.	ICRA	2004	DBLP DOI BibTeX RDF
12	Sameer Sundresh, WooYoung Kim, Gul Agha	SENS: A Sensor, Environment and Network Simulator.	Annual Simulation Symposium	2004	DBLP DOI BibTeX RDF
12	Tim Fühner, Andreas Erdmann, Richárd Farkas, Bernd Tollkühn, Gabriella Kókai	Genetic Algorithms to Improve Mask and Illumination Geometries in Lithographic Imaging Systems.	EvoWorkshops	2004	DBLP DOI BibTeX RDF
12	Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop	Backend CAD flows for "restrictive design rules".	ICCAD	2004	DBLP DOI BibTeX RDF
12	Nikhil Jayakumar, Sunil P. Khatri	A metal and via maskset programmable VLSI design methodology using PLAs.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester	Investigation of performance metrics for interconnect stack architectures.	SLIP	2004	DBLP DOI BibTeX RDF	back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth
12	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars.	DFT	2004	DBLP DOI BibTeX RDF
12	Cor Claeys	Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects.	VLSI Design	2004	DBLP DOI BibTeX RDF
12	Shekhar Borkar, Tanay Karnik, Vivek De	Design and reliability challenges in nanometer technologies.	DAC	2004	DBLP DOI BibTeX RDF	leakage tolerance, reliability, low-power, variability, soft errors, circuits, SEU, SER, variation tolerance
12	Scott Hamilton	Intel Research Extends Moore's Law.	Computer	2003	DBLP DOI BibTeX RDF
12	Puneet Gupta 0001, Andrew B. Kahng	Manufacturing-Aware Physical Design.	ICCAD	2003	DBLP DOI BibTeX RDF
12	James R. Heath	A systems approach to molecular electronics.	ISLPED	2003	DBLP DOI BibTeX RDF
12	Joohyung Lee 0004, Yogesh B. Gianchandani	A scanning thermal microscopy system with a temperature dithering, servo-controlled interface circuit.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
12	Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis	Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs.	ISPD	2001	DBLP DOI BibTeX RDF
12	Kathleen J. M. Surry, Terry M. Peters	A PVA-C Brain Phantom Derived from a High Quality 3D MR Data Set.	MICCAI	2001	DBLP DOI BibTeX RDF
12	Ashok K. Sinha	Extending Moore's Law through Advances in Semiconductor Manufacturing Equipment.	ISQED	2000	DBLP DOI BibTeX RDF
12	Rui Escadas Martins, Wolfgang Pyka, Rainer Sabelka, Siegfried Selberherr	High-precision interconnect analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
12	Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost	A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 µm silicon bipolar production technology.	ISLPED	1998	DBLP DOI BibTeX RDF
12	Mohammed Hasanuzzaman, Carlos H. Mastrangelo	Process compilation of thin film microdevices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Edward W. Scheckler, Andrew R. Neureuther	Models and algorithms for three-dimensional topography simulation with SAMPLE-3D.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Kenny K. H. Toh, Andrew R. Neureuther, Edward W. Scheckler	Algorithms for simulation of three-dimensional etching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
12	Aleksandra Pavasovic, Andreas G. Andreou, Charles R. Westgate	Characterization of subthreshold MOS mismatch in transistors for VLSI systems.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
12	Richard I. Hartley, Kenneth Welles II, Michael J. Hartman, Paul Delano, Abhijit Chatterjee	Rapid prototyping using high density interconnects.	EURO-DAC	1990	DBLP DOI BibTeX RDF