Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Armin Tajalli, Yusuf Leblebici	A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems.	ESSCIRC	2010	DBLP DOI BibTeX RDF
15	Massimo Alioto	Closed-form analysis of DC noise immunity in subthreshold CMOS logic circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
15	David Sander, Timir Datta, Pamela Abshire	Mismatch compensation of a subthreshold CMOS current normalizer.	ISCAS	2010	DBLP DOI BibTeX RDF
15	David Bol, Cédric Hocquet, Denis Flandre, Jean-Didier Legat	Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Stephen T. Kim, Jaehyouk Choi, Sungho Beck, Taejoong Song, Kyutae Lim, Joy Laskar	Subthreshold current mode matrix determinant computation for analog signal processing.	ISCAS	2010	DBLP DOI BibTeX RDF
15	Bai Na, Xuan Chen, Yang Jun, Longxin Shi	A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme.	SoCC	2010	DBLP DOI BibTeX RDF
15	Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang	Fault models and test methods for subthreshold SRAMs.	ITC	2010	DBLP DOI BibTeX RDF
15	Qi Li, Tony T. Kim	A 9T subthreshold SRAM bitcell with data-independent bitline leakage for improved bitline swing and variation tolerance.	APCCAS	2010	DBLP DOI BibTeX RDF
15	Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu	Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
15	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
15	Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal	Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Anthony R. Kellems, Derrick Roos, Nan Xiao, Steven J. Cox	Low-dimensional, morphologically accurate models of subthreshold membrane potential.	J. Comput. Neurosci.	2009	DBLP DOI BibTeX RDF
15	Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David T. Blaauw	Energy-Efficient Subthreshold Processor Design.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
15	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Interests and Limitations of Technology Scaling for Subthreshold Logic.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
15	Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
15	Hyunju Ham, Toshimasa Matsuoka, Kenji Taniguchi 0001	Application of Noise-Enhanced Detection of Subthreshold Signals for Communication Systems.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
15	Osamu Hoshino	GABA Transporter Preserving Ongoing Spontaneous Neuronal Activity at Firing Subthreshold.	Neural Comput.	2009	DBLP DOI BibTeX RDF
15	Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici	Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
15	Ranjith Kumar, Volkan Kursun	Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
15	Balaji Jayaraman, Navakanta Bhat	Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology.	J. Low Power Electron.	2009	DBLP DOI BibTeX RDF
15	Sik-Lam Siu, Hei Wong, Wing-Shan Tam, Kuniyuki Kakushima, Hiroshi Iwai	Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
15	Te-Kuang Chiang	A new two-dimensional subthreshold behavior model for the short-channel asymmetrical dual-material double-gate (ADMDG) MOSFET's.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
15	S. Baishya	A surface potential and quasi-Fermi potential based drain current model for pocket-implanted MOS transistors in subthreshold regime.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
15	Te-Kuang Chiang	A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET's.	Microelectron. Reliab.	2009	DBLP DOI BibTeX RDF
15	Alexander I. Kostyukov, S. V. Lytvynenko, N. V. Bulgakova, A. V. Gorkovenko	Subthreshold activation of spinal motoneurones in the stretch reflex: experimental data and modeling.	Biol. Cybern.	2009	DBLP DOI BibTeX RDF
15	Hak-Kee Jung	Subthreshold Current Model of FinFET Using Three Dimensional Poisson's Equation.	J. Inform. and Commun. Convergence Engineering	2009	DBLP BibTeX RDF
15	Armin Tajalli, Massimo Alioto, Yusuf Leblebici	Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Leakage Current Reduction Using Subthreshold Source-Coupled Logic.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
15	Francesco Cannillo, Chris Toumazou	Subthreshold Parallel FM-to-Digital Delta- Sigma Converter With Output-Bit-Stream Addition by Interleaving.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
15	Hyungdong Roh, Hyoungjoong Kim, Youngkil Choi, Jeongjin Roh, Yi-Gyeong Kim, Jong-Kee Kwon	A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
15	Francesco Cannillo, Christofer Toumazou, Tor Sverre Lande	Nanopower Subthreshold MCML in Submicrometer CMOS Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
15	Yusuf Leblebici	Subthreshold Circuit Design for Ultra-Low-Power Applications.	PATMOS	2009	DBLP DOI BibTeX RDF
15	Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski	Variation resilient adaptive controller for subthreshold circuits.	DATE	2009	DBLP DOI BibTeX RDF
15	Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya	Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers.	ICECS	2009	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems.	ESSCIRC	2009	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold.	CICC	2009	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.	CICC	2009	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Michael B. Henry, Steven B. Griffin, Leyla Nazhandali	Fast Simulation Framework for Subthreshold Circuits.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Abdul Kadir Kureshi, Naushad Alam, Mohd. Hasan, Tughrul Arslan	Subthreshold Deep Submicron Performance Investigation of CMOS and DTCMOS Biasing Schemes for Reconfigurable Computing.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Ahmad-Hossein Adl, Kamal El-Sankary, Ezz I. El-Masry	Bandgap Reference with Curvature Corrected Compensation using Subthreshold MOSFETs.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Ken Ueno, Tetsuya Asai, Yoshihito Amemiya	Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Xiaofei Chang, Yong Lian 0001	A Quasi-delay-insensitive Dual-rail Adder working in Subthreshold Region.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Sagi Fisher, Adam Teman, Dmitry Vaysman, Alexander Gertsman, Orly Yadid-Pecht, Alexander Fish	Ultra-low Power Subthreshold Flip-flop Design.	ISCAS	2009	DBLP DOI BibTeX RDF
15	Massimo Alioto, Yusuf Leblebici	Analysis and Design of Ultra-low Power Subthreshold MCML Gates.	ISCAS	2009	DBLP DOI BibTeX RDF
15	S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya	100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Bo Zhai, Scott Hanson, David T. Blaauw, Dennis Sylvester	A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
15	Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz	Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
15	Naveen Verma, Anantha P. Chandrakasan	A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
15	Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim	A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
15	Bevin George Perumana, Rajarshi Mukhopadhyay, Sudipto Chakraborty, Chang-Ho Lee, Joy Laskar	A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
15	Corrado Calì, Thomas K. Berger, Michele Pignatelli, Alan Carleton, Henry Markram, Michele Giugliano	Inferring connection proximity in networks of electrically coupled cells by subthreshold frequency response analysis.	J. Comput. Neurosci.	2008	DBLP DOI BibTeX RDF	Gap-junctions, Electrical coupling, ZAP current, Layer VI, Networks, Cortex, Interneurons, Impedance
15	Jorge X. Velasco-Hernández, Brenda Tapia-Santos	Multistability and subthreshold Endemic States in a Model for the Dynamics of Nonsterilizing HIV vaccines.	Int. J. Bifurc. Chaos	2008	DBLP DOI BibTeX RDF
15	Osamu Hoshino	An Ongoing Subthreshold Neuronal State Established Through Dynamic Coassembling of Cortical Cells.	Neural Comput.	2008	DBLP DOI BibTeX RDF
15	Hussam Al-Hertani, Dhamin Al-Khalili, Côme Rozon	UDSM subthreshold leakage model for NMOS transistor stacks.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
15	Guoyi Yu, Xuecheng Zou	A novel current reference based on subthreshold MOSFETs with high PSRR.	Microelectron. J.	2008	DBLP DOI BibTeX RDF
15	Lin-An Yang, Chun-Li Yu, Yue Hao	A new model of subthreshold swing for sub-100 nm MOSFETs.	Microelectron. Reliab.	2008	DBLP DOI BibTeX RDF
15	Apisak Worapishet, John B. Hughes	Performance Enhancement of Switched-Current Technique Using Subthreshold MOS Operation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2008	DBLP DOI BibTeX RDF
15	Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs.	IEICE Electron. Express	2008	DBLP DOI BibTeX RDF
15	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Impact of Technology Scaling on Digital Subthreshold Circuits.	ISVLSI	2008	DBLP DOI BibTeX RDF
15	T. Shihabudheen, V. Suresh Babu, M. R. Baiju	A low power sub 1V 3.5-ppm/°C voltage reference featuring subthreshold MOSFETs.	ICECS	2008	DBLP DOI BibTeX RDF
15	Ling Su, Dongsheng Ma 0001, A. Paul Brokaw	A monolithic step-down SC power converter with frequency-programmable subthreshold z-domain DPWM control for ultra-low power microsystems.	ESSCIRC	2008	DBLP DOI BibTeX RDF
15	Myeong-Eun Hwang, Kaushik Roy 0001	A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology.	CICC	2008	DBLP DOI BibTeX RDF
15	Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy 0001	A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.	ISSCC	2008	DBLP DOI BibTeX RDF
15	Yu-Shiang Lin, Dennis Sylvester	Single stage static level shifter design for subthreshold to I/O voltage conversion.	ISLPED	2008	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
15	Vinay Agarwal, Sameer R. Sonkusale	A PVT independent subthreshold constant-Gm stage for very low frequency applications.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Mu-Tien Chang, Wei Hwang	A fully-differential subthreshold SRAM cell with auto-compensation.	APCCAS	2008	DBLP DOI BibTeX RDF
15	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy 0001	A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM.	IEEE J. Solid State Circuits	2007	DBLP DOI BibTeX RDF
15	Martin Tobias Huber, Hans Albert Braun	Conductance versus current noise in a neuronal model for noisy subthreshold oscillations and related spike generation.	Biosyst.	2007	DBLP DOI BibTeX RDF
15	Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya	An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
15	Abigail Morrison, Sirko Straube, Hans Ekkehard Plesser, Markus Diesmann	Exact Subthreshold Integration with Continuous Spike Times in Discrete-Time Neural Network Simulations.	Neural Comput.	2007	DBLP DOI BibTeX RDF
15	Akhilesh Kumar, Mohab Anis	Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya	A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters.	Neurocomputing	2007	DBLP DOI BibTeX RDF
15	Fabiano Baroni, Pablo Varona	Subthreshold oscillations and neuronal input-output relationships.	Neurocomputing	2007	DBLP DOI BibTeX RDF
15	Julia Berzhanskaya, Anatoli Gorchetchnikov, Steven J. Schiff	Switching between gamma and theta: Dynamic network control using subthreshold electric fields.	Neurocomputing	2007	DBLP DOI BibTeX RDF
15	Sneha Kabra, Harsupreet Kaur, Subhasis Haldar, Mridula Gupta, R. S. Gupta	Two-dimensional subthreshold analysis of sub-micron GaN MESFET.	Microelectron. J.	2007	DBLP DOI BibTeX RDF
15	Ashudeb Dutta, Kaushik Dasgupta, T. K. Bhattacharyya	Compact small signal modeling and PSO-based input matching of a packaged CMOS LNA in subthreshold region.	Microelectron. J.	2007	DBLP DOI BibTeX RDF
15	Walid Elgharbawy, Pradeep Golconda, Abdelhamid G. Moursy, Magdy A. Bayoumi	Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits.	J. Low Power Electron.	2007	DBLP DOI BibTeX RDF
15	Mohammad Mahdi Khafaji, Mahmoud Kamarei, Behjat Forouzandeh	Modified analytical model for subthreshold current in short channel MOSFET's.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
15	Omer Can Akgun, Yusuf Leblebici, Eric A. Vittoz	Current sensing completion detection for subthreshold asynchronous circuits.	ECCTD	2007	DBLP DOI BibTeX RDF
15	Ranjith Kumar, Volkan Kursun	Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits.	ICECS	2007	DBLP DOI BibTeX RDF
15	Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer	Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept.	ESSCIRC	2007	DBLP DOI BibTeX RDF
15	Tony Tae-Hyoung Kim, Jason Liu 0004, Chris H. Kim	An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement.	CICC	2007	DBLP DOI BibTeX RDF
15	Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim	A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme.	ISSCC	2007	DBLP DOI BibTeX RDF
15	Giuseppe de Vita, Giuseppe Iannaccone	A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations.	ISSCC	2007	DBLP DOI BibTeX RDF
15	Chia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, Chung-Chih Hung	A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi 0001, Takayasu Sakurai	Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS).	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Jinhui Chen, Lawrence T. Clark, Tai-Hua Chen	An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
15	Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya	A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator.	Int. J. Bifurc. Chaos	2006	DBLP DOI BibTeX RDF
15	L. Darrell Whitley, Jonathan E. Rowe	Subthreshold-seeking local search.	Theor. Comput. Sci.	2006	DBLP DOI BibTeX RDF
15	Benjamin Lindner, André Longtin	Comment on "Characterization of Subthreshold Voltage Fluctuations in Neuronal Membranes, " by M. Rudolph and A. Destexhe.	Neural Comput.	2006	DBLP DOI BibTeX RDF
15	Zhiyu Liu, Volkan Kursun	Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
15	Tai-Hua Chen, Jinhui Chen, Lawrence T. Clark	Subthreshold to Above Threshold Level Shifter Design.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
15	Po-Hsuan Huang, Hongchin Lin, Yen-Tai Lin	A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
15	Kristel Fobelets, V. Gaspari, P. W. Ding	Subthreshold Operation of a Monolithically Integrated Strained-Si Current Mirror at Low Temperatures.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
15	Michael S. Reid, Edgar A. Brown, Stephen P. DeWeerth	Subthreshold CMOS Array for Generating a Gaussian Distribution of Currents.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
15	Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	Power-supply circuits for ultralow-power subthreshold MOS-LSIs.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
15	Kristian Granhaug, Snorre Aunet	Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology.	DDECS	2006	DBLP DOI BibTeX RDF
15	Ameet Chavan, Gaurav Dukle, Ben Graniello, Eric W. MacDonald	Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures.	ReConFig	2006	DBLP DOI BibTeX RDF