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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1414 occurrences of 781 keywords
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Results
Found 2380 publication records. Showing 2380 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Akihiro Yamamoto |
Inductive Logic Programming: Yet Another Application of Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INAP ![In: Declarative Programming for Knowledge Management, 16th International Conference on Applications of Declarative Programming and Knowledge Management, INAP 2005, Fukuoka, Japan, October 22-24, 2005, Revised Selected Papers, pp. 102-116, 2005, Springer, 3-540-69233-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 87-92, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data compression, chip multiprocessors, optimizing compiler |
22 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4090-4093, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Esther Salamí, Mateo Valero |
A Vector-µSIMD-VLIW Architecture for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 34th International Conference on Parallel Processing (ICPP 2005), 14-17 June 2005, Oslo, Norway, pp. 69-77, 2005, IEEE Computer Society, 0-7695-2380-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Mohamed A. Gomaa, T. N. Vijaykumar |
Opportunistic Transient-Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 172-183, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Stanley Kok, Pedro M. Domingos |
Learning the structure of Markov logic networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICML ![In: Machine Learning, Proceedings of the Twenty-Second International Conference (ICML 2005), Bonn, Germany, August 7-11, 2005, pp. 441-448, 2005, ACM, 1-59593-180-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jérôme Maloberti, Michèle Sebag |
Fast Theta-Subsumption with Constraint Satisfaction Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Learn. ![In: Mach. Learn. 55(2), pp. 137-174, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
k-locality, constraint satisfaction, phase transition, relational learning, meta-learning |
22 | R. S. Milton, V. Uma Maheswari 0002, Arul Siromoney |
Rough Sets and Relational Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. Rough Sets ![In: Transactions on Rough Sets I, pp. 321-337, 2004, Springer, 3-540-22374-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha |
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 39-45, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Jing Li 0002, Tao Jiang 0001 |
An exact solution for finding minimum recombinant haplotype configurations on pedigrees with missing data by integer linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RECOMB ![In: Proceedings of the Eighth Annual International Conference on Computational Molecular Biology, 2004, San Diego, California, USA, March 27-31, 2004, pp. 20-29, 2004, ACM, 1-58113-755-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
missing data imputation, pedigree analysis, integer linear programming, branch-and-bound algorithm, recombination, haplotyping |
22 | Huibin Shi, Chris Bailey 0002 |
Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 112-120, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ruiming Li, Dian Zhou, Donglei Du |
Satisfiability and integer programming as complementary tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 879-882, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman |
Scaling the issue window with look-ahead latency prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004, pp. 217-226, 2004, ACM, 1-58113-839-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LHT, MNM, SILO, instruction sorting, CLP |
22 | Nagarajan Kandasamy, Dávid Hanák, Christopher P. van Buskirk, Himanshu Neema, Gabor Karsai |
Synthesis of robust task schedules for minimum disruption repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC (6) ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: The Hague, Netherlands, 10-13 October 2004, pp. 5056-5061, 2004, IEEE, 0-7803-8566-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ajay Kumar Todimala, Byrav Ramamurthy |
Survivable Virtual Topology Routing under Shared Risk Link Groups in WDM Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: 1st International Conference on Broadband Networks (BROADNETS 2004), 25-29 October 2004, San Jose, CA, USA, pp. 130-139, 2004, IEEE Computer Society, 0-7695-2221-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Arathi Ramani, Igor L. Markov |
Automatically Exploiting Symmetries in Constraint Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCLP ![In: Recent Advances in Constraints, Joint ERCIM/CoLogNet International Workshop on Constraint Solving and Constraint Logic Programming, CSCLP 2004, Lausanne, Switzerland, June 23-25, 2004, Revised Selected and Invited Papers, pp. 98-112, 2004, Springer, 3-540-25176-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | David P. Enot, Ross D. King |
Application of Inductive Logic Programming to Structure-Based Drug Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PKDD ![In: Knowledge Discovery in Databases: PKDD 2003, 7th European Conference on Principles and Practice of Knowledge Discovery in Databases, Cavtat-Dubrovnik, Croatia, September 22-26, 2003, Proceedings, pp. 156-167, 2003, Springer, 3-540-20085-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Lei Chen 0021, Steve Dropsho, David H. Albonesi |
Dynamic Data Dependence Tracking and its Application to Branch Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 65-76, 2003, IEEE Computer Society, 0-7695-1871-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ratthachat Chatpatanasiri, Boonserm Kijsirikul |
Learning First-Order Bayesian Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AI ![In: Advances in Artificial Intelligence, 16th Conference of the Canadian Society for Computational Studies of Intelligence, AI 2003, Halifax, Canada, June 11-13, 2003, Proceedings, pp. 313-328, 2003, Springer, 3-540-40300-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
First-Order Bayesian Networks, Overfitting Problem, Propositionalisation, Feature Extraction, Inductive Logic Programming |
22 | Pen-Chung Yew |
Is There Exploitable Thread-Level Parallelism in General-Purpose Application Programs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 160, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Lal George, Matthias Blume |
Taming the IXP network processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 26-37, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Intel IXA, bank assignment, programming languages, code generation, register allocation, integer linear programming, network processors |
22 | Pradeep Rao, S. K. Nandy 0001, M. N. V. Satya Kiran |
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 166-179, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 113-126, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cholwich Nattee, Sukree Sinthupinyo, Masayuki Numao, Takashi Okada |
Mining Chemical Compound Structure Data Using Inductive Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Active Mining ![In: Active Mining, Second International Workshop, AM 2003, Maebashi, Japan, October 28, 2003, Revised Selected Papers, pp. 92-111, 2003, Springer, 3-540-26157-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Yu Chen 0005, Puneet Gupta 0001, Andrew B. Kahng |
Performance-impact limited area fill synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 22-27, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method |
22 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Optimizing Loop Performance for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 271-280, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Sam Rash, Dan Gusfield |
String barcoding: uncovering optimal virus signatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RECOMB ![In: Proceedings of the Sixth Annual International Conference on Computational Biology, RECOMB 2002, Washington, DC, USA, April 18-21, 2002, pp. 254-261, 2002, ACM, 1-58113-498-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
string barcoding, virus signatures, suffix trees, barcoding, testing set |
22 | Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer |
Affinity-based cluster assignment for unrolled loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 107-116, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment |
22 | Anupam Datta, Sidharth Choudhury, Anupam Basu |
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 705-710, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Optimal test access architectures for system-on-a-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 6(1), pp. 26-49, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Kenji Watanabe, Wanming Chu, Yamin Li |
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 6th Australasian Computer Systems Architecture Conference (ACSAC 2001), 29-30 January 2001, Gold Coast, Queensland, Australia, pp. 35-44, 2001, IEEE Computer Society, 0-7695-0954-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng |
Estimation for maximum instantaneous current through supply lines for CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(1), pp. 61-73, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Kästner |
PROPAN: A Retargetable System for Postpass Optimisations and Analyses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, Vancouver, BC, Canada, June 18, 2000, Proceedings, pp. 63-80, 2000, Springer, 3-540-41781-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh |
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 217, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 127-136, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
test data bandwidth, linearization, test access mechanism (TAM), testing time, Embedded core testing, test bus |
22 | Valentin E. Brimkov, Stefan S. Dantchev |
On the Complexity of Integer Programming in the Blum-Shub-Smale Computational Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFIP TCS ![In: Theoretical Computer Science, Exploring New Frontiers of Theoretical Informatics, International Conference IFIP TCS 2000, Sendai, Japan, August 17-19, 2000, Proceedings, pp. 286-300, 2000, Springer, 3-540-67823-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Integer programming, Knapsack problem, Algebraic complexity, Complexity bounds |
22 | Fumio Mizoguchi |
Anomaly Detection Using Visualization and Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WETICE ![In: 9th IEEE International Workshops on Enabling Technologies: Infrastructure for Collaborative Enterprises (WETICE 2000), 4-16 June 2000, Gaithersburg, MD, USA, pp. 165-170, 2000, IEEE Computer Society, 0-7695-0798-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Design of system-on-a-chip test access architectures under place-and-route and power constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 432-437, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Saso Dzeroski, James Cussens, Suresh Manandhar |
An Introduction to Inductive Logic Programming and Learning Language in Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Learning Language in Logic ![In: Learning Language in Logic, pp. 3-35, 1999, Springer, 3-540-41145-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Hayato Ohwada, Fumio Mizoguchi |
Parallel Execution for Speeding Up Inductive Logic Programming Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discovery Science ![In: Discovery Science, Second International Conference, DS '99, Tokyo, Japan, December, 1999, Proceedings, pp. 277-286, 1999, Springer, 3-540-66713-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Vijay S. Pai, Sarita V. Adve |
Code Transformations to Improve Memory Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 147-155, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu |
The Program Decision Logic Approach to Predicated Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 208-219, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Yi-Min Jiang, Kwang-Ting Cheng |
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 698-702, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Hayato Ohwada, Makiko Daidoji, Shiroaki Shirato, Fumio Mizoguchi |
Learning First-Order Rules from Image Applied to Glaucoma Diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRICAI ![In: PRICAI'98, Topics in Artificial Intelligence, 5th Pacific Rim International Conference on Artificial Intelligence, Singapore, November 22-27, 1998, Proceedings, pp. 494-505, 1998, Springer, 3-540-65271-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Soo-Mook Moon, Kemal Ebcioglu |
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 19(6), pp. 853-898, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar |
22 | Soohong P. Kim, Raymond Hoare, Henry G. Dietz |
VLIW Across Multiple Superscalar Processors on a Single Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 166-, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Wim Van Laer, Luc De Raedt, Saso Dzeroski |
On Multi-class Problems and Discretization in Inductive Logic Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMIS ![In: Foundations of Intelligent Systems, 10th International Symposium, ISMIS '97, Charlotte, North Carolina, USA, October 15-18, 1997, Proceedings, pp. 277-286, 1997, Springer, 3-540-63614-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Classification, Learning, Knowledge Discovery, Discretization, Inductive Logic Programming |
22 | Avaneendra Gupta, John P. Hayes |
Width minimization of two-dimensional CMOS cells using integer programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 660-667, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation |
22 | Arun Balakrishnan, Srimat T. Chakradhar |
Retiming with logic duplication transformation: theory and an application to partial scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 296-302, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function |
22 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 153-162, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
22 | Adrian Slowik, Georg Piepenbrock, Peter Pfahler |
Compiling Nested Loops for Limited Connectivity VLIWs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 5th International Conference, CC'94, Edinburgh, UK, April 7-9, 1994, Proceedings, pp. 143-157, 1994, Springer, 3-540-57877-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Irene Stahl |
Properties of Inductive Logic Programming in Function-Free Horn Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECML ![In: Machine Learning: ECML-94, European Conference on Machine Learning, Catania, Italy, April 6-8, 1994, Proceedings, pp. 423-426, 1994, Springer, 3-540-57868-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Saso Dzeroski, Stephen H. Muggleton, Stuart Russell 0001 |
Learnability of Constrained Logic Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECML ![In: Machine Learning: ECML-93, European Conference on Machine Learning, Vienna, Austria, April 5-7, 1993, Proceedings, pp. 342-347, 1993, Springer, 3-540-56602-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
CSMT: Simultaneous Multithreading for Clustered VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(3), pp. 385-399, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, ILP, simultaneous multithreading, multithreaded processors, VLIW architectures |
17 | Michele Lombardi 0001, Luca Benini, Abhishek Garg, Giovanni De Micheli |
Methods for Designing Reliable Probe Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBE ![In: 10th IEEE International Conference on Bioinformatics and Bioengineering, BIBE 2010, Philadelphia, Pennsylvania, USA, May 31-June 3 2010, pp. 306-307, 2010, IEEE Computer Society, 978-0-7695-4083-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Probe based sensors, Optimization, Microarrays, SAT, ILP |
17 | Tim De Pauw, Stijn Verstichel, Bruno Volckaert, Filip De Turck, Veerle Ongenae |
Resource-Aware Scheduling of Distributed Ontological Reasoning Tasks in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SUTC/UMC ![In: IEEE International Conference on Sensor Networks, Ubiquitous, and Trustworthy Computing, SUTC 2010 and IEEE International Workshop on Ubiquitous and Mobile Computing, UMC 2010, 7-9 June 2010, Newport Beach, California, USA, pp. 131-137, 2010, IEEE Computer Society, 978-0-7695-4049-8. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
simulation, scheduling, ontology, heuristic, reasoning, ILP |
17 | Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski |
Out-of-order issue logic using sorting networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 385-388, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits |
17 | Yixin Shou, Robert A. van Engelen |
Automatic SIMD vectorization of chains of recurrences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 245-255, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chains of recurrences, short vector simd, vectorization, ILP |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Predictable Performance in SMT Processors: Synergy between the OS and SMTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(7), pp. 785-799, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
real time, operating systems, performance predictability, ILP, thread-level parallelism, simultaneous multithreading, Multithreaded processors |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Architectural support for real-time task scheduling in SMT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 166-176, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
scheduling, real time, multithreading, performance predictability, ILP, thread-level parallelism, SMT |
17 | Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev |
The Midlifekicker Microarchitecture Evaluation Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 92-100, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
pipeline, microarchitecture, ILP |
17 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Removing communications in clustered microarchitectures through instruction replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(2), pp. 127-151, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
instruction replication, statically scheduled processors, ILP, modulo-scheduling, Clustered microarchitectures |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Predictable performance in SMT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 433-443, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
real time, operating systems, multithreading, performance predictability, ILP, thread-level parallelism, SMT |
17 | Hillery C. Hunter, Jaime H. Moreno |
A new look at exploiting data parallelism in embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 159-169, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
sub-word parallelism, architecture, embedded, DSP, telecommunications, SIMD, VLIW, processor, ILP, media, DLP, data-level parallelism |
17 | Young Chul Sohn, N. H. Jung, Seung Ryoul Maeng |
Request Reordering to Enhance the Performance of Strict Consistency Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 1, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multiprocessor, ILP, memory consistency model |
17 | Sunghyun Jee, Kannappan Palaniappan |
Dynamically Scheduling VLIW Instructions with Dependency Information. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 15-23, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP |
17 | Sunghyun Jee, Kannappan Palaniappan |
Compiler Processor Tradeoffs for DISVLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: International Symposium on Parallel Architectures, Algorithms and Networks, ISPAN 2002, May 22-24, 2002, Makati City, Metro Manila, Philippines, pp. 199-204, 2002, IEEE Computer Society, 0-7695-1579-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Balanced Scheduling, DISVLIW, Processor architecture, ILP |
17 | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio 0001, Jyotsna Sabarinathan |
Java Runtime Systems: Characterization and Architectural Implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(2), pp. 131-146, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
CPU and cache architectures, Java, performance evaluation, benchmarking, ILP, Java bytecodes |
17 | M. Balakrishnan, Heman Khanna |
Allocation of FIFO structures in RTL data paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(3), pp. 294-310, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
synthesis, RTL, ILP, FIFO, data path |
17 | Kang Su Gatlin, Larry Carter |
Faster FFTs via Architecture-Cognizance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 249-260, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
cache, feedback, memory hierarchy, compiler optimization, associativity, divide-and-conquer, ILP, runtime systems, registers, TLB |
17 | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 294-299, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache |
17 | Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte |
A Fast Interrupt Handling Scheme for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 136-141, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue |
17 | Erik Nystrom, Alexandre E. Eichenberger |
Effective Cluster Assignment for Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 103-114, 1998, ACM/IEEE Computer Society, 0-8186-8609-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ILP, modulo scheduling, cluster architecture, cluster assignment |
17 | Keiko Shimazu, Koichi Furukawa |
Knowledge discovery in database by Progol-design, implementation and its application to expert system building. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1997 ACM symposium on Applied Computing, SAC'97, San Jose, CA, USA, February 28 - March 1, pp. 91-93, 1997, ACM, 0-89791-850-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
KDD, ILP, datamining, ER model, E-mail-classification |
17 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
Early Zero Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 545-, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP |
17 | Soo-Mook Moon, Kemal Ebcioglu |
A study on the number of memory ports in multiple instruction issue machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 49-59, 1993, ACM / IEEE Computer Society, 0-8186-5280-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
memory ports, speculative loads, ILP, static scheduling, memory disambiguation |
16 | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung |
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 133-144, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP) |
16 | C. Li, J. M. van den Akker, Sjaak Brinkkemper, Guido Diepen |
Integrated Requirement Selection and Scheduling for the Release Planning of a Software Product. ![Search on Bibsonomy](Pics/bibsonomy.png) |
REFSQ ![In: Requirements Engineering: Foundation for Software Quality, 13th International Working Conference, REFSQ 2007, Trondheim, Norway, June 11-12, 2007, Proceedings, pp. 93-108, 2007, Springer, 978-3-540-73030-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Requirement Selection, Requirement Scheduling, Simulation, Release Planning, Integer Linear Programming (ILP) |
16 | Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Benjemaa |
An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 379-382, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ILP formulation, Dynamic Scheduling, real time constraints, HW/SW Partitioning |
16 | Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov |
Architecture-aware classical Taylor shift by 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSAC ![In: Symbolic and Algebraic Computation, International Symposium ISSAC 2005, Beijing, China, July 24-27, 2005, Proceedings, pp. 200-207, 2005, ACM, 1-59593-095-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling |
16 | Andrea Lodi 0001, Silvano Martello, Daniele Vigo |
Models and Bounds for Two-Dimensional Level Packing Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 8(3), pp. 363-379, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ILP models, packing, cutting |
16 | Hui Zang, Canhui Ou, Biswanath Mukherjee |
Path-protection routing and wavelength assignment (RWA) in WDM mesh networks under duct-layer constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 11(2), pp. 248-258, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
optical network, protection, wavelength-division multiplexing (WDM), lightpath, wavelength routing, integer linear program (ILP), shared risk link group |
16 | Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente |
CREC: A Novel Reconfigurable Computing Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 175, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP) |
16 | Donald Chai, Andreas Kuehlmann |
A fast pseudo-boolean constraint solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 830-835, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
0-1 ILP, pseudo-boolean, satisfiability |
16 | Aneesh Aggarwal, Manoj Franklin |
Hierarchical Interconnects for On-Chip Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP) |
16 | Waleed Meleis, Alexandre E. Eichenberger, Ivan D. Baev |
Scheduling Superblocks with Bound-Based Branch Trade-Offs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(8), pp. 784-797, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ILP compiler technique, lower bound, scheduling heuristic, Superblock |
16 | Simonjit Dutta, Manoj Franklin |
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(4), pp. 346-359, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP) |
16 | David López 0001, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 22-29, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
ILP limits, multiply-add fused, performance/cost evaluation, software pipelining, VLIW architectures, numerical code |
16 | Kai Wang, Manoj Franklin |
Highly Accurate Data Value Prediction Using Hybrid Predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 281-290, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Instruction-level parallel (ILP) processing Speculative execution, Stride-based prediction, Two-level prediction, Data speculation |
16 | Krishna K. Sundararaman, Manoj Franklin |
Multiscalar Execution along a Single Flow of Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 1997 International Conference on Parallel Processing (ICPP '97), August 11-15, 1997, Bloomington, IL, USA, Proceedings, pp. 106-113, 1997, IEEE Computer Society, 0-8186-8108-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiple control flows, branch prediction, control dependence, instruction-level parallelism (ILP) |
16 | Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau |
Region-based compilation: an introduction and motivation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 158-168, 1995, ACM / IEEE Computer Society, 0-8186-7349-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ILP compilation, code expansion, compilation time complexity, function inlining, region-based compilation |
16 | Nicolas Lachiche, Christel Vrain (eds.) |
Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![CEUR-WS.org The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
16 | Nunung Nurul Qomariyah, Dimitar Kazakov |
Learning from Ordinal Data with Inductive Logic Programming in Description Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 38-50, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Yulong Gu, Paolo Missier |
Adaptive Incremental Learning for Statistical Relational Models Using Gradient-Based Boosting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 22-26, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Jáchym Barvínek, Filip Zelezný |
A First-Order Axiomatization for Transition Learning with Rich Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 1-5, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Ahmed Samet, Thomas Guyet, Benjamin Négrevergne |
Mining Rare Sequential Patterns with ASP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 51-60, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | James Cussens, Alessandra Russo (eds.) |
Proceedings of the 26th International Conference on Inductive Logic Programming (Short papers), London, UK, 2016. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Short Papers) ![CEUR-WS.org The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Tomoyuki Uchida, Satoshi Matsumoto, Takayoshi Shoudai, Yusuke Suzuki, Tetsuhiro Miyahara |
Learning of Primitive Formal Systems Defining Labelled Ordered Tree Languages via Queries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 61-66, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Yin Jun Phua, Tony Ribeiro, Sophie Tourret, Katsumi Inoue |
Learning Logic Program Representation for Delayed Systems With Limited Training Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Late Breaking Papers) ![In: Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017., pp. 27-37, 2017, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
16 | Hendrik Blockeel, Svetlana Valevich |
A Simple Framework for Theta-Subsumption Testing in Prolog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ILP (Short Papers) ![In: Proceedings of the 26th International Conference on Inductive Logic Programming (Short papers), London, UK, 2016., pp. 14-19, 2016, CEUR-WS.org. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
|
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