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Found 1892 publication records. Showing 1892 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Zheng Zhao 0003, Zheng Wang 0036, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan |
Optical computing on silicon-on-insulator-based photonic integrated circuits.  |
ASICON  |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongsheng Wang, Yang Liu, Xunzhi Zhou, Anyi Wang, Bei Cao, Fengchang Lai |
An on-chip signal conditioning delta-sigma ADC for micro-mechanical gyroscope applications. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Binbin Lyu, Wengao Lu, Sijia Yang, Zhongjian Chen, Yacong Zhang |
A self-adaptive digital calibration technique for multi-channel high resolution capacitive SAR ADCs. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zizhao Liu, Tao Pan, Song Jia, Uan Wang |
Design of a novel ternary SRAM sense amplifier using CNFET. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Tongyang Ye, Ligang Hou, Shier Zhang, Jinhui Wang, Xiaohong Peng |
TSV modelling in 3D IC thermoelectric simulation. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yingchieh Ho, Chen Hsu |
Energy-efficient standby current suppression with bootstrapped power-gating technique. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Francis Balestra |
Ultra low power and high performance nanoelectronic devices. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yun Li, Haihua Shen, Ce Li, Feng Zhang 0014 |
An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoxin Dou, Weiwei Pan, Zheng Shi 0002, Yongjun Zheng |
Design and automatic generation of area-efficient ring oscillator based addressable test chips. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yanan Sun 0003, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun |
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuanliang Kang, Pei Yang, Jian Wang 0036, Jinmei Lai |
A deep research on the chip verification platform based on network. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhongxia Shang, Yang Zhao, Yong Lian 0001 |
An APWM controlled LLC resonant converter for a wide input range and different load conditions. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin Yan, Dongsheng Liu, Xuecheng Zou, Bangdi Xu |
A novel positive-feedback read scheme with tail current source of STT-MRAM. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Li 0004, Ziqian Wang, Song Chen, Fujiang Lin |
A low-power digital GFSK receiver with mid-value filtering frequency offset estimator and soft anti-overlap slicer. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Nan Wang, Hengxiao Wang, Yue Jin, Jiongyao Ye |
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujuan Liu, Ning Lyu, ZiSheng Wang |
High-speed FPGA implementation of orthogonal matching pursuit for analog to information converter. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaozhong Ying, Chong Luo, Xiaolei Zhu |
A scalable hardware architecture for multi-layer spiking neural networks. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Zhang, Xu Cheng, Tong Xiaodong, Xianjin Deng |
High voltage charge pump circuit using vertical parallel plate capacitors. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Franco Maloberti |
Keynote speech: Data converters for mobile and autonomous applications. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongsheng Liu, Jiao Wang, Xiangcheng Sun, Jin Yan, Hi Lin |
A low input power charge pump for passive UHF RFID applications. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiaqi Gu, Ruoyao Wang, Jian Wang 0036, Jinmei Lai, Qinghua Duan |
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenfeng Zhao, Ang Li 0006, Yi Wang 0016, Yajun Ha |
Analysis and design of energy-efficient data-dependent SRAM. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Huang, Siyu Ni, Gengsheng Chen |
A layer-based structured design of CNN on FPGA. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yangcan Zhou, Jun Lin 0001, Zhongfeng Wang 0001 |
Energy efficient SVM classifier using approximate computing. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiang Ge, Hengliang Zhu, Fan Yang 0001, Lingli Wang, Xuan Zeng 0001 |
Parallel sparse LU decomposition using FPGA with an efficient cache architecture. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Yi Chang, Quang-Ho Luc, Huy-Binh Do, Yueh-Chin Lin |
Performance improvement of InGaAs FinFET using NH3 treatment. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ye Huang, Xingquan Li, Wenxing Zhu, Jianli Chen |
Cut redistribution and DSA template assignment for unidirectional design. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qichao He, Xiong Zhou, Qiang Li 0021 |
Optimization of the amplifier's input-referred noise for high resolution comparators. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqiang Lv, Yimao Cai, Yuchao Yang, Zhizhen Yu, Yichen Fang, Zongwei Wang, Lindong Wu, Jianfeng Liu, Wanrong Zhang 0002, Ru Huang |
A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiyuan Dai, Hang Hu 0003, Manxin Li, Fan Ye 0001, Junyan Ren |
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang Li, Ruizhi Sun, Ruoxi Wang, Fanjun Zang, Tao Jiang, Yang Li, Xinyang Wang, Yuchun Chang |
A 20MHz CTIA ROIC for InGaAs focal plane array. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Guoqing Sun, Xiaohong Peng, Jun Zhao, Rui Wang, Xiaodan Li |
Design of digital control unit for implantable stimulator chip. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hang Hu 0003, Manxin Li, Zhiyuan Dai, Fan Ye 0001, Junyan Ren |
A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ze He, Xiaowen Chen |
Design and implementation of high-speed configurable ECC co-processor. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hang Hu 0003, Zhiyuan Dai, Manxin Li, Fan Ye 0001, Junyan Ren |
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qing-An Huang, Lei Dong, Lifeng Wang 0004 |
Towards an LC passive wireless sensor platform. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaorong Luo, Weiwei Ge, Bo Zhang 0027 |
Ultralow power loss integratable high-voltage MOSFETs. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ling Chen, Yanan Sun 0003, Weifeng He |
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiulong Hong, Xiubo Liu, Shaodong Wang |
Design of Ka band bandpass filter using silicon micromachined technology. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Weihong Xu, Xiaohu You 0001, Chuan Zhang 0001 |
Using Fermat number transform to accelerate convolutional neural network. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongsheng Wang, Xinzhi Li, Zhixin Zhang, Fengchang Lai |
A low gain error two-stage dB-linear variable gain amplifier in 0.35μm CMOS process. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Ge, Xiaofei Hu, Yajie Qin, Zhiliang Hong |
A single inductor tri-input dual-output buck-boost DC-DC converter with MPPT for multi-source energy harvesting. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen 0001, Feng Wu |
Memristor-based material implication logic design for full adders. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuhiko Endo |
Advanced FinFET technologies for boosting SRAM performance. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiaqi Yang, Jili Zhang, Xuefei Bai, Fujiang Lin |
A noise-shaping SAR ADC with dual error-feedback paths and alternate DACs. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Gong Xiaowu |
Optimization compensation for primary-side-regulated flyback converters in continuous-conduction-mode and discontinuous conduction mode. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hengzhou Yuan, Jianjun Chen, Bin Liang, Yang Guo 0003 |
A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai |
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Dan Liu, Feng Gao, Liguang Hao, Jianxin Liao |
32-Channel ROIC for X-ray imaging system. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Peng Lu, Po-Yen Chien, Xicheng Duan, Jason C. S. Woo |
Deeply scaled VLSI analog transistor design and optimization. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhou 0006, Chun Shi, Zhengjie Deng, Alex Yakovlev |
Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Long Zhao, Bao Li 0003, Yuhua Cheng |
A 6-bit 700-MS/s single-channel SAR ADC with low kickback noise comparator in 40-nm CMOS. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zengxin Liu, Shaowei Zhen, Shuiqing Xi, Xinjiang Gao, Lei Yang, Jiongwei Zheng, He Tang, Yajuan He, Ping Luo, Bo Zhang 0027 |
A digital-assistant time-to-amplitude converter with dynamic range improvement. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuejiao Ma, Yinshui Xia |
Power optimization based on dual-logic using And-Xor-Inverter Graph. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yipeng Yuan, Zhihua Feng, Xuegong Zhou |
An on-line debug method for FPGAs. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Manxin Li, Hang Hu 0003, Zhiyuan Dai, Fan Ye 0001, Junyan Ren |
A 12bit asynchronous SAR-incremental sub-range ADC. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongming Ding, Wei Jin 0004, Guanghui He, Weifeng He |
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiat Seng Yeo, Wen Xian Ng, Mei Yu Soh, Tee Hui Teo |
Micro-LED arrays for display and communication: Device structure and driver architecture. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Yen Chang, Chia-Chi Fan, Chien Liu, Yu-Chien Chiu, Chun-Hu Cheng |
High speed negative capacitance ferroelectric memory. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongsheng Wang, Qiao Ye, Han Zhao, Xiaowei Liu |
A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Rui Zhang 0024, Jinghui Han, Junkang Li, Xiaoyu Tang, Yi Zhao |
NiGe metal source/drain Ge pMOSFETs for future high performance VLSI circuits applications. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Miaomiao Wang 0006, Xin Miao, James H. Stathis, Richard G. Southwick |
Hot carrier reliability in ultra-scaled sige channel p-FinFETs. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chengying Chen, Liming Chen 0007, Xinghua Wang, Feng Zhang 0014 |
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Luo, Adrian Evans, Shi-Jie Wen, Rick Wong, GengSheng Chen |
IZIP: In-place zero overhead interconnect protection via PIP redundancy. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaojing Zha, Yinshui Xia |
Genetic algorithm based on divide-and-conquer strategy for defect-tolerant CMOL mapping. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Chenjie Dong, Han Jin, IkHwan Kim, Chenyu Wang, Yajie Qin, Li-Rong Zheng 0001 |
An area efficient low power ECoG front-end chip for digitalized subdural grid. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Huizi Zhang, Chang Wu, Xiao Hu |
Heterogeneous computing for CNN. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Qiao, Xiao Wang, Yaohong Zhao |
Optimization of operational amplifier settling time by adjusting secondary poles based on gm/ID design. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Kuimin Zhang, Xiaole Cui, Xiaoxin Cui |
A design of high performance full adder with memristors. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Shu Yang, Minghang Liu, Yusong Mu, Yuchun Chang |
A 14-bit 5 MS/s split non-binary SAR ADC. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchen Yao, Zhiqian Zhang, Zhen Yang, Jian Wang 0036, Jinmei Lai |
FPGA-based convolution neural network for traffic sign recognition. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Ru Huang |
How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang |
An all-n-type dynamic adder for ultra-low-leakage IoT devices. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yajie Qin, Zhiliang Hong, Ting-Ao Tang (eds.) |
12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017 |
ASICON |
2017 |
DBLP BibTeX RDF |
|
| 1 | Shijia Zhu, Yu Wang, Fan Ye, Jun Xu |
A clock interpolation structure using DLL for clock distribution in ADC. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fengwei An, Xiangyu Zhang 0002, Lei Chen 0001, Idaku Ishii |
Object-recognition VLSI for pedestrian detection in automotive applications. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jifa Hao |
Hot carrier reliability in LDMOS devices. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Ding, Wenbo Yin |
A fully-pipelined hash table achieving low-latency and high throughput key-value retrieving system. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingqiang Huang, Xiong Xiong, Tiaoyang Li, Yanqing Wu |
High performance transistors based on two dimensional materials. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhigang Li, Jinglei Huang, Qi Xu, Song Chen 0001 |
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yingdan Li, Fei Chen 0006, Zhuoyi Sun, Zhaoyang Weng, Xian Tang, Hanjun Jiang, Zhihua Wang 0001 |
System architecture of a smart binaural hearing aid using a mobile computing platform. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Min Liu, Ying Jian Yan, Wei Li |
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Jingyu Liu, Yongyong Wang, Xunyong Yang, Fashun Yang, Kui Ma |
Analytical model of internal heat transfer of a power chip with through silicon via. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xu Yan, Lu Yang, Hao Zhang 0076, Jili Zhang, Fujiang Lin |
A 1.0-7.0 GHz inductorless RF mixer with multiple feedback and active load in 40-nm CMOS. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fei Gao 0010, Xiaohua Feng, Ruochong Zhang, Siyu Liu 0001, Ran Ding, Yuanjin Zheng |
Dual-pulse nonlinear photoacoustic imaging: Physics, sensing and imaging system design. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fang-Fa Fu, Na Niu, Xiao-He Xian, Jinxiang Wang 0001, Fengchang Lai |
An optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Lou, Wenbin Ye 0001 |
Low complexity and low power multiplierless FIR filter implementation. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Xu, Tianyuan Cheng, Chundong Wu, Nanshu Lu, Zeyu Yang, Yong Lian 0001, Guoxing Wang |
Ultrathin flexible coils for wireless power and data link in biomedical sensors. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Yujie Cai, Xin Li, Jun Han 0003, Xiaoyang Zeng |
A configurable nonlinear operation unit for neural network accelerator. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Haisheng Qian, Guangxi Hu, Laigui Hu, Xing Zhou, Ran Liu 0001, Li-Rong Zheng 0001 |
Analytical models for channel potential and drain current in AlGaN/GaN HEMT devices. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Haruo Kobayashi 0001, Isao Shimizu, Nobukazu Tsukiji, Miho Arai, Kazuyoshi Kubo, Hitoshi Aoki |
Fundamental design tradeoff and performance limitation of electronic circuits based on uncertainty relationships. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Sotoudeh Hamedi-Hagh |
Extraction of circuit transfer functions with SuTra analyses. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Liang 0005, Yechao She, Harish Vangala, Xiaohu You 0001, Chuan Zhang 0001, Emanuele Viterbo |
An efficient successive cancellation polar decoder based on new folding approaches. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Liyi Xiao, Anlong Li, Xuebing Cao, Hongchen Li, Rongsheng Zhang, Jie Li 0030, Tianqi Wang |
A method to estimate cross-section of circuits at RTL levels. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Zhou, Ping Luo, Linyan He, Tiancheng Xiao |
A radiation-hard waffle layout for BCD power MOSFET. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Shen, Huiwen Yuan, Sitong Bu, Mingyue He, Daming Huang |
Low frequency noise characteristics in p-Type MOSFET with multilayer WSe2 channel and Al2O3 back gate dielectric. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Lining Zhang, Chenyue Ma, Mansun Chan |
A universal approach for signal dependent circuit reliability simulation. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongwei Zhu, Qiuliang Li, Hao Sun, Zhipeng Wang, Ran Liu, Yi Liu |
Ultra low loss and high linearity RF switch using 130nm SOI CMOS process. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Daiki Asai, Masao Yanagisawa, Nozomu Togawa |
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
|
| 1 | Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang |
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology. |
ASICON |
2017 |
DBLP DOI BibTeX RDF |
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