Search results for "BIST"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Hung Le, Doyen Sahoo, Nancy F. Chen, Steven C. H. Hoi	BiST: Bi-directional Spatio-Temporal Reasoning for Video-Grounded Dialogues.	EMNLP (1)	2020	DBLP DOI BibTeX RDF
14	Siyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty, Gi-Joon Nam	BISTLock: Efficient IP Piracy Protection using BIST.	ITC	2020	DBLP DOI BibTeX RDF
14	G. Sathesh Kumar, V. Saminadan	Fuzzy logic based Truly Random number generator for high-speed BIST applications.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	K. Jamal, Kamsali Manjunatha Chari, P. Srihari	Test pattern generation using thermometer code counter in TPC technique for BIST implementation.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
14	Senthil Sivakumar, S. P. Joy Vasantha Rani	Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
14	Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada	Logic BIST With Capture-Per-Clock Hybrid Test Points.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
14	Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
14	G. Naveen Balaji, S. Chenthur Pandian	Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
14	Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta 0001, Girish Patankar, Parthajit Bhattacharya	Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach.	ICIT	2019	DBLP DOI BibTeX RDF
14	Hani Malloug, Manuel J. Barragán, Salvador Mir	A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology.	ETS	2019	DBLP DOI BibTeX RDF
14	Zhikuang Cai, Ying Wang, Shihuan Liu, Kai Lv, Zixuan Wang	A Novel BIST Algorithm for Low-Voltage SRAM.	ITC-Asia	2019	DBLP DOI BibTeX RDF
14	Tal Kogan, Yehonatan Abotbol	Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs.	ITC	2019	DBLP DOI BibTeX RDF
14	Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai	Asymmetry dual-LFSR reseeding for low power BIST.	Integr.	2018	DBLP DOI BibTeX RDF
14	J. Praveen, M. N. Shanmukha Swamy	BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture.	J. Circuits Syst. Comput.	2018	DBLP DOI BibTeX RDF
14	Ahcène Bounceur, Samia Djemai, Belkacem Brahmi, Mohand Ouamer Bibi, Reinhardt Euler	A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
14	Hani Malloug, Manuel J. Barragán, Salvador Mir	Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
14	Senthil Sivakumar, S. P. Joy Vasantha Rani	An ADC BIST using on-chip ramp generation and digital ORA.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
14	Abdallatif S. Abu-Issa	Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation.	IEEE Trans. Circuits Syst. II Express Briefs	2018	DBLP DOI BibTeX RDF
14	Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-Um, Masayoshi Tachibana	Phase difference analysis technique for parametric faults BIST in CMOS analog circuits.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
14	Tieqiao Liu, Peng Liu 0045, Yi Liu	An efficient controlled LFSR hybrid BIST scheme.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
14	Abhishek Vashist, Amlan Ganguly, Mark A. Indovina	Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects.	NOCS	2018	DBLP DOI BibTeX RDF
14	D. Sargsyan	Firmware Generation Architecture for Memory BIST.	EWDTS	2018	DBLP DOI BibTeX RDF
14	Kaiyue Zhou, Jia Li 0022, Jianmao Li, Weibing Wang, Dapeng Chen	A Fault-Tolerant BIST Design of MEMS Infrared Thermopile Sensor.	IEEE SENSORS	2018	DBLP DOI BibTeX RDF
14	Sushanti Priya, Suvadip Hazra, Bidesh Chakraborty, Mamata Dalui	A Cellular Automata Based BIST for Detecting NPSFs in High Speed Memories.	ICSCA	2018	DBLP DOI BibTeX RDF
14	Shigeyuki Oshima, Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara	On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST.	ATS	2018	DBLP DOI BibTeX RDF
14	Tsung-Chu Huang, Jeffae Schroff	Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM.	ATS	2018	DBLP DOI BibTeX RDF
14	Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima	Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST.	ATS	2018	DBLP DOI BibTeX RDF
14	Hao Meng, Randall L. Geiger, Degang Chen 0001	A High Constancy Rail-to-rail Level Shift Generator for SEIR-based BIST circuit for ADCs.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Kyungtae Lim, Cheon-Eum Park, Changki Lee, Thierry Poibeau	SEx BiST: A Multi-Source Trainable Parser with Deep Contextualized Lexical Representations.	CoNLL Shared Task (2)	2018	DBLP DOI BibTeX RDF
14	Hans-Mart von Staudt, James Izon, Sule Ozev, Peter Sarson	Special session on BIST/calibration of A/MS devices.	VTS	2018	DBLP DOI BibTeX RDF
14	Abhishek Koneru, Krishnendu Chakrabarty	An inter-layer interconnect BIST solution for monolithic 3D ICs.	VTS	2018	DBLP DOI BibTeX RDF
14	Yingdi Liu, Nilanjan Mukherjee 0001, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer	Deterministic Stellar BIST for In-System Automotive Test.	ITC	2018	DBLP DOI BibTeX RDF
14	Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn	XLBIST: X-Tolerant Logic BIST.	ITC	2018	DBLP DOI BibTeX RDF
14	Aromhack Saysanasongkham, Satoshi Fukumoto, Masayuki Arai	Fault masking issue on a dependable processor using BIST under highly electromagnetic environment.	Int. J. Comput. Sci. Eng.	2017	DBLP DOI BibTeX RDF
14	Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor	Design of Reliable SoCs With BIST Hardware and Machine Learning.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Martin Omaña 0001, Daniele Rossi 0001, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche	Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Babak Aghaei, Ahmad Khademzadeh, Midia Reshadi, Kambiz Badie	A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip.	J. Electron. Test.	2017	DBLP DOI BibTeX RDF
14	Jae Woong Jeong, Vishwanath Natarajan, Shreyas Sen, T. M. Mak, Jennifer Kitchen, Sule Ozev	A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources.	ACM Trans. Design Autom. Electr. Syst.	2017	DBLP DOI BibTeX RDF
14	Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi	BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding.	CoRR	2017	DBLP BibTeX RDF
14	Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy, Zainalabedin Navabi	Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint.	CoRR	2017	DBLP BibTeX RDF
14	Elena Dubrova, Mats Näslund, Gunnar Carlsson, John Fornehed, Ben J. M. Smeets	Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.	J. Signal Process. Syst.	2017	DBLP DOI BibTeX RDF
14	Sahil Shah, Jennifer Hasler	Tuning of Multiple Parameters With a BIST System.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
14	Navya Mohan, Maya Krishnan, Sudhir Kumar Rai, M. MathuMeitha, S. Sivakalyan	Efficient test scheduling for reusable BIST in 3D stacked ICs.	ICACCI	2017	DBLP DOI BibTeX RDF
14	Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir	Mixed-signal BIST computation offloading using IEEE 1687.	ETS	2017	DBLP DOI BibTeX RDF
14	Hani Malloug, Manuel J. Barragan Asian, Salvador Mir, Laurent Basteres, Hervé Le Gall	Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology.	ETS	2017	DBLP DOI BibTeX RDF
14	Yen-Chun Ko, Shih-Hsu Huang	3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints.	ATS	2017	DBLP DOI BibTeX RDF
14	Junshi Wang, Letian Huang, Masoumeh Ebrahimi, Qiang Li 0021, Guangjun Li, Axel Jantsch	Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim	Adapting an industrial memory BIST solution for testing CAMs.	ITC-Asia	2017	DBLP DOI BibTeX RDF
14	Ioannis Voyiatzis, Cleo Sgouropoulou, Giuseppe Airo Farulla	Processor-based Symmetric Transparent BIST.	DTIS	2017	DBLP DOI BibTeX RDF
14	Yatharth Gupta, Sujay Deb, Vikrant Singh, V. N. Srinivasan, Manish Sharma, Sabyasachi Das	Pseudo-BIST: A Novel Technique for SAR-ADC Testing.	VDAT	2017	DBLP DOI BibTeX RDF
14	Martin Omaña 0001, Daniele Rossi 0001, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche	Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
14	Mukesh Agrawal 0001, Krishnendu Chakrabarty, Bill Eklow	A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
14	Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet	A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
14	Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang	Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
14	Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal	A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
14	Christian Fandrych, Elena Frick, Hanna Hedeland, Anna Iliash, Daniel Jettka, Cordula Meißner, Thomas Schmidt 0002, Franziska Wallner, Kathrin Weigert	Wer bist Du, Nutzer?	DHd	2016	DBLP DOI BibTeX RDF
14	Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen	A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.	ATS	2016	DBLP DOI BibTeX RDF
14	Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Arnaud Virazel, Leonardo Bonet Zordan	An effective BIST architecture for power-gating mechanisms in low-power SRAMs.	ISQED	2016	DBLP DOI BibTeX RDF
14	Jae Woong Jeong, Jennifer Kitchen, Sule Ozev	Process independent gain measurement with low overhead via BIST/DUT co-design.	VTS	2016	DBLP DOI BibTeX RDF
14	V. R. Devanathan, Sumant Kale	A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath.	ITC	2016	DBLP DOI BibTeX RDF
14	Rim Ayadi, Intissar Toihria, Mohamed Masmoudi	Fault coverage analysis of selection circuit based BIST for RF CP-PLL.	SSD	2016	DBLP DOI BibTeX RDF
14	Hakan Gunduz, Zehra Cataltepe	Borsa Istanbul (BIST) daily prediction using financial news and balanced feature selection.	Expert Syst. Appl.	2015	DBLP DOI BibTeX RDF
14	Igor Gadelha Pereira, Leonardo Alves Dias, Cleonilson Protásio de Souza	A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
14	Haiying Yuan, Kun Guo, Xun Sun, Jiaping Mei, Hongying Song	A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
14	Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir	A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
14	Elena Dubrova, Mats Näslund, Gunnar Carlsson, John Fornehed, Ben J. M. Smeets	Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST.	CoRR	2015	DBLP BibTeX RDF
14	Nan Li 0018, Gunnar Carlsson, Elena Dubrova, Kim Petersén	Logic BIST: State-of-the-Art and Open Problems.	CoRR	2015	DBLP BibTeX RDF
14	Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi	Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip.	J. Low Power Electron.	2015	DBLP DOI BibTeX RDF
14	Chao Wang 0016, Jun Zhou 0017, Roshan Weerasekera, Bin Zhao, Xin Liu 0015, Philippe Royannez, Minkyu Je	BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
14	Hao Meng, Degang Chen 0001	A simple ramp generator with level spreading for SEIR based ADC BIST circuit.	MWSCAS	2015	DBLP DOI BibTeX RDF
14	Abdallatif S. Abu-Issa, Iyad K. Tumar, Wasel T. Ghanem	SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST.	IDT	2015	DBLP DOI BibTeX RDF
14	Kosuke Sawaki, Satoshi Ohtake	A method of LFSR seed generation for hierarchical BIST.	IDT	2015	DBLP DOI BibTeX RDF
14	L. Martirosyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian	A power based memory BIST grouping methodology.	EWDTS	2015	DBLP DOI BibTeX RDF
14	Abdullah Yassine, Lauren Blair, Wayland Seifert	Employing transistor reliability testing as an FA tool for understanding HTOL product BIST failures.	IRPS	2015	DBLP DOI BibTeX RDF
14	Ioannis Voyiatzis	Symmetric transparent on-line BIST of word-organized memories with binary adders.	ETS	2015	DBLP DOI BibTeX RDF
14	Jae Woong Jeong, Jennifer Kitchen, Sule Ozev	Robust amplitude measurement for RF BIST applications.	ETS	2015	DBLP DOI BibTeX RDF
14	Farshad Firouzi, Fangming Ye, Arunkumar Vijayan, Abhishek Koneru, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori	Re-using BIST for circuit aging monitoring.	ETS	2015	DBLP DOI BibTeX RDF
14	Liang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu	An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.	ASP-DAC	2015	DBLP DOI BibTeX RDF
14	Norman Dodel, Stefan Keil, Andreas Wiemhofer, Malte Kortstock, Philipp Scholz, Uwe Kerst, Roland Thewes	A BIST structure for the evaluation of the MOSFET gate dielectric interface state density in post-processed CMOS chips.	ESSCIRC	2015	DBLP DOI BibTeX RDF
14	Yan Duan, Tao Chen 0006, Zhiqiang Liu, Xu Zhang, Degang Chen 0001	High-constancy offset generator robust to CDAC nonlinearity for SEIR-based ADC BIST.	ISCAS	2015	DBLP DOI BibTeX RDF
14	Puneet Ramesh Savanur, Phaninder Alladi, Spyros Tragoudas	A BIST approach for counterfeit circuit detection based on NBTI degradation.	DFTS	2015	DBLP DOI BibTeX RDF
14	Sule Ozev, Linda Milor	Panel: Analog/RF BIST: Are we there yet?	VTS	2015	DBLP DOI BibTeX RDF
14	Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu, Sule Ozev	Disturbance-free BIST for loop characterization of DC-DC buck converters.	VTS	2015	DBLP DOI BibTeX RDF
14	Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak 0001, Jedrzej Solecki, Jerzy Tyszer	A deterministic BIST scheme based on EDT-compressed test patterns.	ITC	2015	DBLP DOI BibTeX RDF
14	Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang 0001	Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine.	ITC	2015	DBLP DOI BibTeX RDF
14	Ioannis Voyiatzis, Cleo Sgouropoulou, Costas Efstathiou	A concurrent BIST scheme for read only memories.	DTIS	2015	DBLP DOI BibTeX RDF
14	Arpita Dutta, Santanu Chattopadhyay	Particle swarm optimization approach for low temperature BIST.	VDAT	2015	DBLP DOI BibTeX RDF
14	N. Ravi Kiran, G. Harish, A. Karthik 0004, Siva Sankar Yellampalli	Low power and hardware cost STUMPS BIST.	VDAT	2015	DBLP DOI BibTeX RDF
14	Favoureen Swer, V. Pradeep, Siva Sankar Yellampalli	Analog BIST for Capacitive MEMS Sensor using PLL.	WCI	2015	DBLP DOI BibTeX RDF
14	Ioannis Voyiatzis, Costas Efstathiou	Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
14	Shao-Feng Hung, Hao-Chiao Hong	A Fully Integrated BIST $\Delta \Sigma $ ADC Using the In-Phase and Quadrature Waves Fitting Procedure.	IEEE Trans. Instrum. Meas.	2014	DBLP DOI BibTeX RDF
14	Akihiro Tomita, Xiaoqing Wen, Yasuo Sato, Seiji Kajihara, Kohei Miyase, Stefan Holst, Patrick Girard 0001, Mohammad Tehranipoor, Laung-Terng Wang	On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
14	Chih-Sheng Hou, Jin-Fu Li 0001, Ting-Jun Fu	A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2014	DBLP DOI BibTeX RDF
14	Daniel Arbet, Viera Stopjaková, Juraj Brenkus, Gábor Gyepes, Martin Kovác, Libor Majer	BIST architecture for oscillation test of analog ICs and investigation of test hardware influence.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Bruce C. Kim, Saikat Mondal, Friedrich Taenzler, Kenneth Moushegian	A novel BIST technique for LDMOS drivers.	MWSCAS	2014	DBLP DOI BibTeX RDF
14	Ahcène Bounceur, Belkacem Brahmi, Kamel Beznia, Reinhardt Euler	Accurate analog/RF BIST evaluation based on SVM classification of the process parameters.	IDT	2014	DBLP DOI BibTeX RDF
14	Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST.	VLSI-SoC (Selected Papers)	2014	DBLP DOI BibTeX RDF
14	Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue	Memory block based scan-BIST architecture for application-dependent FPGA testing.	FPGA	2014	DBLP DOI BibTeX RDF
14	Andrew B. Kahng, Ilgweon Kang	Co-optimization of memory BIST grouping, test scheduling, and logic placement.	DATE	2014	DBLP DOI BibTeX RDF
14	Emanuel Dogaru, Filipe Vinci dos Santos, William Rebernak	A flexible BIST strategy for SDR transmitters.	DATE	2014	DBLP DOI BibTeX RDF