Search results for "ISMVL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hajime Machida, Michael Pinsker	Polynomials as Generators of Minimal Clones.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu	Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Ricardo Cunha, Henri Boudinov, Luigi Carro	Quaternary Look-Up Tables Using Voltage-Mode CMOS Logic Design.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross	Survey of Stochastic Computation on Factor Graphs.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Janusz A. Brzozowski, Yuli Ye	Simulation of Gate Circuits with Feedback in Multi-Valued Algebras.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Igor N. Aizenberg, Claudio Moraga	The Genetic Code as a Multiple-Valued Function and Its Implementation Using Multilayer Neural Network Based on Multi-Valued Neurons.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Asif Islam Khan, Nadia Nusrat, Samira Manabi Khan, Masud Hasan, Mozammel H. A. Khan	Quantum Realization of Some Ternary Circuits Using Muthukrishnan-Stroud Gates.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Jun Liu 0001, Luis Martínez-López 0001, Yang Xu 0001, Zhirui Lu	Automated Reasoning Algorithm for Linguistic Valued Lukasiewicz Propositional Logic.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Witold Charatonik, Michal Wrona	2-SAT Problems in Some Multi-Valued Logics Based on Finite Lattices.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba	New Fastest Linearly Independent Transforms over GF(3).	ISMVL	2007	DBLP DOI BibTeX RDF
1	Arushi Raghuvanshi, Yale Fan, Michal Woyke, Marek A. Perkowski	Quantum Robots for Teenagers.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Yasushi Yuminaka, Kazuyoshi Yamamura	Equalization Techniques for Multiple-Valued Data Transmission and Their Application.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Milena Stankovic, Suzana Stojkovic, Claudio Moraga	Linearization of Ternary Decision Diagrams by Using the Polynomial Chrestenson Spectrum.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Dietlinde Lau, Masahiro Miyakawa	Classifications and Enumeration of Bases in P_{3}(2).	ISMVL	2007	DBLP DOI BibTeX RDF
1	Tsutomu Sasao	An Application of 16-Valued Logic to Design of Reconfigurable Logic Arrays.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Lucien Haddad, Dietlinde Lau	Characterization of Partial Sheffer Functions in 3-Valued Logic.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Boris A. Romov	Restriction-Closed Hyperclones.	ISMVL	2007	DBLP DOI BibTeX RDF
1	D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton	Variable Reordering and Sifting for QMDD.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto	Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Rusins Freivalds, Liva Garkaje	Boolean Functions of Low Polynomial Degree for Quantum Query Complexity Theory.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Heng Zhang 0006, Mingyi Zhang	Model-Characterizing Formulas and Normal Forms in Godel Logics.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Arnon Avron, Anna Zamansky	Non-deterministic Multi-valued Matrices for First-Order Logics of Formal Inconsistency.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Mark Glusker	The Ternary Calculating Machine of Thomas Fowler.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler	Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Viorica Sofronie-Stokkermans, Carsten Ihlemann	Automated Reasoning in Some Local Extensions of Ordered Structures.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Dan A. Simovici	On the Axiomatization of Generalized Entropic Metrics.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Valeriu Beiu	Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Juan Núñez 0002, José M. Quintana, Maria J. Avedillo	Limits to a Correct Evaluation in RTD-Based Quaternary Inverters.	ISMVL	2007	DBLP DOI BibTeX RDF
1	Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu	The new architecture of radix-4 Chinese abacus adder.	ISMVL	2006	DBLP DOI BibTeX RDF
1		Message from the Program Chair.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Tsutomu Sasao, Jon T. Butler	Implementation of Multiple-Valued CAM Functions by LUT Cascades.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Eun-Ju Choi, Kyoung-Rok Cho, Je-Hoon Lee	New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Jovanka Pantovic, Gradimir Vojvodic	Commuting Hyperoperations.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Elena Dubrova	Random Multiple-Valued Networks: Theory and Applications.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Lun Li, Mitchell A. Thornton, Marek A. Perkowski	A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Tsutomu Sasao	Design Methods for Multiple-Valued Input Address Generators.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi	A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Matthias Baaz, Norbert Preining, Richard Zach	Completeness of a Hypersequent Calculus for Some First-order Godel Logics with Delta.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Claudio Moraga, Radomir S. Stankovic, Jaakko Astola	Properties of matrix-valued spectral coefficients obtained with the Fourier Transform on a non-Abelian group.	ISMVL	2006	DBLP DOI BibTeX RDF
1		Message from the Symposium Chairs.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Masahiro Miyakawa, Ivo G. Rosenberg, Hisayuki Tatsumi	Associativity Test in Hypergroupoids.	ISMVL	2006	DBLP DOI BibTeX RDF	hypergroupoid, associativity
1	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Sergiu Rudeanu, Dan A. Simovici	On the Ranges of Algebraic Functions in Lattices - A Preliminary Report.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Jaakko Astola, Radomir S. Stankovic	Signal Processing Algorithms and Multiple-Valued Logic Design Methods.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Hisayuki Tatsumi, Masahiro Miyakawa, Masao Mukaidono	Upper and Lower Bounds on the Number of Disjunctive Forms.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Haque Mohammad Munirul, Michitaka Kameyama	Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Svetlana N. Yanushkevich, Vlad P. Shmerko, Oleg Boulanov	Embedding and Assembling Techniques for Spatial Computing Structure Design using Decision Trees and Diagrams.	ISMVL	2006	DBLP DOI BibTeX RDF
1		Organizing Committee.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Lucien Haddad, Hajime Machida, Ivo G. Rosenberg	Theoretical Basis of Commutation Theory for Partial Clones.	ISMVL	2006	DBLP DOI BibTeX RDF	partial clone, Clone, centralizer, commutation
1	Michael Katz	Multi-Valued Quantum Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Akira Mochizuki, Takahiro Hanyu	Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Bogdan J. Falkowski, Shixing Yan	Arithmetic-Haar Spectral Transform Decision Diagrams.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Görschwin Fey, Junhao Shi, Rolf Drechsler	Efficiency of Multi-Valued Encoding in SAT-based ATPG.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Daniel Stamate	Assumption based multi-valued semantics for extended logic programs.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu	Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama	Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Hajime Machida, Michael Pinsker	Some Observations on Minimal Clones.	ISMVL	2006	DBLP DOI BibTeX RDF	minimal clone, Clone, Galois field
1	Tsutomu Sasao, Shinobu Nagayama	Representations of Elementary Functions Using Binary Moment Diagrams.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Josep Argelich, Xavier Domingo, Chu Min Li, Felip Manyà, Jordi Planes	Towards Solving Many-Valued MaxSAT.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Bogdan J. Falkowski, Cheng Fu	Generation and Relation of Quaternary and Binary Linearly Independent Transforms.	ISMVL	2006	DBLP DOI BibTeX RDF
1	D. Michael Miller, Mitchell A. Thornton	QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits.	ISMVL	2006	DBLP DOI BibTeX RDF
1	los Roberto Mingoto Jr.	A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Mitsuhiro Tanihata, Takao Waho	A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter.	ISMVL	2006	DBLP DOI BibTeX RDF
1		36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore	ISMVL	2006	DBLP BibTeX RDF
1	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	On Designs of Radix Converters Using Arithmetic Decompositions.	ISMVL	2006	DBLP DOI BibTeX RDF
1		List of Reviewers.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Michel Serfati	A Note on Triangulation of PostAlgebras and "Leibnizian" Lattices.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Keisuke Eguchi, Masaru Chibashi, Takao Waho	A Design of 10-GHz Delta-Sigma Modulator using a 4-Level Differential Resonant-Tunneling Quantizer.	ISMVL	2005	DBLP DOI BibTeX RDF
1		35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada	ISMVL	2005	DBLP BibTeX RDF
1	Phil Serchuk	The Alleged Limitations of Fuzzy Control.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Hideki Fukuda	Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Sebastian Kinder, Görschwin Fey, Rolf Drechsler	Controlling the Memory During Manipulation of Word-Level Decision Diagrams.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Arnon Avron, Anna Zamansky	Quantification in Non-Deterministic Multi-Valued Structures.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Emre Özer 0001, Resit Sendag, David Gregg	Multiple-Valued Caches for Power-Efficient Embedded Systems.	ISMVL	2005	DBLP DOI BibTeX RDF
1		Message from the Program Chair.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Cheng Fu, Bogdan J. Falkowski	Properties and Relations of Quaternary Linearly Independent Helix Transformations.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu	Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Elena N. Zaitseva, Vitaly G. Levashenko, Karol Matiasko, Seppo Puuronen	Dynamic Reliability Indices for k-out-of-n Multi-State System.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Michael P. Frank	Approaching the Physical Limits of Computing.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Nabil Abu-Khader, Pepe Siy	Multiple-Valued Logic Approach for a Systolic^2 AB Circuit in Galois Field.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Sergey Edward Lyshevski	Multi-Valued Nanoelectronics With Fullerenes.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Hajime Machida, Ivo G. Rosenberg	Centralizers of Monoids Containing the Symmetric Group.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Tsutomu Sasao	Radix Converters: Complexity and Implementation by LUT Cascades.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi 0001, Yasuo Takahashi	A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Seiki Akama, Yasunori Nagata	On Prior's Three-Valued Modal Logic Q.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Lucien Haddad, Ivo G. Rosenberg	Partial Clones Determined by Concatenated Relations.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Walter Alexandre Carnielli	Polynomial Ring Calculus for Many-Valued Logics.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Michiro Kondo, Mayuka F. Kawaguchi	Partially Ordered Set with Residuated t-norm.	ISMVL	2005	DBLP DOI BibTeX RDF
1		Two New Awards.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Carlos Ansótegui, Felip Manyà	Mapping Many-Valued CNF Formulas to Boolean CNF Formulas.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Mitchell A. Thornton	The Karhunen-Loève Transform of Discrete MVL Functions.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Ivo G. Rosenberg, Dan A. Simovici	An Abstract Axiomatization of the Notion of Entropy.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Marek A. Perkowski, Jacob D. Biamonte, Martin Lukac	Test Generation and Fault Localization for Quantum Circuits.	ISMVL	2005	DBLP DOI BibTeX RDF
1		Organizing Committee.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Bernd Steinbach, Christian Lang 0001	Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX Gates.	ISMVL	2005	DBLP DOI BibTeX RDF
1	Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama	Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.	ISMVL	2005	DBLP DOI BibTeX RDF

Publications at "ISMVL"( http://dblp.L3S.de/Venues/ISMVL )