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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 79 occurrences of 73 keywords
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Results
Found 1930 publication records. Showing 1930 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano |
A Reconfigurable Array Architecture for NML. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Pankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini |
On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sheng Liu 0001, Haiyan Chen, Jianghua Wan, Yaohua Wang |
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Andrew Whetzel, Mircea R. Stan |
Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shaon Yousuf, Ann Gordon-Ross |
An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sunil Kumar Maddikatla, Srivatsava Jandhyala |
An Accurate All CMOS Temperature Sensor for IoT Applications. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Xinghua Yang, Yue Xing 0001, Fei Qiao, Qi Wei 0001, Huazhong Yang |
Approximate Adder with Hybrid Prediction and Error Compensation Technique. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Renan Netto, Vinicius S. Livramento, Chrystian Guth, Luiz C. V. dos Santos, José Luís Güntzel |
Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yaojie Lu 0002, Seyed Amin Rooholamin, Sotirios G. Ziavras |
Power-Performance Optimization of a Virtualized SMT Vector Processor via Thread Fusion and Lane Configuration. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Weiwei Shi 0001, Zhao Guangdong, Oliver Chiu-sing Choy |
Subthreshold Passive RFID Tag's Baseband Processor Core Design with Custom Modules and Cells. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mohammed Alawad, Mingjie Lin |
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Nan Wu, Zheyu Liu, Fei Qiao, Qi Wei 0001, Xiaojun Guo, Yuan Xie 0001, Huazhong Yang |
A Real-Time and Energy-Efficient Implementation of Difference-of-Gaussian with Flexible Thin-Film Transistors. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Bohua Li, Yukui Pei, Wujie Wen |
Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini |
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Festus Hategekimana, Pierre-Alexis Nardin, Christophe Bobda |
Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yunxi Guo, Akhilesh Tyagi |
Voice Based User-Device Physical Unclonable Functions for Mobile Device Authentication. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha |
Design of Low Power 5-Bit Hybrid Flash ADC. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sunil Kumar Maddikatla, Srivatsava Jandhyala |
An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Aymen Touati, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda |
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Khadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu |
System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat |
Routing-Aware Incremental Timing-Driven Placement. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Grégoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza |
Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin |
Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | |
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016 |
ISVLSI |
2016 |
DBLP BibTeX RDF |
|
1 | Peipei Yin, Chenghua Wang, Weiqiang Liu 0001, Fabrizio Lombardi |
Design and Performance Evaluation of Approximate Floating-Point Multipliers. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Xiaowen Wang, William H. Robinson |
A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits. |
ISVLSI |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Elias Kougianos, Shital Joshi, Saraju P. Mohanty |
Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator Circuit. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh |
A Timing Error Mitigation Technique for High Performance Designs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Arthur Francisco Lorenzon, Anderson Luiz Sartor, Márcia C. Cera, Antonio Carlos Schneider Beck |
Optimized Use of Parallel Programming Interfaces in Multithreaded Embedded Architectures. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ali Dadashi, Yngvar Berg, Omid Mirmotahari |
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yngvar Berg, Omid Mirmotahari |
Flexible Ultra-Low-Voltage CMOS Circuit Design Applicable for Digital and Analog Circuits Operating below 300mV. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | M. Tarek Ibn Ziad, Amr Al-Anwar 0001, Yousra Alkabani, M. Watheq El-Kharashi, Hassan Bedour |
Homomorphic Data Isolation for Hardware Trojan Protection. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Prateek Puri, Michael S. Hsiao |
Fast Stimuli Generation for Design Validation of RTL Circuits Using Binary Particle Swarm Optimization. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Soumya Basu 0002, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza |
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi |
DONUT: A Double Node Upset Tolerant Latch. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Andreas Emeretlis, George Theodoridis, Panayiotis Alefragis, Nikos S. Voros |
Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Antonio Maffucci |
Semi-Classical Modelling of the Electron Transport in Carbon Nanotubes and Graphene Nanoribbons for THz Range Applications. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ciaran MacNamee, Donal Heffernan |
On-Chip Instrumentation for Runtime Verification in Deeply Embedded Processors. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yanghyeok Choi, Seonghyun Park 0002, Jieun Yoo, Seol Namgung, Minkyu Song |
A Full-Swing CMOS Current Steering DAC with an Adaptive Cell and a Quaternary Driver. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ghizlane Mouslih, Aida Todri-Sanial, Pascal Nouet |
On Analysis of On-chip DC-DC Converters for Power Delivery Networks. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yun Cheng, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 |
A Similarity Based Circuit Partitioning and Trimming Method to Defend against Hardware Trojans. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alireza Mahzoon, Bijan Alizadeh |
Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi |
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rajdeep Mukherjee, Daniel Kroening, Tom Melham, Mandayam K. Srivas |
Equivalence Checking Using Trace Partitioning. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Kanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta 0001 |
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar |
A Statistical Approach to Probe Chaos from Noise in Analog and Mixed Signal Designs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jérémy Métairie, Arnaud Tisserand, Emmanuel Casseau |
Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m). |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Cristian Zambelli, Alessandro Grossi, Piero Olivo, Christian Walczyk, Christian Wenger |
RRAM Reliability/Performance Characterization through Array Architectures Investigations. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre |
Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Liuyang Zhang, Wang Kang 0001, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao |
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rajdeep Mukherjee, Daniel Kroening, Tom Melham |
Hardware Verification Using Software Analyzers. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zenghua Cheng, Xuchong Zhang, Huisheng Peng, Baolu Zhai, Hongbin Sun 0001, Nanning Zheng 0001 |
VLSI Design of Edge-Preserving Coding Artifacts Reduction for Display Processing. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Hiller, Ludwig Kurzinger, Georg Sigl, Sven Müelich, Sven Puchinger, Martin Bossert |
Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni |
Logic-in-Memory: A Nano Magnet Logic Implementation. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mayukh Sarkar, Prasun Ghosal |
Implementing Data Structure Using DNA: An Alternative in Post CMOS Computing. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Anush Bekal, Rohit Joshi, Manish Goswami, Babu R. Singh, Ashok Srivatsava |
An Improved Dynamic Latch Based Comparator for 8-Bit Asynchronous SAR ADC. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Clermidy |
An Unbalanced Area Ratio Study for High Performance Monolithic 3D Integrated Circuits. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch |
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Swagata Mandal, Suman Sau, Amlan Chakrabarti, Jogendra Saini, Sushanta Kumar Pal, Subhasish Chattopadhyay |
FPGA Based Novel High Speed DAQ System Design with Error Correction. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tanya Nigam, Andreas Kerber |
Enabling Scaling of Advanced CMOS Technologies: A Reliability Perspective. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Axel Jantsch, Guangjun Li |
Design of Fault-Tolerant and Reliable Networks-on-Chip. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Saggio, Gaoming Du, Xueqian Zhao, Zhonghai Lu |
Validating Delay Bounds in Networks on Chip: Tightness and Pitfalls. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | John Taylor 0002, Benjamin Metcalfe, Chris Clarke, Daniel Chew, Thomas Nielsen 0001, Nick Donaldson |
A Summary of Current and New Methods in Velocity Selective Recording (VSR) of Electroneurogram (ENG). |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Santanu Sarkar 0002, Swapna Banerjee |
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zhou Zhao, Ashok Srivastava, Shaoming Chen, Saraju P. Mohanty |
An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Lafifa Jamal, Hafiz Md. Hasan Babu |
Design and Implementation of a Reversible Central Processing Unit. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif 0003 |
On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Peter Malík |
High Throughput Floating Point Exponential Function Implemented in FPGA. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xueqian Zhao, Zhonghai Lu |
Backlog Bound Analysis for Virtual-Channel Routers. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mozammel H. A. Khan, Himanshu Thapliyal |
Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Gregorek, Alberto García Ortiz |
The DRACON Embedded Many-Core: Hardware-Enhanced Run-Time Management Using a Network of Dedicated Control Nodes. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yasuhiro Sugimoto |
The Solar Cells and the Battery Charger System Using the Fast and Precise Analog Maximum Power Point Tracking Circuits. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sergey A. Maksimenko, Mikhail V. Shuba, P. P. Kuzhir, K. G. Batrakov, G. Y. Slepyan |
Challenges and Perspectives of Nanoelectromagnetics in the THz Range. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Marjan Asadinia, Hamid Sarbazi-Azad |
Using Intra-Line Level Pairing for Graceful Degradation Support in PCMs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Donald M. Chiarulli, Brandon B. Jennings, Yan Fang, Andrew J. Seel, Steven P. Levitan |
A Computational Primitive for Convolution based on Coupled Oscillator Arrays. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev |
A Linear Comparator-Based Fully Digital Delay Element. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard |
Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Imran Ashraf, Koen Bertels, Nader Khammassi, Jean-Christophe Le Lann |
Communication-Aware Parallelization Strategies for High Performance Applications. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yichuan Lu, Kiruba S. Subramani, He Huang, Nathan Kupp, Yiorgos Makris |
Silicon Demonstration of Statistical Post-Production Tuning. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Heike Riel |
The Future of Nanoelectronics: New Materials, Architectures and Devices. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Niels Thole, Görschwin Fey, Alberto García Ortiz |
Conservatively Analyzing Transient Faults. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang 0001, Evangeline F. Y. Young |
An Effective Chemical Mechanical Polishing Filling Approach. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xiaowen Chen, Zhonghai Lu, Yang Li, Axel Jantsch, Xueqian Zhao, Shuming Chen, Yang Guo 0003, Zonglin Liu, Jianzhuang Lu, Jianghua Wan, Shuwei Sun, Shenggang Chen, Hu Chen |
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Fernando Cladera Ojeda, Matthieu Gautier, Olivier Sentieys |
Energy-Aware Computing via Adaptive Precision under Performance Constraints in OFDM Wireless Receivers. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hamzeh Ahangari, Gulay Yalcin, Ozcan Ozturk 0001, Osman S. Unsal, Adrián Cristal |
JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Haji Seyed Javadi, Hamid Reza Mahdiani |
Efficient Utilization of Imprecise Blocks for Hardware Implementation of a Gaussian Filter. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Francesco Orfei, Luca Gammaitoni |
Logic Switches Operating at the Minimum Energy of Computing. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres |
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hassan Ghasemzadeh 0002, Pierre-Emmanuel Gaillardon, J. Zhang, Giovanni De Micheli, Ernesto Sánchez 0001, Matteo Sonza Reorda |
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Thiago Berticelli Lo, Fernanda Lima Kastensmidt, Antonio Carlos Schneider Beck |
Using Configurable Bit-Width Voters to Mask Multiple Errors in Integrated Circuits. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis |
Modulo 2n ± 1 Fused Add-Multiply Units. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Christian Weis, Matthias Jung 0001, Omar Naji, Norbert Wehn, Cristiano Santos, Pascal Vivet, Andreas Hansson 0001 |
Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | |
2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015 |
ISVLSI |
2015 |
DBLP BibTeX RDF |
|
1 | Samaneh Ghandali, Cunxi Yu, Duo Liu, Walter Brown, Maciej J. Ciesielski |
Logic Debugging of Arithmetic Circuits. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Manish Kumar Jaiswal, B. Sharat Chandra Varma 0001, Hayden Kwok-Hay So |
Architecture for Dual-Mode Quadruple Precision Floating Point Adder. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Layer, Kotb Jabeur, Laurent Becker, Bernard Dieny, Stephane Gros, Virgile Javerliac, Pierre Paoli, Fabrice Bernard-Granger |
Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Giuseppe Tagliavini, Davide Rossi, Luca Benini, Andrea Marongiu |
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel |
3D DFT Challenges and Solutions. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
|
1 | David Cavalheiro, Francesc Moll, Stanimir Stoyanov Valtchev |
Novel UHF Passive Rectifier with Tunnel FET Devices. |
ISVLSI |
2015 |
DBLP DOI BibTeX RDF |
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