Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Bhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Steve Clay	Cross-correlation of specification and RTL for soft IP analysis.	DATE	2014	DBLP DOI BibTeX RDF
15	Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle	A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks.	DATE	2014	DBLP DOI BibTeX RDF
15	Daniel Lorenz 0002, Kim Grüttner, Wolfgang Nebel	Data-and State-Dependent Power Characterisation and Simulation of Black-Box RTL IP Components at System Level.	DSD	2014	DBLP DOI BibTeX RDF
15	Sven Alexander Horsinka, Rolf Meyer, Jan Wagner, Rainer Buchty, Mladen Berekovic	On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration.	NoCArc@MICRO	2014	DBLP DOI BibTeX RDF
15	Liang Chen 0014, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Quantitative evaluation of register vulnerabilities in RTL control paths.	ETS	2014	DBLP DOI BibTeX RDF
15	Boonyarit Uengtrakul, Dahmmaet Bunnjaweht	A cost efficient software defined radio receiver for demonstrating concepts in communication and signal processing using Python and RTL-SDR.	DICTAP	2014	DBLP DOI BibTeX RDF
15	Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi 0001	Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs.	ATS	2014	DBLP DOI BibTeX RDF
15	Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria	Probabilistic model checking of single event transient propagation at RTL level.	ICECS	2014	DBLP DOI BibTeX RDF
15	Bastian Haetzer, Martin Radetzki	A comparison of parallel systemc simulation approaches at RTL.	FDL	2014	DBLP DOI BibTeX RDF
15	Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu	Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.	SoCC	2014	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Francesco Stefanni, Tara Ghasempouri, Michele Lora, Giovanni Auditore, Mirella Negro Marcigaglia	On the reuse of RTL assertions in SystemC TLM verification.	LATW	2014	DBLP DOI BibTeX RDF
15	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs.	LATW	2014	DBLP DOI BibTeX RDF
15	Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi	RTL datapath optimization using system-level transformations.	ISQED	2014	DBLP DOI BibTeX RDF
15	Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le	Simulation and satisfiability guided counter-example triage for RTL design debugging.	ISQED	2014	DBLP DOI BibTeX RDF
15	Zissis Poulos, Andreas G. Veneris	Clustering-based failure triage for RTL regression debugging.	ITC	2014	DBLP DOI BibTeX RDF
15	Mehdi Dehbashi, Görschwin Fey	Debug Automation for Synchronization Bugs at RTL.	VLSID	2014	DBLP DOI BibTeX RDF
15	Pierre Vanhauwaert, Paolo Maistri, Régis Leveugle, Athanasios Papadimitriou, David Hély, Vincent Beroulle	On error models for RTL security evaluations.	DTIS	2014	DBLP DOI BibTeX RDF
15	Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David M. Brooks	Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures.	ISCA	2014	DBLP DOI BibTeX RDF
15	Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan	Code Coverage of Assertions Using RTL Source Code Analysis.	DAC	2014	DBLP DOI BibTeX RDF
15	Bijan Alizadeh, Payman Behnam	Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
15	Jayanand Asok Kumar, Shobha Vasudevan	Formal Probabilistic Timing Verification in RTL.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2013	DBLP DOI BibTeX RDF
15	L. A. Zolotorevich	Project verification and construction of superchip tests at the RTL level.	Autom. Remote. Control.	2013	DBLP DOI BibTeX RDF
15	Syed Saif Abrar, Maksim Jenihhin, Jaan Raik	Extensible open-source framework for translating RTL VHDL IP cores to SystemC.	DDECS	2013	DBLP DOI BibTeX RDF
15	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions.	IDT	2013	DBLP DOI BibTeX RDF
15	Otacilio de Araujo Ramos Neto, Antonio Carlos Cavalcanti, Ruy Alberto Pisani Altafim	Comparison between three RTL implementations of the multiplicative inverse calculation of galois field elements based on a standard cells library.	ISVLSI	2013	DBLP DOI BibTeX RDF
15	Michel A. Kinsy, Michael Pellauer, Srinivas Devadas	Heracles: a tool for fast RTL-based design space exploration of multicore processors.	FPGA	2013	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Diego Forrini, Franco Fummi, Matteo Laurenzi, Sara Vinco	RTL IP abstraction into optimized embedded software.	EWDTS	2013	DBLP DOI BibTeX RDF
15	Xinyu He, Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Huazhong Yang	Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications.	DATE	2013	DBLP DOI BibTeX RDF
15	Wei Song 0002, Jim D. Garside	Automatic Controller Detection for Large Scale RTL Designs.	DSD	2013	DBLP DOI BibTeX RDF
15	Khaled Salah 0001	An online RTL-level scan-chain-based methodology for accelerating IP emulation debugging at run-time.	ICEAC	2013	DBLP DOI BibTeX RDF
15	Shuangchen Li, Yongpan Liu, Xiaobo Sharon Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang	Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications.	ASP-DAC	2013	DBLP DOI BibTeX RDF
15	Bin Xue, Prosenjit Chatterjee, Sandeep K. Shukla	Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models.	ASP-DAC	2013	DBLP DOI BibTeX RDF
15	Kelson Gent, Michael S. Hsiao	Functional Test Generation at the RTL Using Swarm Intelligence and Bounded Model Checking.	Asian Test Symposium	2013	DBLP DOI BibTeX RDF
15	Simen Gimle Hansen, Dirk Koch, Jim Tørresen	Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL.	ReCoSoC	2013	DBLP DOI BibTeX RDF
15	Neil Burgess, David Raymond Lutz	Exhaustive testing of Fused Multiply-Add RTL.	ACSSC	2013	DBLP DOI BibTeX RDF
15	Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele	RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study.	IPDPS Workshops	2013	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Sara Vinco	On the automatic generation of GPU-oriented software applications from RTL IPs.	CODES+ISSS	2013	DBLP DOI BibTeX RDF
15	Tobias Strauch	Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs.	PARCO	2013	DBLP DOI BibTeX RDF
15	Andrea Höller, Christopher Preschern, Christian Steger, Christian Kreiner, Armin Krieg, Holger Bock, Josef Haid	Automatized high-level evaluation of security properties for RTL hardware designs.	WESS	2013	DBLP DOI BibTeX RDF
15	Adrian Evans, Dan Alexandrescu, Enrico Costenaro, Liang Chen	Hierarchical RTL-based combinatorial SER estimation.	IOLTS	2013	DBLP DOI BibTeX RDF
15	Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang	Formal equivalence checking between high-level and RTL hardware designs.	LATW	2013	DBLP DOI BibTeX RDF
15	Yi-Hong Lu, Chun-Hong Huang	RTL/FPGA implementation of color correction for digital cameras.	iCAST/UMEDIA	2013	DBLP DOI BibTeX RDF
15	Lingyi Liu, Shobha Vasudevan	Scaling RTL property checking using feasible path analysisand decomposition.	ACM Great Lakes Symposium on VLSI	2013	DBLP DOI BibTeX RDF
15	David W. Palmer, Parbati Kumar Manna	An efficient algorithm for identifying security relevant logic and vulnerabilities in RTL designs.	HOST	2013	DBLP DOI BibTeX RDF
15	Mingsong Chen, Prabhat Mishra 0001	Assertion-Based Functional Consistency Checking between TLM and RTL Models.	VLSI Design	2013	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Hung-Yi Liu, Franco Fummi, Luca P. Carloni	A method to abstract RTL IP blocks into C++ code and enable high-level synthesis.	DAC	2013	DBLP DOI BibTeX RDF
15	Lilia Zaourar, Yann Kieffer, Chouki Aktouf	A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.	VLSI Design	2012	DBLP DOI BibTeX RDF
15	Ki-Hong Park, Won-Ki Ju, Yoon-Ho Kim	Implementation of MAC-based RTL module for Inverse DCT in H.264/AVC.	Multim. Tools Appl.	2012	DBLP DOI BibTeX RDF
15	Yuya Miyaoka, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi	RTL Design of High-Speed Sorted QR Decomposition for MIMO Decoder.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2012	DBLP DOI BibTeX RDF
15	Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar	On the Reuse of TLM Mutation Analysis at RTL.	J. Electron. Test.	2012	DBLP DOI BibTeX RDF
15	Mingsong Chen, Prabhat Mishra 0001, Dhrubajyoti Kalita	Automatic RTL Test Generation from SystemC TLM Specifications.	ACM Trans. Embed. Comput. Syst.	2012	DBLP DOI BibTeX RDF
15	Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu	Improving design verifiability by early RTL coverability analysis.	MEMOCODE	2012	DBLP DOI BibTeX RDF
15	Lukás Charvát, Ales Smrcka, Tomás Vojnar	Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description.	MTV	2012	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Emad Samuel Malki Ebeid, Franco Fummi, Michele Lora	On the Reuse of RTL IPs for SysML Model Generation.	MTV	2012	DBLP DOI BibTeX RDF
15	Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov	A scalable model based RTL framework zamiaCAD for static analysis.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
15	Shilpa Pendyala, Srinivas Katkoori	Interval arithmetic based input vector control for RTL subthreshold leakage minimization.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
15	Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer	ArchFP: Rapid prototyping of pre-RTL floorplans.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
15	Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad	Efficient in-system RTL verification and debugging using FPGAs (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
15	Nainala Vyagrheswarudu, Subrangshu Das, Abhishek Ranjan	PowerAdviser: An RTL power platform for interactive sequential optimizations.	DATE	2012	DBLP DOI BibTeX RDF
15	Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov	RTL analysis and modifications for improving at-speed test.	DATE	2012	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs.	DATE	2012	DBLP DOI BibTeX RDF
15	Mahesh Prabhu, Jacob A. Abraham	Functional test generation for hard to detect stuck-at faults using RTL model checking.	ETS	2012	DBLP DOI BibTeX RDF
15	Robert B. Reese, Scott C. Smith, Mitchell A. Thornton	Uncle - An RTL Approach to Asynchronous Design.	ASYNC	2012	DBLP DOI BibTeX RDF
15	Bijan Alizadeh, Masahiro Fujita	A functional test generation technique for RTL datapaths.	HLDVT	2012	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Andrea Acquaviva	Energy aware TLM platform simulation via RTL abstraction.	HLDVT	2012	DBLP DOI BibTeX RDF
15	Gregor Nitsche, Georg Glaeser, Dirk Nuernbergk, Eckhard Hennig	Hardware/Software Co-design of a Smart Sensor Interface Using a Fast but Accurate Close-to-RTL Instruction Set Interpreter.	MBMV	2012	DBLP BibTeX RDF
15	Vahid Saljooghi, Alen Bardizbanyan, Magnus Själander, Per Larsson-Edefors	Configurable RTL model for level-1 caches.	NORCHIP	2012	DBLP DOI BibTeX RDF
15	Ghaith Tarawneh, Alex Yakovlev	An RTL method for hiding clock domain crossing latency.	ICECS	2012	DBLP DOI BibTeX RDF
15	Daniel Lorenz 0002, Kim Grüttner, Nicola Bombieri, Valerio Guarnieri, Sara Bocchio	From RTL IP to functional system-level models with extra-functional properties.	CODES+ISSS	2012	DBLP DOI BibTeX RDF
15	Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung	Rapid RTL-based signal ranking for FPGA prototyping.	FPT	2012	DBLP DOI BibTeX RDF
15	Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang	QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification.	TACAS	2012	DBLP DOI BibTeX RDF
15	Jamil Mazzawi, Ziyad Hanna	Formal Analysis of Security Data Paths in RTL Design.	Haifa Verification Conference	2012	DBLP DOI BibTeX RDF
15	Andrea Acquaviva, Nicola Bombieri, Franco Fummi, Sara Vinco	On the automatic synthesis of parallel SW from RTL models of hardware IPs.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
15	Sangchul Kim, Hyunjin Kim, Taeil Chung, Jin-Gyeong Kim	Design of H.264 video encoder with C to RTL design tool.	ISOCC	2012	DBLP DOI BibTeX RDF
15	Min Li 0013, Kelson Gent, Michael S. Hsiao	Design validation of RTL circuits using evolutionary swarm intelligence.	ITC	2012	DBLP DOI BibTeX RDF
15	Somnath Banerjee 0003, Tushar Gupta	Efficient Online RTL Debugging Methodology for Logic Emulation Systems.	VLSI Design	2012	DBLP DOI BibTeX RDF
15	Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz	System verification of concurrent RTL modules by compositional path predicate abstraction.	DAC	2012	DBLP DOI BibTeX RDF
15	Jayanand Asok Kumar, Kenneth M. Butler, Heesoo Kim, Shobha Vasudevan	Early prediction of NBTI effects using RTL source code analysis.	DAC	2012	DBLP DOI BibTeX RDF
15	Cristiano Scavongelli, Marco Giammarini, Massimo Conti, Simone Orcioni	Computational cost estimation of a RTL JPEG architecture with Powersim.	WISES	2012	DBLP BibTeX RDF
15	Jayanand Asok Kumar	Statistical guarantees of performance for RTL designs		2012	RDF
15	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan: A DFT Method for Functional Scan at RTL.	IEICE Trans. Inf. Syst.	2011	DBLP DOI BibTeX RDF
15	Benjamin Carrión Schäfer, Kazutoshi Wakabayashi	Precision tunable RTL macro-modelling cycle-accurate power estimation.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
15	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
15	Lirida A. B. Naviner, Jean-François Naviner, G. G. dos Santos Jr., Elaine Crespo Marques, Nilson M. Paiva Jr.	FIFA: A fault-injection-fault-analysis-based tool for reliability assessment at RTL level.	Microelectron. Reliab.	2011	DBLP DOI BibTeX RDF
15	Tatsuya Koyagi, Sohaib Majzoub, Masahiro Fukui, Resve A. Saleh	RTL delay macro-modeling with Vt and Vdd variability.	IDT	2011	DBLP DOI BibTeX RDF
15	Lingyi Liu, Shobha Vasudevan	Efficient validation input generation in RTL by hybridized source code analysis.	DATE	2011	DBLP DOI BibTeX RDF
15	Manish Baphna, Anchal Jain, Ashish Mathur	A Method to Reuse RTL Verification Tests to Validate Cycle Accurate Model.	ISED	2011	DBLP DOI BibTeX RDF
15	Michal Rumplík, Josef Strnadel	On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits.	DSD	2011	DBLP DOI BibTeX RDF
15	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	ETS	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
15	Nobuyuki Nishiguchi	An RTL-to-GDS2 design methodology for advanced system LSI.	ASP-DAC	2011	DBLP DOI BibTeX RDF
15	Andreas G. Veneris, Brian Keng, Sean Safarpour	From RTL to silicon: The case for automated debug.	ASP-DAC	2011	DBLP DOI BibTeX RDF
15	Lilia Zaourar, Yann Kieffer, Chouki Aktouf	An Innovative Methodology for Scan Chain Insertion and Analysis at RTL.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
15	Leonard J. Mselle	Using formal logic to define the grammar for memory transfer language (MTL) on the mould of register transfer language (RTL) and high level languages.	PPIG	2011	DBLP BibTeX RDF
15	Paul Schumacher, Pradip Jha, Sudha Kuntur, Tim Burke, Alan Frost	Fast RTL Power Estimation for FPGA Designs.	FPL	2011	DBLP DOI BibTeX RDF
15	Jianchao Lu, Baris Taskin	From RTL to GDSII: An ASIC design course development using Synopsys® University Program.	MSE	2011	DBLP DOI BibTeX RDF
15	Mark C. Johnson	Interactive application for learning RTL code structures.	MSE	2011	DBLP DOI BibTeX RDF
15	Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour	Debugging with dominance: On-the-fly RTL debug solution implications.	ICCAD	2011	DBLP DOI BibTeX RDF
15	Hao Qian, Yangdong Deng	Accelerating RTL simulation with GPUs.	ICCAD	2011	DBLP DOI BibTeX RDF
15	Lingkan Gong, Oliver Diessel	ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration.	FPT	2011	DBLP DOI BibTeX RDF
15	Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee	Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations.	DFT	2011	DBLP DOI BibTeX RDF