Search results for "SBCCI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt	Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic.	SBCCI	2005	DBLP DOI BibTeX RDF	SEU and soft error detection, SET, BICS
1	Xiangrong Zhou, Peter Petrov	Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Armando G. da Silva Jr.	IC design requirements for automotive applications.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Abdelkarim Mercha	Technology and architecture for deep submicron RF CMOS technology.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia	Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing.	SBCCI	2005	DBLP DOI BibTeX RDF	resistor biasing, low power, wireless, CMOS, low voltage, voltage controlled oscillator (VCO), phase noise
1	Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini	Fault tolerance overhead in network-on-chip flow control schemes.	SBCCI	2005	DBLP DOI BibTeX RDF	fault tolerance, network on chip, error correction, flow control
1	Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.	SBCCI	2005	DBLP DOI BibTeX RDF	burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent
1	C. P. Moreira, Alexandre A. Shirakawa, Eric Kerherve, Jean-Marie Pham, Pierre Jarry, Didier Belot, Pascal Ancey	Design of a fully-integrated BiCMOS/FBAR reconfigurable RF receiver front-end.	SBCCI	2005	DBLP DOI BibTeX RDF	BAW technology, FBAR integrated filters, RF receiver front-end, direct conversion receiver architecture, dual-standard operation, low noise amplifier
1	Jung Hyun Choi	Minimization of parasitic effects on the design of an accurate 2-MHz RC oscillator for low voltage and low power applications.	SBCCI	2005	DBLP DOI BibTeX RDF	2MHz RC circuit, parasitic effects, design, minimization, oscillator
1	John Sanguinetti	The process of higher level design.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Paul L. Jespers	A design methodology for analogue CMOS circuits.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Aline Mello 0001, Leonel Tedesco, Ney Calazans, Fernando Moraes 0001	Virtual channels in networks on chip: implementation and evaluation on hermes NoC.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, network-on-chip, virtual channel
1	Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin	Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.	SBCCI	2005	DBLP DOI BibTeX RDF	mapping and optimization algorithms, systems-on-chip, networks-on-chip
1	Eduardo Tavares, Paulo Romero Martins Maciel, Arthur Bessa, Raimundo S. Barreto, Leonardo Barros, Meuse N. Oliveira Jr., Ricardo Massa Ferreira Lima	A time petri net based approach for embedded hard real-time software synthesis with multiple operational modes.	SBCCI	2005	DBLP DOI BibTeX RDF	embedded hard real-time systems, hardware/software codesign methodologies, software synthesis
1	Eduardo Afonso Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Braulio Wanderley Netto	Design of a decompressor engine on a SPARC processor.	SBCCI	2005	DBLP DOI BibTeX RDF	performance, code compression
1	David Varghese, J. Neil Ross	A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design.	SBCCI	2005	DBLP DOI BibTeX RDF	HFPAA, differential difference amplifier, interconnectivity analysis, non-permuting grouped combinations listing algorithm, rents rule, second generation current-conveyor, hierarchical architecture, FPAA
1	Ghiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione	TheoSim: combining symbolic simulation and theorem proving for hardware verification.	SBCCI	2004	DBLP DOI BibTeX RDF	theorem proving, symbolic simulation, hardware verification
1	Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije	A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology.	SBCCI	2004	DBLP DOI BibTeX RDF	TSPC, high speed digital circuit, low power, prescaler
1	Edna Natividade da Silva Barros, Flávio Rech Wagner, Luigi Carro, Franz-Josef Rammig (eds.)	Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004	SBCCI	2004	DBLP DOI BibTeX RDF
1	Luiz Alberto Pasini Melek, Márcio C. Schneider, Carlos Galup-Montoro	Body-bias compensation technique for SubThreshold CMOS static logic gates.	SBCCI	2004	DBLP DOI BibTeX RDF	body-bias compensation, static logic, low-power, CMOS, logic circuits, subthreshold
1	Hans-Dieter Wohlmuth, Daniel Kehrer	A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOS.	SBCCI	2004	DBLP DOI BibTeX RDF	flip-flop, pseudo random, CML
1	Mike Hutton	Architecture and CAD for FPGAs.	SBCCI	2004	DBLP DOI BibTeX RDF
1	C. P. Moreira, Eric Kerherve, Pierre Jarry, Alexandre A. Shirakawa, Didier Belot	Dual-mode RF receiver front-end using a 0.25-µm 60-GHz fTSiGe: C BiCMOS7RF technology.	SBCCI	2004	DBLP DOI BibTeX RDF	RF receiver front-end, direct conversion receiver architecture, high performance integration technology, multi-mode operation, noise/input impedance optimisation methodology, low noise amplifier
1	Antonio Carlos Schneider Beck, Luigi Carro	A VLIW low power Java processor for embedded applications.	SBCCI	2004	DBLP DOI BibTeX RDF	Java, power consumption, VLIW
1	Edgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider	An ultra-low-power self-biased current reference.	SBCCI	2004	DBLP DOI BibTeX RDF	inversion level, self-cascode MOSFET, design methodology, low-voltage, ultra-low-power, current reference
1	Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski	Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.	SBCCI	2004	DBLP DOI BibTeX RDF	system-on-chip, BIST, power aware, mixed-signal test
1	Enrico Macii	Leakage power optimization in standard-cell designs.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Alexander Thomas, Thomas Zander, Jürgen Becker 0001	Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures.	SBCCI	2004	DBLP DOI BibTeX RDF	HoneyComb architecture, adaptive I/O interfaces, data stream handling, multi-grained reconfigurable hardware architecture
1	Márcio Oyamada, Felipe Zschornack, Flávio Rech Wagner	Accurate software performance estimation using domain classification and neural networks.	SBCCI	2004	DBLP DOI BibTeX RDF	neural networks, embedded software, performance estimation
1	David Camarero, Jean-François Naviner, Patrick Loumeau	Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters.	SBCCI	2004	DBLP DOI BibTeX RDF	digital calibration, parallel ADC, sample-time errors, time-interleaved, adaptive filters, clock skew
1	João M. S. Silva, L. Miguel Silveira	Issues in parallelizing multigrid-based substrate model extraction and analysis.	SBCCI	2004	DBLP DOI BibTeX RDF	grid computing, multigrid, substrate coupling
1	José Luis Huertas	Test and design-for-test of mixed-signal integrated circuits.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Vinícius P. Correia, André Inácio Reis	Advanced technology mapping for standard-cell generators.	SBCCI	2004	DBLP DOI BibTeX RDF	cell library, library-free, logic synthesis, technology mapping, complex gates
1	César Augusto Dueñas M.	Verification and test challenges in SoC designs.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Accurate capture of timing parameters in inductively-coupled on-chip interconnects.	SBCCI	2004	DBLP DOI BibTeX RDF	signal delay, crosstalk, on-chip interconnects, interconnect models, inductive coupling
1	Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa	A programmable cellular neural network circuit.	SBCCI	2004	DBLP DOI BibTeX RDF	VLSI, cellular neural networks, microelectronics
1	Chandu Visweswariah	Statistical analysis and design: from picoseconds to probabilities.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Michael J. Thul, Norbert Wehn	FPGA implementation of parallel turbo-decoders.	SBCCI	2004	DBLP DOI BibTeX RDF	wireless, parallel architecture, FPGA implementation, turbo-decoder
1	Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro 0001, Sergio Bampi	An improved synthesis method for low power hardwired FIR filters.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA synthesis, parallel FIR filter, power-of-two, common subexpression elimination
1	Marcel Jacomet, Josef Goette, Venanz Zbinden, Christian Narvaez	On the dynamic behavior of a novel digital-only sigma--delta A/D converter.	SBCCI	2004	DBLP DOI BibTeX RDF	?? modulator, FPGA, A/D converter
1	Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich	Task scheduling for heterogeneous reconfigurable computers.	SBCCI	2004	DBLP DOI BibTeX RDF	hardware preemption, scheduling, FPGA, placement, reconfigurable computing, partial reconfiguration
1	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Low-power dual Vth pseudo dual Vdd domino circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
1	Mike Hutton	Advances and trends in FPGA design.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Raimundo S. Barreto, Marília Neves, Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Eduardo Tavares, Ricardo Massa Ferreira Lima	A formal software synthesis approach for embedded hard real-time systems.	SBCCI	2004	DBLP DOI BibTeX RDF	embedded hard real-time systems, hardware/software codesign methodologies, software synthesis
1	Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas	Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic.	SBCCI	2004	DBLP DOI BibTeX RDF	ECDL, CMOS, adder, digital circuits
1	Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro	Characterization of MOS transistor current mismatch.	SBCCI	2004	DBLP DOI BibTeX RDF	matching, analog design, MOSFET, mismatch, compact models
1	Christian Meise, Christoph Grimm 0001	A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping.	SBCCI	2004	DBLP DOI BibTeX RDF	SystemC-AMS, behavioral model, virtual prototype
1	Alfredo Arnaud, Carlos Galup-Montoro	A fully integrated physical activity sensing circuit for implantable pacemakers.	SBCCI	2004	DBLP DOI BibTeX RDF	low-power, CMOS, analog design, biomedical
1	Rodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo	When reconfigurable architecture meets network-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	multiprocessor, system on chip, network on chip, reconfigurable architecture
1	Fernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes	Exception handling in microprocessors using assertion libraries.	SBCCI	2004	DBLP DOI BibTeX RDF	exceptions handling, assertions
1	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
1	Leandro Buss Becker, Marco A. Wehrmeister, Carlos Eduardo Pereira	Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applications.	SBCCI	2004	DBLP DOI BibTeX RDF	performance, power consumption, scheduling algorithms
1	Timo Vogt, Norbert Wehn, Philippe Alves	A multi-standard channel-decoder for base-station applications.	SBCCI	2004	DBLP DOI BibTeX RDF	CDMA2k, convolutional decoder, hardware sharing, wireless, configurable, MAP, W-CDMA
1	Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho	ATPG for fault diagnosis on analog electrical networks using evolutionary techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	genetic algorithms, automatic test pattern generation, fault models, analog and mixed-signal test
1	José Vieira do Vale Neto	Design sequence for a LC-tank voltage controlled oscillator in CMOS for RF.	SBCCI	2004	DBLP DOI BibTeX RDF	LC-tank, ASIC, CMOS, VCO, radio frequency
1	Frank Sill, Frank Grassert, Dirk Timmermann	Low power gate-level design with mixed-Vth (MVT) techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
1	Mircea R. Stan, Fatih Hamzaoglu, David Garrett	Non-Manhattan maze routing.	SBCCI	2004	DBLP DOI BibTeX RDF	Manhattan routing, multi-layer routing, non-Manhattan routing, global routing, local routing
1	Andre Vilas Boas, Jefferson B. D. Soldera, Alfredo Olmos	A 1.8V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability.	SBCCI	2004	DBLP DOI BibTeX RDF	bandgap, low-voltage detector, relaxation, oscillator, trimming
1	Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner	A switch architecture and signal synchronization for GALS system-on-chips.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC switch, clock stretching, synchronization, GALS
1	Enrico Macii	RTL power estimation and optimization.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs.	SBCCI	2004	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
1	Karina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta	An automatic testbench generation tool for a SystemC functional verification methodology.	SBCCI	2004	DBLP DOI BibTeX RDF	Brazilip, SCV, VeriSC, tool, SystemC
1	Armando Carbonari	Avionic systems overview.	SBCCI	2004	DBLP DOI BibTeX RDF
1	Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia	A 0.8 mum CMOS switched-capacitor video filter.	SBCCI	2004	DBLP DOI BibTeX RDF	allpass circuits, testing, filters, analog integrated circuits, switched-capacitor filters
1	Virgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho	Design of RF CMOS low noise amplifiers using a current based MOSFET model.	SBCCI	2004	DBLP DOI BibTeX RDF	noise, CMOS, RF, LNA
1	Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho	A partial reconfigurable architecture for controllers based on Petri nets.	SBCCI	2004	DBLP DOI BibTeX RDF	virtual hardware, FPGAs, Petri nets, partial reconfiguration, programmable logic controller (PLC)
1	Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein	Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic.	SBCCI	2004	DBLP DOI BibTeX RDF	configware, morphware, reconfigurable systolic arrays, term rewriting systems (TRS), dynamic programming, rewriting-logic
1	César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin	ParIS: a parameterizable interconnect switch for networks-on-chip.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA, systems-on-chip, networks-on-chip
1	Fulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante	A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.	SBCCI	2004	DBLP DOI BibTeX RDF	fault injection, automotive, CAN bus
1	Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes 0001	PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.	SBCCI	2004	DBLP DOI BibTeX RDF	dynamically and partially reconfigurable systems, partial bitstream generation, reconfiguration control, run-time reconfiguration
1	Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001	Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.	SBCCI	2004	DBLP DOI BibTeX RDF	virtex, dynamic partial reconfiguration
1	Raul Camposano	Will the ASIC survive?	SBCCI	2004	DBLP DOI BibTeX RDF
1	Klaus Danne	Distributed arithmetic FPGA design with online scalable size and performance.	SBCCI	2004	DBLP DOI BibTeX RDF	FPGA, reconfiguration, multitasking, arithmetic
1	Eric E. Fabris, Luigi Carro, Sergio Bampi	Modeling and designing high performance analog reconfigurable circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	analog programmability, band-pass sigma-delta modulator, analog design, FPAA
1	Abel Guilhermino Silva-Filho, Alejandro César Frery, Cristiano C. de Araújo, Haglay Alice, Jorge Cerqueira, Juliana A. Loureiro, Manoel Eusébio de Lima, Maria das Gracas S. Oliveira, Michelle Matos Horta	Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm.	SBCCI	2003	DBLP DOI BibTeX RDF
1	César Albenes Zeferino, Altamiro Amadeu Susin	SoCIN: A Parametric and Scalable Network-on-Chip.	SBCCI	2003	DBLP DOI BibTeX RDF	FPGA, Embedded Systems, Systems-on-Chip
1	Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi	Novel Design Methodology for High-Performance XOR-XNOR Circuit Design.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Achim Rettberg, Florian Dittmann 0001, Mauro Cesar Zanella, Thomas Lehmann 0001	Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Stephane Adriaensen, Denis Flandre	Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Grant Martin	SystemC and the Future of Design Languages: Opportunities for Users and Research.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Artur Pereira, Antonio Rui Borges, Antonio B. Ferrari	Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann 0001, Ulrich Dierkes, Carsten Rustemeier	Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Alfredo Olmos	A Temperature Compensated Fully Trimmable On-Chip IC Oscillator.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller	Simplification of Toffoli Networks via Templates.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Jefferson B. D. Soldera, Andre Vilas Boas, Alfredo Olmos	A Low Ripple Fully Integrated Charge Pump Regulator.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis 0001, José Luís Almada Güntzel	A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Eric E. Fabris, Luigi Carro, Sergio Bampi	A Universal High-Performance Analog Interface for Signal Processing SOCs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Luiz Franca-Neto	High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro	CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein	Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Patrick Lysaght	System-Level Design for FPGAs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Ivan Augé, François Donnet, Frédéric Pétrot	Retiming Finite State Machines to Control Hardened Data-Paths.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva	A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes 0001, Everton Carara	From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.	SBCCI	2003	DBLP DOI BibTeX RDF	transaction level, VHDL, SystemC, System modeling, register transfer level
1	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages.	SBCCI	2003	DBLP DOI BibTeX RDF	Background Calibration, Analog-to-Digital Converter, Pipeline ADC, LMS algorithm
1	Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis	Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Sandro Binsfeld Ferreira, José Felipe Haffner, Luís Fernando Alves Pereira, Fernando Moraes 0001	Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Christian Haubelt, Dirk Koch, Jürgen Teich	ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije	A Methodology for CMOS Low Noise Ampli.er Design.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Julio A. de Oliveira Filho, Manoel Eusébio de Lima, Paulo Romero Martins Maciel, Juliana Moura, Bruno Celso	A Fast IP-Core Integration Methodology for SoC Design.	SBCCI	2003	DBLP DOI BibTeX RDF

Publications at "SBCCI"( http://dblp.L3S.de/Venues/SBCCI )