Search results for "VLSI-SoC"

Hits ?▲	Authors	Title	Venue	Year	Link
32	Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis	Probabilistic Models for Off-Line Arbiters in Embedded Systems.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	F. L. Denis Nunes, Márcio Eduardo Kreutz	Using SDN Strategies to Improve Resource Management On a NoC.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis	Exploring area and total wirelength using a cell merging technique.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Soner Seçkiner, Longfei Wang, Selçuk Köse	An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt	SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Diego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier de Souza	Exploiting guard band limits for energy gains in MPSoCs.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Wellington Silva de Souza, Arman Iranfar, Anderson B. N. da Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza	A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Arman Iranfar, Wellington Silva de Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza	A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin	On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Owais Talaat Waheed, Ibrahim Abe M. Elfadel	Domain-Specific Architecture for IMU Array Data Fusion.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis	Netlist Optimization by Gate Merging.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen	Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Atishay, Ankit Gupta 0010, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B	SEARS: A Statistical Error and Redundancy Analysis Simulator.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Denis F. L. Nunes, Silvio Roberto Fernandes de Araujo, Márcio Eduardo Kreutz	Optimizing an Architecture with Software Pipelining Strategies.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Solon Falas, Charalambos Konstantinou, Maria K. Michael	A Hardware-based Framework for Secure Firmware Updates on Embedded Systems.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Vitor V. Bandeira, Felipe Rosa 0001, Ricardo Augusto da Luz Reis, Luciano Ost	Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Impact of Process Variability and Single Event Transient on FinFET Technology.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik	Engineering of an Effective Automatic Dynamic Assertion Mining Platform.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Sandro Matheus V. N. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Alessandro Gonçalves Girardi, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon	The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza	Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet	A Digital Event-Based Strategy for ASK demodulation.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza	An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez 0001	Exploiting Approximate Computing to Increase System Lifetime.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Keisuke Inoue	An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon	A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Bin Wu, Matthew R. Guthaus	Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Vitor V. Bandeira, Isadora Oliveira, Felipe da Rosa 0001, Ricardo A. L. Reis, Luciano Ost	Soft Error Reliability Analysis of Autonomous Vehicles Software Stack.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski	Functional Verification of Hardware Dividers using Algebraic Model.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32	Yu-Cheng Chen, Vincent John Mooney, Santiago Grijalva	A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
32		IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018	VLSI-SoC	2018	DBLP BibTeX RDF
32	Valentino Peluso, Andrea Calimera	Energy-Driven Precision Scaling for Fixed-Point ConvNets.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Gionata Benelli, Gabriele Meoni, Luca Fanucci	A low power keyword spotting algorithm for memory constrained embedded systems.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Evelina Forno, Andrea Acquaviva, Yuki Kobayashi, Enrico Macii, Gianvito Urgese	A Parallel Hardware Architecture For Quantum Annealing Algorithm Acceleration.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Anna Bernasconi 0001, Antonio Boffa, Fabrizio Luccio, Linda Pagli	Two Combinatorial Problems on the Layout of Switching Lattices.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Florenc Demrozi, Kevin Costa, Federico Tramarin, Graziano Pravadelli	A graph-based approach for mobile localization exploiting real and virtual landmarks.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Edouard Giacomin, Pierre-Emmanuel Gaillardon	Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Yakup Murat	Key Architectural Optimizations for Hardware Efficient JPEG-LS Encoder.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Muhammad Awais 0009, Hassan Ghasemzadeh Mohammadi, Marco Platzner	An MCTS-based Framework for Synthesis of Approximate Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Lorena Anghel, Denys Ly, Giorgio Di Natale, Benoît Miramond, Elena Ioana Vatajelu, Elisa Vianello	Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Mubashir Hussain, Hui Guo 0001	A Bandwidth-Aware Authentication Scheme for Packet-Integrity Attack Detection on Trojan Infected NoC.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Md. Adnan Zaman, Srinivas Katkoori	Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Luiz Antonio de Oliveira Junior, Edna Barros	An FPGA-based Hardware Accelerator for Scene Text Character Recognition.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini	Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Mahabub Hasan Mahalat, Nikhil Ugale, Rohit Shahare, Bibhash Sen	Design of Latch based Configurable Ring Oscillator PUF Targeting Secure FPGA.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang	Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Achraf Lamlih, Philippe Freitas, Mohamed Moez Belhaj, Jérémie Salles, Vincent Kerzerho, Fabien Soulier, Serge Bernard, Tristan Rouyer, Sylvain Bonhommeau	A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Stefano Centomo, Marco Panato, Franco Fummi	Cyber-Physical Systems Integration in a Production Line Simulator.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Ian O'Connor, Mayeul Cantan, Cédric Marchand 0002, Bertrand Vilquin, Stefan Slesazeck, Evelyn T. Breyer, Halid Mulaosmanovic, Thomas Mikolajick, Bastien Giraud, Jean-Philippe Noel, Adrian M. Ionescu, Igor Stolichnov	Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Naoki Ojima, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Shahzad Muzaffar, Ibrahim Abe M. Elfadel	An Instruction Set Architecture for Low-power, Dynamic IoT Communication.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Utkarsh Gupta, Irina Ilioaea, Vikas Rao, Arpitha Srinath, Priyank Kalla, Florian Enescu	On the Rectifiability of Arithmetic Circuits using Craig Interpolants in Finite Fields.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Erya Deng, Zhaohao Wang, Wang Kang 0001, Shaoqian Wei, Weisheng Zhao	Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Pasquale Davide Schiavone, Ernesto Sánchez 0001, Annachiara Ruospo, Francesco Minervini, Florian Zaruba, Germain Haugou, Luca Benini	An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Francesco Barchi, Gianvito Urgese, Andrea Acquaviva, Enrico Macii	Directed Graph Placement for SNN Simulation into a multi-core GALS Architecture.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Sophiane Senni, Frederic Ouattara, Jad Mohdad, Kaan Sevin, Guillaume Patrigeon, Pascal Benoit, Pascal Nouet, Lionel Torres, François Duhem, Gregory di Pendina, Guillaume Prenat	From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay	Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Julien Le Kernec, Francesco Fioranelli, Shufan Yang, Jordane Lorandel, Olivier Romain	Radar for assisted living in the context of Internet of Things for Health and beyond.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Mahdi Tala, Davide Bertozzi	Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Anna Bernasconi 0001, Valentina Ciriani, Luca Frontini	Testability of Switching Lattices in the Stuck at Fault Model.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Luca Stornaiuolo, Marco Rabozzi, Donatella Sciuto, Marco D. Santambrogio, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu	HLS Support for Polymorphic Parallel Memories.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Swagata Mandal, Debjyoti Bhattacharjee, Yaswanth Tavva, Anupam Chattopadhyay	ReRAM-based In-Memory Computation of Galois Field arithmetic.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Konstantin Braun, Tim Fritzmann, Georg Maringer, Thomas Schamberger, Johanna Sepúlveda	Secure and Compact Full NTRU Hardware Implementation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Rahul Shrestha, Ashutosh Sharma	VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Stefano Aldegheri, Silvia Manzato, Nicola Bombieri	Enhancing Performance of Computer Vision Applications on Low-Power Embedded Systems Through Heterogeneous Parallel Programming.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin	Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Keerthikumara Devarajegowda, Wolfgang Ecker	Meta-model Based Automation of Properties for Pre-Silicon Verification.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa	An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Marc Souchaud, Pierre Jacob, Camille Simon Chane, Aymeric Histace, Olivier Romain, Maurice Tchuenté, Denis Sereno	Mobile Phones Hematophagous Diptera Surveillance in the field using Deep Learning and Wing Interference Patterns.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Steve Bigalke, Jens Lienig	FLUTE-EM: Electromigration-Optimized Net Considering Topology Currents and Mechanical Stress.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener	Design Understanding: From Logic to Specification*.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Valerio Tenace, Andrea Calimera	Inferential Logic: a Machine Learning Inspired Paradigm for Combinational Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Anastasis Keliris, Charalambos Konstantinou, Marios Sazos, Michail Maniatakos	Low-budget Energy Sector Cyberattacks via Open Source Exploitation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Zahira Perez, Hector Villacorta, Víctor H. Champac	An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Riccardo Cantoro, Sara Carbonara, Andrea Floridia, Ernesto Sánchez 0001, Matteo Sonza Reorda, Jan-Gerd Mess	An analysis of test solutions for COTS-based systems in space applications.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Mathieu Moreau, Eloi Muhr, Marc Bocquet, Hassen Aziza, Jean-Michel Portal, Bastien Giraud, Jean-Philippe Noel	Reliable ReRAM-based Logic Operations for Computing in Memory.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Suyuan Chen, Ranga Vemuri	On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Andres F. Gomez, Freddy Forero, Kaushik Roy 0001, Víctor H. Champac	Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32	Reza Ranjandish, Alexandre Schmid	Implantable IoT System for Closed-Loop Epilepsy Control based on Electrical Neuromodulation.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
32		2017 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017	VLSI-SoC	2017	DBLP BibTeX RDF
32	Daniele Cesarini, Andrea Bartolini, Luca Benini	Prediction horizon vs. efficiency of optimal dynamic thermal control policies in HPC nodes.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Thiago Santos Copetti, Tiago R. Balen, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls	Analyzing the behavior of FinFET SRAMs with resistive defects.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano	Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Shuangxing Zhao, Chenchang Zhan, Guigang Cai	A 2×VDD-enabled fully-integrated low-dropout regulator with fast transient response.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Mahesh Kumar Adimulam, Krishna Kumar Movva, Amit Kapoor, M. B. Srinivas	A low power, programmable bias inverter quantizer (BIQ) flash ADC.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu	Defect-aware synthesis for reconfigurable single-electron transistor arrays.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Matthias Thiele, Steve Bigalke, Jens Lienig	Exploring the use of the finite element method for electromigration analysis in future physical design.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Kyounghoon Kim, Kiyoung Choi	Synthesis of multi-variate stochastic computing circuits.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Stelvio Cimato, Valentina Ciriani, Ernesto Damiani, Maryam Ehsanpour	A multiple valued logic approach for the synthesis of garbled circuits.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Hans G. Kerkhoff, Ghazanfar Ali, Jinbo Wan, Ahmed Ibrahim 0001, Jerrin Pathrose	Applying IJTAG-compatible embedded instruments for lifetime enhancement of analog front-ends of cyber-physical systems.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Mohammed Ismail 0001	A self-powered IoT SoC platform for wearable health care.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Binod Kumar 0001, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh	Improving post-silicon error detection with topological selection of trace signals.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Shahzad Muzaffar, Ibrahim M. Elfadel	A pulsed decimal technique for single-channel, dynamic signaling for IoT applications.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Roberto Giorgio Rizzo, Valentino Peluso, Andrea Calimera, Jun Zhou 0017, Xin Liu 0015	Early bird sampling: A short-paths free error detection-correction strategy for data-driven VOS.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Muhammad Yasin, Ozgur Sinanoglu	Evolution of logic locking.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	George Michael, Nectarios Efstathiou, Kyriacos Mantis, Theocharis Theocharides, Danilo Pau	Intelligent embedded and real-time ANN-based motor control for multi-rotor unmanned aircraft systems.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Stefano Aldegheri, Nicola Bombieri	Extending OpenVX for model-based design of embedded vision applications.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
32	Murugappan Alagappan, Jeyavijayan Rajendran, Milos Doroslovacki, Guru Venkataramani	DFS covert channels on multi-core platforms.	VLSI-SoC	2017	DBLP DOI BibTeX RDF