Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Göran Jerke, Jens Lienig	Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	Sheldon X.-D. Tan, C.-J. Richard Shi	Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy	On the exploration of the solution space in analog placement with symmetry constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	Liuqing Yang 0001, Georgios B. Giannakis	Analog space-time coding for multiantenna ultra-wideband transmissions.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
17	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
17	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Low Cost Analog Testing of RF Signal Paths.	DATE	2004	DBLP DOI BibTeX RDF
17	Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang	A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
17	Jochen Rivoir	Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	low-cost ATE, multi-site test, mixed-signal test, concurrent test, low-cost test, test resource partitioning
17	Chin-Long Wey, Meng-Yao Liu	Burn-In Stress Test of Analog CMOS ICs.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
17	Daniel Matolin, Jörg Schreiter, Stefan Getzlaff, René Schüffny	An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation.	PARELEC	2004	DBLP DOI BibTeX RDF
17	Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar	Towards formal verification of analog designs.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Ranga Vemuri, Glenn Wolfe	Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Jörg Langeheine, Martin Trefzer, Daniel Brüderle, Karlheinz Meier, Johannes Schemmel	On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA.	GECCO (1)	2004	DBLP DOI BibTeX RDF
17	Kalle Ruttik	BER for CMOS Analog Decoder with Different Working Points.	ICT	2004	DBLP DOI BibTeX RDF
17	Silviu Ionita, Emil Sofron	Field-Programmable Analog Filters Array with Applications for Fuzzy Inference Systems.	HIS	2004	DBLP DOI BibTeX RDF
17	Joachim Becker, Yiannos Manoli	A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Gladys Omayra Ducoudray, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal	High-speed high-precision analog rank order filter in CMOS technology.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Zeljko Ignjatovic, Mark F. Bocko	Sigma-delta analog to digital converter architecture based upon a modulator design employing a mirrored integrator.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Roxana Saint-Nom, Daniel Jacoby	Switched capacitors: a bridge between analog and digital SP.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Nhan Nguyen, Chris Winstead, Vincent C. Gaudet, Christian Schlegel	A 0.8V CMOS analog decoder for an (8, 4, 4) extended Hamming code.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Shantanu Chakrabartty, Gert Cauwenberghs	Margin normalization and propagation in analog VLSI.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Chun-Cheng Huang, Jieh-Tsorng Wu	A statistical background calibration technique for flash analog-to-digital converters.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Stephen P. Carullo, Michael Olaleye, Chika Nwankpa	VSLI Based Analog Power System Emulator for Fast Contingency Analysis.	HICSS	2004	DBLP DOI BibTeX RDF
17	Yukiya Miura	Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method.	DFT	2004	DBLP DOI BibTeX RDF
17	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.	VTS	2004	DBLP DOI BibTeX RDF
17	Claudio Mattiussi, Dario Floreano	Evolution of Analog Networks using Local String Alignment on Highly Reorganizable Genomes.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
17	Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser	Will Moore's Law rule in the land of analog?	DAC	2004	DBLP DOI BibTeX RDF
17	Mandeep Singh, Israel Koren	Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
17	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Alex Doboli, Ranga Vemuri	Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Carles Pous, Joan Colomer, Joaquím Meléndez, Josep Lluís de la Rosa	Case Base Management for Analog Circuits Diagnosis Improvement.	ICCBR	2003	DBLP DOI BibTeX RDF
17	Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man	Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver.	DATE	2003	DBLP DOI BibTeX RDF
17	Peng Li 0001, Xin Li 0001, Yang Xu 0017, Lawrence T. Pileggi	A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
17	Cesare Alippi, Marco Stellini	High level accuracy loss estimates for a class of analog/digital systems.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Sandro A. P. Haddad, Richard Houben, Wouter A. Serdijn	Analog wavelet transform employing dynamic translinear circuits for cardiac signal characterization.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
17	Sarat C. Maruvada, Karthik Krishnamoorthy, Subodh Annojvala, Florin Balasa	Placement with symmetry constraints for analog layout using red-black trees.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Gustavo Liñán Cembrano, Ángel Rodríguez-Vázquez, Ricardo Carmona-Galán, Servando Espejo-Meana, Rafael Domínguez-Castro	Analog weight buffering strategy for CNN chips.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
17	Timothy Kuan-Ta Lu, Michael W. Baker, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar	A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu	Algorithms for analog VLSI 2D stack generation and block merging.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Matteo Perenzoni, Andrea Gerosa, Andrea Neviani	Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Christian Falconi, Arnaldo D'Amico, Marco Faccio	Design of accurate analog circuits for low voltage low power CMOS systems.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
17	Esteban Tlelo-Cuautle, Alejandro Díaz-Sánchez	An heuristic circuit-generation technique for the design-automation of analog circuits.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
17	James M. Masciotti, Lessing Luu, Dariusz Czarkowski	CMOS current-mode analog circuit building blocks for rf DC-DC converter controllers.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
17	H. S. Ng, Sui-Tung Mak, Kai-Pui Lam	Field programmable gate arrays and analog implementation of BRIN for optimization problems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani	A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits.	DFT	2003	DBLP DOI BibTeX RDF
17	Yukiya Miura, Daisuke Kato	Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation.	DFT	2003	DBLP DOI BibTeX RDF
17	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.	VTS	2003	DBLP DOI BibTeX RDF
17	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	Concurrent Error Detection in Linear Analog Circuits Using State Estimation.	ITC	2003	DBLP DOI BibTeX RDF
17	Jeannette Plante, Harry C. Shaw, Lisa P. Mickens, Charles T. Johnson-Bey	Overview of Field Programmable Analog Arrays as Enabling Technology for Evolvable Hardware for High Reliability Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
17	Fernando De Bernardinis, Michael I. Jordan, Alberto L. Sangiovanni-Vincentelli	Support vector machines for analog circuit performance representation.	DAC	2003	DBLP DOI BibTeX RDF
17	Razvan Ionita, Andrei Vladimirescu, Paul G. A. Jespers	Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.	PATMOS	2002	DBLP DOI BibTeX RDF
17	Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez	Bio-Inspired Analog VLSI Design Realizes Programmable Complex Spatio-Temporal Dynamics on a Single Chip.	DATE	2002	DBLP DOI BibTeX RDF
17	Alex Doboli, Ranga Vemuri	A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems.	DATE	2002	DBLP DOI BibTeX RDF
17	Jacob Savir, Zhen Guo	Test Limitations of Parametric Faults in Analog Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
17	Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy	Efficient solution space exploration based on segment trees in analog placement with symmetry constraints.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Sule Ozev, Alex Orailoglu	Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
17	Jacob Savir, Zhen Guo	On the Detectability of Parametric Faults in Analog Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
17	Janusz A. Starzyk, Dong Liu	A decomposition method for analog fault location.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
17	Lihong Zhang, Ulrich Kleine	A genetic approach to analog module placement with simulated annealing.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
17	Ricardo Carmona, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana, Ángel Rodríguez-Vázquez	Bio-inspired analog parallel array processor chip with programmable spatio-temporal dynamics.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
17	Eric J. McDonald, Bradley A. Minch	Synthesis of a translinear analog adaptive filter.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
17	Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel	Cell library for automatic synthesis of analog error control decoders.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
17	Mostafa A. R. Eltokhy, Boon-Keat Tan, Toshimasa Matsuoka, Kenji Taniguchi 0001	A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
17	Toshihiko Yamasaki, Teruyasu Taguchi, Tadashi Shibata	Low-power CDMA analog matched filters based on floating-gate technology.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
17	Viera Stopjaková, Daniel Micusík, Lubica Benusková, Martin Margala	Neural Networks-Based Parametric Testing of Analog IC.	DFT	2002	DBLP DOI BibTeX RDF
17	Lyudmila Zinchenko, Heinz Mühlenbein, Victor Kureichik, Thilo Mahnig	Application of the Univariate Marginal Distribution Algorithm to Analog Circuit Design.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
17	Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny	An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.	ICANN	2002	DBLP DOI BibTeX RDF
17	Debapriya Sahu	A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
17	Ion E. Opris, Seiichiro Watanabe	A Fast Analog Front-End Processor for Digital Imaging Systems.	IEEE Micro	2001	DBLP DOI BibTeX RDF
17	Chang-Ki Kwon, Kwyro Lee	Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	Jun-Weir Lin, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	Fault Diagnosis for Linear Analog Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	diagnosing evaluators, un-powered network, fault diagnosis, signal flow graph
17	Biranchinath Sahu, Abhijit Chatterjee	Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	test transfer function model, AC testing, optimization, fault simulation
17	Achintya Halder, Abhijit Chatterjee	Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
17	Johannes Schemmel, Karlheinz Meier, Felix Schürmann	A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms.	ICES	2001	DBLP DOI BibTeX RDF
17	Karen Nazaryan	Quasi Analog Formal Neuron and Its Learning Algorithm Hardware.	International Conference on Computational Science (2)	2001	DBLP DOI BibTeX RDF
17	Nuno F. Paulino, João Goes, Adolfo Steiger-Garção	Design methodology for optimization of analog building blocks using genetic algorithms.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
17	Costantino Pala, Lars Thylén, Mehrun Mokhtari, Urban Westergren	A high-speed electro-optical analog-to-digital converter principle.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Eduard Alarcón, Alfonso Romero 0001, Alberto Poveda, Sonia Porta, Luis Martínez-Salamero	Sliding-mode control analog integrated circuit for switching DC-DC power converters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	David H. Goldberg, Gert Cauwenberghs, Andreas G. Andreou	Analog VLSI spiking neural network with address domain probabilistic synapses.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
17	Alex Doboli, Ranga Vemuri	Hierarchical performance optimization for synthesis of linear analog systems.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
17	Shashidhar Tantry, Teru Yoneyama, Hideki Asai	Two floating resistor circuits and their applications to synaptic weights in analog neural networks.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Samgsuk Kim, Minkyu Song	An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Toshihiko Yamasaki, Atsushi Suzuki, Daisuke Kobayashi, Tadashi Shibata	A fast self-convergent flash-memory programming scheme for MV and analog data storage.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
17	Bogdan Pankiewicz, Marek Wójcikowski, Stanislaw Szczepanski, Yichuang Sun	A CMOS field programmable analog array and its application in continuous-time OTA-C filter design.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan	A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Neeraj Nayak, Baiying Yu, William C. Black Jr.	A comparison of transient digitization methods for high speed analog signals.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
17	Pierluigi Daglio, M. Araldi, Michele Morbarigazzi, Carlo Roma	A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies.	ISQED	2001	DBLP DOI BibTeX RDF
17	Mohammad Athar Khalil, Chin-Long Wey	High-Voltage Stress Test Paradigms of Analog CMOS ICs for Gate-Oxide Reliability Enhancement.	VTS	2001	DBLP DOI BibTeX RDF
17	Sheldon X.-D. Tan, C.-J. Richard Shi	Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	Bapiraju Vinnakota, Ramesh Harjani	DFT for digital detection of analog parametric faults in SC filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	C.-J. Richard Shi, Sheldon X.-D. Tan	Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
17	Sydney Reader, Won Namgoong, Teresa H. Meng	Partitioning Analog and Digital Processing in Mixed-Signal Systems.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
17	Christian Paulus, Ulrich Kleine, Roland Thewes	Area Optimization of Analog Circuits Considering Matching Constraints.	DATE	2000	DBLP DOI BibTeX RDF
17	Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski	Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.	DATE	2000	DBLP DOI BibTeX RDF
17	Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte	Layout-Oriented Synthesis of High Performance Analog Circuits.	DATE	2000	DBLP DOI BibTeX RDF
17	Martin Margala, Srdjan Dragic, Ahmed El-Abasiry, Samuel Ekpe, Viera Stopjaková	I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Testing, Sensors, Iddq, Ultra-Low-Voltage, Current
17	Tetsuya Asai, Masato Koutani, Yoshihito Amemiya	An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
17	Ramakrishna Voorakaranam, Abhijit Chatterjee	Test Generation for Accurate Prediction of Analog Specifications.	VTS	2000	DBLP DOI BibTeX RDF
17	Tao Pi, C.-J. Richard Shi	Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.	DAC	2000	DBLP DOI BibTeX RDF
17	Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh	Test set selection for structural faults in analog IC's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF