Search results for "cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Ruirui C. Huang, Daniel Y. Deng, G. Edward Suh	Orthrus: efficient software integrity protection on multi-cores.	ASPLOS	2010	DBLP DOI BibTeX RDF	replication-aware architecture, software diversity and redundancy, software security, multi-core architecture, memory protection
18	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
18	Feng Ge, Pranjal Jain, Ken Choi	Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
18	Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zhang, Dongrui Fan	High Performance Matrix Multiplication on Many Cores.	Euro-Par	2009	DBLP DOI BibTeX RDF
18	Heiner Giefers, Marco Platzner	ARMLang: A language and compiler for programming reconfigurable mesh many-cores.	IPDPS	2009	DBLP DOI BibTeX RDF
18	Muhammet Erkoc, Arda Yurdakul	Halftoning soft cores for low-cost digital displays.	ISCIS	2009	DBLP DOI BibTeX RDF
18	Amit Pande, Joseph Zambreno	Efficient Translation of Algorithmic Kernels on Large-Scale Multi-cores.	CSE (2)	2009	DBLP DOI BibTeX RDF
18	Albert Meixner, Michael E. Bauer, Daniel J. Sorin	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, dependability, error detection, microarchitecture
18	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Ozgur Sinanoglu, Tsvetomir Petrov	Isolation Techniques for Soft Cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
18	Roberto Asín, Robert Nieuwenhuis, Albert Oliveras, Enric Rodríguez-Carbonell	Efficient Generation of Unsatisfiability Proofs and Cores in SAT.	LPAR	2008	DBLP DOI BibTeX RDF
18	Peng Chen 0001, Chunmei Liu, Legand L. Burge III, Mahmood Mohammad, William M. Southerland, Clay Gloster	Prediction of Inter-residue Contact Clusters from Hydrophobic Cores.	ICMLA	2008	DBLP DOI BibTeX RDF
18	Saulo Oliveira Dornellas Luiz, Genildo de Moura Vasconcelos, Leandro Dias da Silva	Formal specification of DSP gateway for data transmission between processor cores of OMAP platform.	SAC	2008	DBLP DOI BibTeX RDF	OMAP161x platform, modelling, model checking, embedded systems, timed-automata, discrete event systems, inter-processor communication
18	Shan Tang, Qiang Xu 0001	A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Heiner Giefers	Reconfigurable many-cores with lean interconnect.	FPL	2008	DBLP DOI BibTeX RDF
18	Markus Koester, Wayne Luk, Geoffrey Brown	A hardware compilation flow for instance-specific VLIW cores.	FPL	2008	DBLP DOI BibTeX RDF
18	Alexander Klimm, Lars Braun, Jürgen Becker 0001	An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores.	IPDPS	2008	DBLP DOI BibTeX RDF
18	Yousra Alkabani, Farinaz Koushanfar	Active control and digital rights management of integrated circuit IP cores.	CASES	2008	DBLP DOI BibTeX RDF	active IP control, security, IP protection
18	André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler	Using unsatisfiable cores to debug multiple design errors.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	sat-based debugging, unsatisfiable core, fault localization
18	Francesco Abate, Massimo Violante	Coping with Obsolescence of Processor Cores in Critical Applications.	DFT	2008	DBLP DOI BibTeX RDF
18	Peter Damaschke	Multiple Hypernode Hitting Sets and Smallest Two-Cores with Targets.	COCOA	2008	DBLP DOI BibTeX RDF
18	Gregory L. Lee, Dong H. Ahn, Dorian C. Arnold, Bronis R. de Supinski, Matthew P. LeGendre, Barton P. Miller, Martin Schulz 0001, Ben Liblit	Lessons learned at 208K: towards debugging millions of cores.	SC	2008	DBLP DOI BibTeX RDF
18	Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy 0001, Shay Gueron	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	Rashid Rashidzadeh, Majid Ahmadi, William C. Miller	Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Dan Zhao, Unni Chandran, Hideo Fujiwara	Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores.	ASP-DAC	2007	DBLP DOI BibTeX RDF
18	Encarnación Castillo, Luis Parrilla 0001, Antonio García 0001, Uwe Meyer-Bäse, Antonio Lloris-Ruíz	Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.	FPL	2007	DBLP DOI BibTeX RDF
18	Li Zhang 0034, Chris R. Jesshope	On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
18	Mazen A. R. Saghir, Rawan Naous	A Configurable Multi-ported Register File Architecture for Soft Processor Cores.	ARC	2007	DBLP DOI BibTeX RDF
18	Sylvie Renaud, Jean Tomas, Yannick Bornat, Adel Daouzli, Sylvain Saïghi	Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Shrutisagar Chandrasekaran, Abbes Amira	A New Behavioural Power Modelling Approach for FPGA based Custom Cores.	AHS	2007	DBLP DOI BibTeX RDF
18	Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara	Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.	VTS	2007	DBLP DOI BibTeX RDF	multi-clock domain, wrapper design, SoC, test scheduling, embedded core test
18	Andrew B. T. Hopkins, Klaus D. McDonald-Maier	Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	multiprocessor systems, System architectures, real-time and embedded systems, debugging aids, integration and modeling
18	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	A Self Test Program Design Technique for Embedded DSP Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	self test programs, pseudorandom BIST, LSFR, DSP, ATPG
18	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
18	Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos	Efficient test-data compression for IP cores using multilevel Huffman coding.	DATE	2006	DBLP DOI BibTeX RDF
18	Georg Gottlob, Alan Nash	Data exchange: computing cores in polynomial time.	PODS	2006	DBLP DOI BibTeX RDF	complexity, databases, data integration, constraints, dependencies, data exchange, core, conjunctive queries, query evaluation, tractability, chase, universal solutions
18	Chen Wu, Xiaohua Hu 0001, Jingyu Yang, Xibei Yang	Expanding Tolerance RST Models Based on Cores of Maximal Compatible Blocks.	RSCTC	2006	DBLP DOI BibTeX RDF	rough set model, knowledge represented system, entropy, incomplete information system
18	Ian D. L. Anderson, Mohammed A. S. Khalid	Design Space Exploration using Parameterized Cores: A Case Study.	CCECE	2006	DBLP DOI BibTeX RDF
18	Koushik Chakraborty, Philip M. Wells, Gurindar S. Sohi	Computation spreading: employing hardware migration to specialize CMP cores on-the-fly.	ASPLOS	2006	DBLP DOI BibTeX RDF	dynamic specialization, cache locality
18	Wenbiao Zhou, Yan Zhang 0066, Zhigang Mao	Pareto based Multi-objective Mapping IP Cores onto NoC Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
18	Jianmin Zhang, Sikun Li, ShengYu Shen	Extracting Minimum Unsatisfiable Cores with a Greedy Genetic Algorithm.	Australian Conference on Artificial Intelligence	2006	DBLP DOI BibTeX RDF
18	Qiang Xu 0001, Nicola Nicolici	Wrapper design for multifrequency IP cores.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy 0001	Synthesis of application-specific highly efficient multi-mode cores for embedded systems.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system
18	B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu	At-Speed Logic BIST for IP Cores.	DATE	2005	DBLP DOI BibTeX RDF
18	Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos	A processor for testing mixed-signal cores in System-on-Chip.	DSD	2005	DBLP DOI BibTeX RDF
18	K. Uday Bhaskar, M. Prasanth, V. Kamakoti 0001, Kailasnath Maneparambil	A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
18	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
18	Jakub Wroblewski	Pairwise Cores in Information Systems.	RSFDGrC (1)	2005	DBLP DOI BibTeX RDF
18	Georg Gottlob	Computing cores for data exchange: new algorithms and practical solutions.	PODS	2005	DBLP DOI BibTeX RDF
18	Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
18	Ludovic L'Hours	Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications.	ASAP	2005	DBLP DOI BibTeX RDF
18	Sudarshan Bahukudumbi, Krishna Bharath	A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan	Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Qiang Xu 0001, Nicola Nicolici, Krishnendu Chakrabarty	Multi-frequency wrapper design and optimization for embedded cores under average power constraints.	DAC	2005	DBLP DOI BibTeX RDF	scan control unit, wrapper design, multiple clock domains
18	Linjian Mo, Haixiang Zhang, Jiajun Bu, Chun Chen 0001	Speed Optimization of a MPEG-4 Software Decoder Based on ARM Family Cores.	ICIAR	2005	DBLP DOI BibTeX RDF
18	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
18	Hendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard P. Fettweis	Generated DSP Cores for Implementation of an OFDM Communication System.	SAMOS	2004	DBLP DOI BibTeX RDF
18	Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda	Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores.	MTV	2004	DBLP DOI BibTeX RDF
18	Michael Molloy 0001	The pure literal rule threshold and cores in random hypergraphs.	SODA	2004	DBLP BibTeX RDF
18	Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna	STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.	DATE	2004	DBLP DOI BibTeX RDF
18	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	Designing Self Test Programs for Embedded DSP Cores.	DATE	2004	DBLP DOI BibTeX RDF
18	Qiang Xu 0001, Nicola Nicolici	Wrapper Design for Testing IP Cores with Multiple Clock Domains.	DATE	2004	DBLP DOI BibTeX RDF
18	Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu	Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment.	CIT	2004	DBLP DOI BibTeX RDF
18	Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu	Mixed-clock issue queue design for energy aware, high-performance cores.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada	Design methodology for SoC arthitectures based on reusable virtual cores.	ASP-DAC	2004	DBLP DOI BibTeX RDF
18	Kazuko Kambe, Michiko Inoue, Hideo Fujiwara	Efficient Template Generation for Instruction-Based Self-Test of Processor Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
18	Rawat Siripokarpirom	Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
18	Rawat Siripokarpirom, Friedrich Mayer-Lindenberg	Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
18	Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici	Compressed Embedded Diagnosis of Logic Cores.	ICCD	2004	DBLP DOI BibTeX RDF	Built-In Diagnosis, Test Data Compression
18	Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante	Hybrid Soft Error Detection by Means of Infrastructure IP Cores.	IOLTS	2004	DBLP DOI BibTeX RDF
18	Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi	Scan Test of IP Cores in an ATE Environment.	DELTA	2004	DBLP DOI BibTeX RDF
18	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Delay Fault Self-Testing of Processor Cores.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu	Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits.	IWDC	2004	DBLP DOI BibTeX RDF
18	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test
18	Ozgur Sinanoglu, Alex Orailoglu	Compacting Test Responses for Deeply Embedded SoC Cores.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
18	Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero	Fully Automatic Test Program Generation for Microprocessor Cores.	DATE	2003	DBLP DOI BibTeX RDF
18	Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Riadh Gaiech, Eric Martin 0001	A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration.	DATE	2003	DBLP DOI BibTeX RDF
18	Zhigang Jiang, Sandeep K. Gupta 0001	A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
18	Sangman Moh, Kyoung Park, Sungnam Kim	KinCA: An InfiniBand Host Channel Adapter Based on Dual Processor Cores.	ISCIS	2003	DBLP DOI BibTeX RDF
18	Marcio Buss, Tony Givargis, Nikil D. Dutt	Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores.	RTSS	2003	DBLP DOI BibTeX RDF
18	Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero	Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.	ISHPC	2003	DBLP DOI BibTeX RDF
18	Ahmet T. Erdogan, Tughrul Arslan	Low power block based FIR filtering cores.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	George Xenoulis, Dimitris Gizopoulos, Nektarios Kranitis, Antonis M. Paschalis	Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores.	IOLTS	2003	DBLP DOI BibTeX RDF
18	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Transparency of Cores in System-on-a-Chip.	VTS	2003	DBLP DOI BibTeX RDF	consecutive transparency, design for testability, system-on a chip, register transfer level, test access mechanism, consecutive testability
18	Praveen Bhojwani, Rabi N. Mahapatra	Interfacing Cores with On-chip Packet-Switched Networks.	VLSI Design	2003	DBLP DOI BibTeX RDF
18	Tony Givargis, Frank Vahid, Jörg Henkel	Instruction-based system-level power evaluation of system-on-a-chip peripheral cores.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
18	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
18	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.	DFT	2002	DBLP DOI BibTeX RDF
18	M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff	A New Test Generation Approach for Embedded Analogue Cores in SoC.	ITC	2002	DBLP DOI BibTeX RDF
18	Mohsen Nahvi, André Ivanov, Resve A. Saleh	Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.	ITC	2002	DBLP DOI BibTeX RDF
18	Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang	An on-chip march pattern generator for testing embedded memory cores.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Rolf Backofen, Sebastian Will	Optimally Compact Finite Sphere Packings - Hydrophobic Cores in the FCC.	CPM	2001	DBLP DOI BibTeX RDF
18	Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty	Synthesis of single-output space compactors with application to scan-based IP cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
18	John MacBeth, Patrick Lysaght	Dynamically Reconfigurable Cores.	FPL	2001	DBLP DOI BibTeX RDF
18	Jürgen Becker 0001, Nicolas Liebau, Thilo Pionteck, Manfred Glesner	Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures.	FPL	2001	DBLP DOI BibTeX RDF
18	Albert Simpson, Jill K. Hunter, Moira Wylie, Yi Hu, David Mann	Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing.	FPL	2001	DBLP DOI BibTeX RDF
18	Mauro Olivieri, Alessandro Trifiletti	An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.	ISCAS (4)	2001	DBLP DOI BibTeX RDF