Search results for "wiring"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Federico Silla, José Duato	On the Use of Virtual Channels in Networks of Workstations with Irregular Topology.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	block multiplexing, channel pipelining, flow control, Networks of workstations, virtual channels, wormhole switching, irregular topology
9	Federico Silla, José Duato	High-Performance Routing in Networks of Workstations with Irregular Topology.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	adaptive routing, Networks of workstations, wormhole switching, deadlock avoidance, irregular topologies
9	Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. Panda 0001	Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	switch/router architecture, performance evaluation, multicast, interconnection networks, broadcast, collective communication, wormhole switching, Parallel computer architecture, cut-through switching
9	Sung-Woo Hur, Ashok Jagannathan, John Lillis	Timing-driven maze routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
9	Miroslaw Kutylowski, Krzysztof Lorys, Brigitte Oesterdiekhoff, Rolf Wanka	Periodification scheme: constructing sorting networks with constant period.	J. ACM	2000	DBLP DOI BibTeX RDF	comparator network
9	Jean-Baptiste Boullié, Michel Brun	A New Rolling Stock Architecture Using Safety Computers and Networks.	DSN	2000	DBLP DOI BibTeX RDF
9	Alexander Marquardt, Vaughn Betz, Jonathan Rose	Timing-driven placement for FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
9	Youxin Gao, D. F. Wong 0001	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
9	Xavier Molero, Federico Silla, Vicente Santonja	Modeling and Simulation of a Network of Workstations with Wormhole Switching.	Annual Simulation Symposium	2000	DBLP DOI BibTeX RDF	performance evaluation, modeling, routing algorithms, networks of workstations, wormhole switching, irregular topologies
9	José Flich, Manuel P. Malumbres, Pedro López 0001, José Duato	Improving Routing Performance in Myrinet Networks.	IPDPS	2000	DBLP DOI BibTeX RDF	Networks of workstations, wormhole switching, Myrinet, irregular topologies, minimal routing
9	José Flich, Manuel P. Malumbres, Pedro López 0001, José Duato	Performance evaluation of a new routing strategy for irregular networks with source routing.	ICS	2000	DBLP DOI BibTeX RDF	networks of workstations, wormhole switching, irregular topologies, source routing, minimal routing
9	Shervin Hojat, Paul Kartschoke	Techniques for Improving Timing Convergence of Advanced Microprocessors.	EUROMICRO	2000	DBLP DOI BibTeX RDF
9	Thomas Kutzschebauch	Efficient Logic Optimization Using Regularity Extraction.	ICCD	2000	DBLP DOI BibTeX RDF
9	Henry G. Dietz, Timothy Mattox	Compiler Techniques for Flat Neighborhood Networks.	LCPC	2000	DBLP DOI BibTeX RDF
9	José Flich, Pedro López 0001, Manuel P. Malumbres, José Duato	Improving the Performance of Regular Networks with Source Routing.	ICPP	2000	DBLP DOI BibTeX RDF
9	Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz Parhami	Multilayer VLSI Layout for Interconnection Networks.	ICPP	2000	DBLP DOI BibTeX RDF
9	Olav Lysne, José Duato	Fast Dynamic Reconfiguration in Irregular Networks.	ICPP	2000	DBLP DOI BibTeX RDF
9	Dietrich Birngruber, Markus Hof	Using Plans for Specifying Preconfigured Bean Sets.	TOOLS (34)	2000	DBLP DOI BibTeX RDF	Compositional Patterns, Composition Automation, Components, JavaBeans
9	Minghorng Lai, D. F. Wong 0001	Maze routing with buffer insertion and wiresizing.	DAC	2000	DBLP DOI BibTeX RDF
9	William J. Dally, Andrew Chang 0001	The role of custom design in ASIC Chips.	DAC	2000	DBLP DOI BibTeX RDF
9	Manish Goel, Naresh R. Shanbhag	Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
9	Min Xu, Fadi J. Kurdahi	Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
9	Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang	The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems
9	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
9	Federico Silla, José Duato	Is It Worth the Flexibility Provided by Irregular Topologies in Networks of Workstations?	CANPC	1999	DBLP DOI BibTeX RDF
9	Gerald G. Pechanek, Stamatis Vassiliadis, Nikos Pitsianis	ManArray Processor Interconnection Network: An Introduction.	Euro-Par	1999	DBLP DOI BibTeX RDF
9	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
9	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Is wire tapering worthwhile?	ICCAD	1999	DBLP DOI BibTeX RDF
9	Erwin Riederer, Rolf Matzner	labAlive - A Java Toolbox for the Simulation of Systems.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF	animation and computer graphics, on-line teaching, Java, educational applications
9	Lieven Eeckhout, Henk Neefs, Koenraad De Bosschere, Jan Van Campenhout	Investigating the Implementation of a Block Structured Architecture in an Early Design Stage.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Miuno Toshihiro, Toshimasa Watanabe	Extracting nonplanar connections in a terminal-vertex graph.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
9	Mark J. W. Rodwell, Q. Lee, Dino Mensa, J. Guthrie, Yoram Betser, S. C. Martin, R. P. Smith, S. Jaganathan, Thomas Mathew, P. Krishnan, C. Serhan, Stephen I. Long	Ultra high frequency integrated circuits using transferred substrate heterojunction bipolar transistors.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
9	John Poulton	Problems and Prospects for Electrical Signaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
9	James D. Meindl	XXI Century Gigascale Integration (GSI) : The Interconnect Problem.	ARVLSI	1999	DBLP DOI BibTeX RDF
9	Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran	An Incremental Floorplanner.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
9	Kanad Chakraborty, Natesan Venkateswaran	Congestion Mitigation During Placement.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
9	José Flich, Manuel P. Malumbres, Pedro López 0001, José Duato	Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation.	ICPP	1999	DBLP DOI BibTeX RDF	adaptive routing, Networks of workstations, wormhole switching, irregular topologies, execution-driven simulation
9	Jayadeva	Sequential Chaotic Annealing and its Application to Multilayer Channel Routing.	VLSI Design	1999	DBLP DOI BibTeX RDF
9	Vaughn Betz, Jonathan Rose	Effect of the prefabricated routing track distribution on FPGA area-efficiency.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
9	Bongjin Jung, Wayne P. Burleson	Efficient VLSI for Lempel-Ziv compression in wireless data communication networks.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
9	Haluk Konuk, F. Joel Ferguson	Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko	VLSI/PCB placement with obstacles based on sequence pair.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Chris C. N. Chu, Martin D. F. Wong	A matrix synthesis approach to thermal placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Mladen Berekovic, Peter Pirsch, Johannes Kneip	An Algorithm-Hardware-System Approach to VLIW Multimedia Processors.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
9	Christian Ebner	Efficiency evaluation of a time-triggered architecture for vehicle body-electronics.	ECRTS	1998	DBLP DOI BibTeX RDF
9	Atsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami	More Wires and Fewer LUTs: A Design Methodology for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
9	Jian Li 0061, Rajesh K. Gupta 0001	An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions.	DATE	1998	DBLP DOI BibTeX RDF
9	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma	Interconnect Tuning Strategies for High-Performance Ics.	DATE	1998	DBLP DOI BibTeX RDF
9	Keiki Takadama, Shinichi Nakasuka, Takao Terano	Amalyzing the Roles of Problem Solving and Learning in Organizational-Learning Oriented Classifier System.	PRICAI	1998	DBLP DOI BibTeX RDF	print circuit board design, multiagent system, learning classifier system, organizational learning
9	Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl	Analysis, reduction and avoidance of crosstalk on VLSI chips.	ISPD	1998	DBLP DOI BibTeX RDF
9	Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley	Device-level early floorplanning algorithms for RF circuits.	ISPD	1998	DBLP DOI BibTeX RDF
9	Eric Kusse, Jan M. Rabaey	Low-energy embedded FPGA structures.	ISLPED	1998	DBLP DOI BibTeX RDF	dual voltage, pass-transistors, FPGAs, interconnect network, embedded, power, low energy, low swing
9	Hui Zhang 0008, Jan M. Rabaey	Low-swing interconnect interface circuits.	ISLPED	1998	DBLP DOI BibTeX RDF
9	Peter Glösekötter, Andreas Kanstein, Stefan Jung, Karl Goser	Implementation of a RBF Network Based on Possibilistic Reasoning.	EUROMICRO	1998	DBLP DOI BibTeX RDF
9	Federico Silla, Manuel P. Malumbres, José Duato, Donglai Dai, Dhabaleswar K. Panda 0001	Impact of Adaptivity on the Behaviour of Networks of Workstations under Bursty Traffic.	ICPP	1998	DBLP DOI BibTeX RDF
9	Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici	Built-in self-test of FPGA interconnect.	ITC	1998	DBLP DOI BibTeX RDF
9	Daniel R. Knebel, Pia N. Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika	Diagnosis and characterization of timing-related defects by time-dependent light emission.	ITC	1998	DBLP DOI BibTeX RDF
9	Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi	In-Place Power Optimization for LUT-Based FPGAs.	DAC	1998	DBLP DOI BibTeX RDF
9	Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah	Congestion Driven Quadratic Placement.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
9	Chien-Kuo V. Tien, Kelvin Lewis, Hans J. Greub, Tom Tsen, John F. McDonald 0001	Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
9	Chih-Chang Lin, Malgorzata Marek-Sadowska	On designing universal logic blocks and their application to FPGA design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Ralf Schmid, Reinhold Schmitt, Matthias Brunner, Oliver Gessner, Matthias Sturm	Electron Beam Probing - A Solution for MCM Test and Failure Analysis.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	electron-beam testing, short, open, MCM, printed circuit board
9	Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch	An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
9	Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss	A Clock Methodology for High-Performance Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
9	Federico Silla, Manuel P. Malumbres, Antonio Robles, Pedro López 0001, José Duato	Efficient Adaptive Routing in Networks of Workstations with Irregular Topology.	CANPC	1997	DBLP DOI BibTeX RDF
9	Woo-Jong Hahn, Kee-Wook Rim, Soo-Won Kim	SPAX: A New Parallel Processing System for Commercial Application.	IPPS	1997	DBLP DOI BibTeX RDF	SPAX, commercial applications, Xcent-Net, 2.67 Gbyte/s, scalability, parallel architectures, bandwidth, SMP, hierarchical network, parallel processing system
9	Jack Greenbaum, Michael Baxter	Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing.	FCCM	1997	DBLP DOI BibTeX RDF
9	Mohankumar Guruswamy, Martin D. F. Wong	Echelon: a multilayer detailed area router.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani	VLSI module placement based on rectangle-packing by the sequence-pair.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Post-processing of clock trees via wiresizing and buffering for robust design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano	A Consistent Scan Design System for Large-Scale ASICs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
9	David A. Eckhardt, Peter Steenkiste	Measurement and Analysis of the Error Characteristics of an In-Building Wireless Network.	SIGCOMM	1996	DBLP DOI BibTeX RDF	Ethernet
9	Henk L. Muller, Paul W. A. Stallard, David H. D. Warren	Implementing the Data Diffusion Machine Using Crossbar Routers.	IPPS	1996	DBLP DOI BibTeX RDF	multithreading, multitasking, COMA, virtual shared memory
9	Daniel Brand, Chandramouli Visweswariah	Inaccuracies in power estimation during logic synthesis.	ICCAD	1996	DBLP DOI BibTeX RDF	glitch power, simulation, logic synthesis, power estimation, power optimization
9	Ki-Seok Chung, Rajesh K. Gupta 0001, C. L. Liu 0001	An algorithm for synthesis of system-level interface circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	System-Level Design Issues, Optimization, Algorithm, Interface Synthesis
9	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
9	Sandip Das 0001, Bhargab B. Bhattacharya	Channel routing in Manhattan-diagonal model.	VLSI Design	1996	DBLP DOI BibTeX RDF	Manhattan-diagonal model, layout grid, cyclic vertical constraints, low via count, reduced wire length, VLSI, network routing, circuit layout CAD, VLSI layout, integrated circuit layout, channel routing, output-sensitive algorithm
9	Vojin G. Oklobdzija, David Villeger	Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
9	Jun Dong Cho, Majid Sarrafzadeh	A buffer distribution algorithm for high-performance clock net optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
9	Dale D. Harman, Gang Huang, Gi-Hong Im, Mai-Huong Nguyen, Jean-Jacques Werner, Michael K. Wong	Local Distribution for Interactive Multimedia TV to the Home.	IEEE Multim.	1995	DBLP DOI BibTeX RDF	carrierless AM/PM (CAP), residential networking, fiber-to-the-curb, unshielded twisted pair, switched digital video, digital local distribution technology, ATM, interactive TV
9	Heinrich J. Stüttgen	Network Evolution and Multimedia Communication.	IEEE Multim.	1995	DBLP DOI BibTeX RDF
9	Jason Cong, Kwok-Shing Leung	Optimal wiresizing under Elmore delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin	TRACER-fpga: a router for RAM-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato	Min-cut placement with global objective functions for large scale sea-of-gates arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Wing Ning Li	The complexity of segmented channel routing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Jacob Savir	Shrinking wide compressors [BIST].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	H. Zhou, Howard C. Card, Gregory E. Bridges	Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing high-speed circuits, cellular automata, pseudorandom number generation, GaAs
9	Larry McMurchie, Carl Ebeling	PathFinder: A Negotiation-based Performance-driven Router for FPGAs.	FPGA	1995	DBLP DOI BibTeX RDF
9	Gensoh Matsubara, Nobuhiro Ide, Haruyuki Tago, Seigo Suzuki, Nobuyuki Goto	30-ns 55-b Radix 2 Division and Square Root Using a Self-Timed Circuit.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	simulation, CMOS, division, square root, self-timed, SRT, on-the-fly
9	Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani	Rectangle-packing-based module placement.	ICCAD	1995	DBLP DOI BibTeX RDF
9	Massoud Pedram, Bahman S. Nobandegani, Bryan Preas	Design and analysis of segmented routing channels for row-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Jeff Griffith, Gabriel Robins, Jeffrey S. Salowe, Tongtong Zhang	Closing the gap: near-optimal Steiner trees in polynomial time.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Shekar Rao, Bert Haskell, Ian Yee	Trade-off analysis on cost and manufacturing technology of an electronic product: Case study.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	analysis of PCB (printed circuit boards), Benchmarking, trade-off, redesign
9	Vojin G. Oklobdzija, David Villeger, Thierry Soulas	An integrated multiplier for complex numbers.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
9	Kazuhiro Takahashi, Kazuo Nakajima, Masayuki Terai, Koji Sato	Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin	Universal logic gate for FPGA design.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Raja Venkateswaran, Pinaki Mazumder	Coprocessor design for multilayer surface-mounted PCB routing.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
9	D. Sreenivasa Rao, Fadi J. Kurdahi	Hierarchical design space exploration for a class of digital systems.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
9	Stella N. Batalama, Dimitrios A. Pados, Theodore S. Papatheodorou	A heuristic single-row router minimizing interstreet crossings.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Robert Cypher, C. Bernard Shung	Generalized trace-back techniques for survivor memory management in the Viterbi algorithm.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF	trace-back, survivor memory, VLSI area requirements, Viterbi algorithm