Search results for "BDD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Gerd Behrmann, Kim Guldstrand Larsen, Justin Pearson, Carsten Weise, Wang Yi 0001	Efficient Timed Reachability Analysis Using Clock Difference Diagrams.	CAV	1999	DBLP DOI BibTeX RDF
9	Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer	Computing Timed Transition Relations for Sequential Cycle-Based Simulation.	DATE	1999	DBLP DOI BibTeX RDF
9	Michele Favalli, Cecilia Metra	On the Design of Self-Checking Functional Units Based on Shannon Circuits.	DATE	1999	DBLP DOI BibTeX RDF
9	João Marques-Silva 0001, Thomas Glass	Combinational Equivalence Checking Using Satisfiability and Recursive Learning.	DATE	1999	DBLP DOI BibTeX RDF	Boolean Satisfiability, Recursive Learning, Combinational Equivalence Checking
9	Frank Reffel, Stefan Edelkamp	Error Detection with Directed Symbolic Model Checking.	World Congress on Formal Methods	1999	DBLP DOI BibTeX RDF
9	Parosh Aziz Abdulla, Bengt Jonsson 0001	On the Existence of Network Invariants for Verifying Parameterized Systems.	Correct System Design	1999	DBLP DOI BibTeX RDF
9	Dirk W. Hoffmann, Thomas Kropf	Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction.	CHARME	1999	DBLP DOI BibTeX RDF	Automatic error correction, design error diagnosis, formal methods, equivalence checking
9	Nina Amla, E. Allen Emerson, Kedar S. Namjoshi	Efficient Decompositional Model Checking for Regular Timing Diagrams.	CHARME	1999	DBLP DOI BibTeX RDF
9	Hüsnü Yenigün, Vladimir Levin, Doron A. Peled, Peter A. Beerel	Hazard-Freedom Checking in Speed-Independent Systems.	CHARME	1999	DBLP DOI BibTeX RDF
9	Jules P. Bergmann, Mark Horowitz	Improving coverage analysis and test generation for large designs.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Hiroyuki Higuchi, Fabio Somenzi	Lazy group sifting for efficient symbolic state traversal of FSMs.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Sani R. Nassif, Tuyen V. Nguyen	SOI technology and tools (abstract).	ICCAD	1999	DBLP BibTeX RDF
9	Aiguo Xie, Peter A. Beerel	Implicit enumeration of strongly connected components.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Kavita Ravi, Fabio Somenzi	Efficient Fixpoint Computation for Invariant Checking.	ICCD	1999	DBLP DOI BibTeX RDF
9	Justin E. Harlow III, Franc Brglez	Mirror, mirror, on the wall...is the new release any different at all? [BDDs].	ISCAS (6)	1999	DBLP DOI BibTeX RDF
9	Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs	Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits.	VTS	1999	DBLP DOI BibTeX RDF
9	David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska	A hybrid methodology for switching activities estimation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
9	Ragavan Manian, Joanne Bechta Dugan, David Coppit, Kevin J. Sullivan	Combining Various Solution Techniques for Dynamic Fault Tree Analysis of Computer Systems.	HASE	1998	DBLP DOI BibTeX RDF
9	Takayuki Fujinaga, Kousuke Moriwaki, Nobuhiro Inuzuka, Hidenori Itoh	Evolving Cooperative Actions Among Heterogeneous Agents by an Evolutionary Programming Method.	SEAL	1998	DBLP DOI BibTeX RDF
9	Friedrich W. von Henke, Stephan Pfab, Holger Pfeifer, Harald Rueß	Case Studies in Meta-Level Theorem Proving.	TPHOLs	1998	DBLP DOI BibTeX RDF
9	Enric Pastor, Jordi Cortadella	Efficient Encoding Schemes for Symbolic Analysis of Petri Nets.	DATE	1998	DBLP DOI BibTeX RDF	Petri nets, BDDs, symbolic analysis
9	Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton	Combinational Verification based on High-Level Functional Specifications.	DATE	1998	DBLP DOI BibTeX RDF	Combinational verification, Domain transformations, BDDs
9	Radu Negulescu	Event-Driven Verification of Switch-Level Correctness Concerns.	ACSD	1998	DBLP DOI BibTeX RDF	switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces
9	Tevfik Bultan, Richard Gerber 0001, Christopher League	Verifying Systems with Integer Constraints and Boolean Predicates: A Composite Approach.	ISSTA	1998	DBLP DOI BibTeX RDF
9	Jan Behrens, Stephan Waack	Equivalence Test and Ordering Transformation for Parity-OBDDs of Different Variable Ordering.	STACS	1998	DBLP DOI BibTeX RDF
9	Apostolos A. Kountouris, Christophe Wolinski	Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing.	EUROMICRO	1998	DBLP DOI BibTeX RDF
9	Sela Mador-Haim, Limor Fix	Input Elimination and Abstraction in Model Checking.	FMCAD	1998	DBLP DOI BibTeX RDF
9	Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz	Hybrid Techniques for Fast Functional Simulation.	DAC	1998	DBLP DOI BibTeX RDF	ASIC verification, simulation, emulation
9	Aiguo Xie, Peter A. Beerel	Efficient State Classification of Finite State Markov Chains.	DAC	1998	DBLP DOI BibTeX RDF	model checking, verification, guided search
9	Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos	Automatic verification of implementations of large circuits against HDL specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal	Redundancy removal and test generation for circuits with non-Boolean primitives.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	M. Hira, Dipankar Sarkar 0001	Verification of Tempura specification of sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Maurizio Damiani	The state reduction of nondeterministic finite-state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Gianpiero Cabodi, Paolo Camurati	Symbolic FSM traversals based on the transition relation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Armin Biere	µcke - Efficient µ-Calculus Model Checking.	CAV	1997	DBLP DOI BibTeX RDF
9	Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani	Partial-Order Reduction in Symbolic State Space Exploration.	CAV	1997	DBLP DOI BibTeX RDF
9	Yonit Kesten, Oded Maler, Monica Marcus, Amir Pnueli, Elad Shahar	Symbolic Model Checking with Rich ssertional Languages.	CAV	1997	DBLP DOI BibTeX RDF
9	David Cyrluk, M. Oliver Möller, Harald Rueß	An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors.	CAV	1997	DBLP DOI BibTeX RDF
9	Marius Bozga, Oded Maler, Amir Pnueli, Sergio Yovine	Some Progress in the Symbolic Verification of Timed Automata.	CAV	1997	DBLP DOI BibTeX RDF
9	Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi	Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.	ED&TC	1997	DBLP DOI BibTeX RDF
9	MoonBae Song, Hoon Chang	A variable reordering method for fast optimization of binary decision diagrams.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	variable reordering, distributed reordering algorithm, dynamic variable ordering, window permutation, optimization, binary decision diagrams, computation time, circuit optimisation
9	Christoph Scholl 0001, Rolf Drechsler, Bernd Becker 0001	Functional simulation using binary decision diagrams.	ICCAD	1997	DBLP DOI BibTeX RDF	Binary Decision Diagrams, Functional simulation
9	Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello	Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
9	Nils Klarlund	Mona & Fido: The Logic-Automaton Connection in Practice.	CSL	1997	DBLP DOI BibTeX RDF
9	Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley	Formal Verification of FIRE: A Case Study.	DAC	1997	DBLP DOI BibTeX RDF
9	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	An Efficient Assertion Checker for Combinational Properties.	DAC	1997	DBLP DOI BibTeX RDF
9	Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi	Markovian analysis of large finite state machines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani	Scheduling and control generation with environmental constraints based on automata representations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Masahiro Fujita	Verification of Arithmetic Circuits by Comparing Two Similar Circuits.	CAV	1996	DBLP DOI BibTeX RDF
9	Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten	A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings.	Application and Theory of Petri Nets	1996	DBLP DOI BibTeX RDF
9	Krzysztof Bilinski, Erik L. Dagless	High Level Synthesis of Synchronous Parallel Controllers.	Application and Theory of Petri Nets	1996	DBLP DOI BibTeX RDF
9	Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi	Formal Verification Of Self-Testing Properties Of Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
9	Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet	A symbolic simulation approach in resolving signals' correlation.	Annual Simulation Symposium	1996	DBLP DOI BibTeX RDF	signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools
9	Scott Woods, Giorgio Casinovi	Efficient solution of systems of Boolean equations.	ICCAD	1996	DBLP DOI BibTeX RDF	Boolean equations solution, gate-level logic simulation
9	Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose	CTL model checking based on forward state traversal.	ICCAD	1996	DBLP DOI BibTeX RDF	state traversal, partitioned transition relation, model checking, formal verification, CTL
9	Rajeev K. Ranjan 0001, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Binary decision diagrams on network of workstation.	ICCD	1996	DBLP DOI BibTeX RDF	memory resources, breadth-first technique, verification, Boolean functions, synthesis, binary decision diagram, network of workstations
9	Mitchell A. Thornton, V. S. S. Nair	Efficient calculation of spectral coefficients and their applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Bill Lin 0001, Srinivas Devadas	Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Henrik Reif Andersen, Bart Vergauwen	Efficient Checking of Behavioural Relations and Modal Assertions using Fixed-Point Inversion.	CAV	1995	DBLP DOI BibTeX RDF
9	S. Rajan, Natarajan Shankar, Mandayam K. Srivas	An Integration of Model Checking with Automated Proof Checking.	CAV	1995	DBLP DOI BibTeX RDF
9	Kenneth L. McMillan	Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings.	CAV	1995	DBLP DOI BibTeX RDF
9	Randal E. Bryant	Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract).	CAV	1995	DBLP DOI BibTeX RDF
9	Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda	An improved data parallel algorithm for Boolean function manipulation using BDDs.	PDP	1995	DBLP DOI BibTeX RDF	Boolean function manipulation, parallel algorithms, parallel algorithm, Boolean functions, Binary Decision Diagrams, BDDs, SIMD architectures, CPU time, data parallel algorithm
9	Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken	Efficient orthonormality testing for synthesis with pass-transistor selectors.	ICCAD	1995	DBLP DOI BibTeX RDF
9	Edmund M. Clarke, Masahiro Fujita, Xudong Zhao 0005	Hybrid decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	MTBDDs, arithmetic circuits verification, boolean vectors, hybrid decision diagrams, linear expressions, multi-terminal binary decision diagrams, symbolic model checking algorithms, computational complexity, time complexity, digital arithmetic, binary decision diagrams, circuit analysis computing, integers, BMDs
9	David Cyrluk, Mandayam K. Srivas	Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification.	ICCD	1995	DBLP DOI BibTeX RDF	industrial hardware verification, industrial verification, formal verification, logic testing, theorem proving, theorem prover, hardware verification
9	Srimat T. Chakradhar, Steven G. Rothweiler	Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives.	VTS	1995	DBLP DOI BibTeX RDF
9	Andrew Seawright, Forrest Brewer	Clairvoyant: a synthesis system for production-based specification.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
9	Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill	Symbolic model checking for sequential circuit verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Ted Stanion, Carl Sechen	Boolean division and factorization using binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Edmund M. Clarke	Automatic Verification of Finite-state Concurrent Systems.	Application and Theory of Petri Nets	1994	DBLP DOI BibTeX RDF
9	Mikko Tiusanen	Symbolic, Symmetry, and Stubborn Set Searches.	Application and Theory of Petri Nets	1994	DBLP DOI BibTeX RDF
9	Christoph Meinel, Anna Slobodová	On the Complexity of Constructing Optimal Ordered Binary Decision Diagrams.	MFCS	1994	DBLP DOI BibTeX RDF
9	Bill Lin 0001, Srinivas Devadas	Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Kenneth Y. Yun, Bill Lin 0001, David L. Dill, Srinivas Devadas	Performance-driven synthesis of asynchronous controllers.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton	A redesign technique for combinational circuits based on gate reconnections.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Susanne Graf, Claire Loiseaux	A Tool for Symbolic Program Verification and Abstration.	CAV	1993	DBLP DOI BibTeX RDF
9	Edmund M. Clarke, Thomas Filkorn, Somesh Jha	Exploiting Symmetry In Temporal Logic Model Checking.	CAV	1993	DBLP DOI BibTeX RDF
9	Felice Balarin, Alberto L. Sangiovanni-Vincentelli	An Iterative Approach to Language Containment.	CAV	1993	DBLP DOI BibTeX RDF
9	Robert P. Kurshan, Leslie Lamport	Verification of a Multiplier: 64 Bits and Beyond.	CAV	1993	DBLP DOI BibTeX RDF
9	Farn Wang, Aloysius K. Mok, E. Allen Emerson	Symbolic Model Checking for Distributed Real-Time Systems.	FME	1993	DBLP DOI BibTeX RDF
9	Carl Pixley	A theory and implementation of sequential hardware equivalence.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Reinhard Enders, Thomas Filkorn, Dirk Taubner	Generating BDDs for Symbolic Model Checking in CCS.	CAV	1991	DBLP DOI BibTeX RDF
9	Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill	Sequential Circuit Verification Using Symbolic Model Checking.	DAC	1990	DBLP DOI BibTeX RDF