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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 664 occurrences of 364 keywords
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Results
Found 985 publication records. Showing 985 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
9 | Gerd Behrmann, Kim Guldstrand Larsen, Justin Pearson, Carsten Weise, Wang Yi 0001 |
Efficient Timed Reachability Analysis Using Clock Difference Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 341-353, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Gianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer |
Computing Timed Transition Relations for Sequential Cycle-Based Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 8-12, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Michele Favalli, Cecilia Metra |
On the Design of Self-Checking Functional Units Based on Shannon Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 368-375, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | João Marques-Silva 0001, Thomas Glass |
Combinational Equivalence Checking Using Satisfiability and Recursive Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 145-149, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Boolean Satisfiability, Recursive Learning, Combinational Equivalence Checking |
9 | Frank Reffel, Stefan Edelkamp |
Error Detection with Directed Symbolic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
World Congress on Formal Methods ![In: FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume I, pp. 195-211, 1999, Springer, 3-540-66587-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Parosh Aziz Abdulla, Bengt Jonsson 0001 |
On the Existence of Network Invariants for Verifying Parameterized Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Correct System Design ![In: Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel), pp. 180-197, 1999, Springer, 3-540-66624-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Dirk W. Hoffmann, Thomas Kropf |
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 157-171, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Automatic error correction, design error diagnosis, formal methods, equivalence checking |
9 | Nina Amla, E. Allen Emerson, Kedar S. Namjoshi |
Efficient Decompositional Model Checking for Regular Timing Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 67-81, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Hüsnü Yenigün, Vladimir Levin, Doron A. Peled, Peter A. Beerel |
Hazard-Freedom Checking in Speed-Independent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 317-320, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Jules P. Bergmann, Mark Horowitz |
Improving coverage analysis and test generation for large designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 580-583, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Hiroyuki Higuchi, Fabio Somenzi |
Lazy group sifting for efficient symbolic state traversal of FSMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 45-49, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Sani R. Nassif, Tuyen V. Nguyen |
SOI technology and tools (abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 459, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP BibTeX RDF |
|
9 | Aiguo Xie, Peter A. Beerel |
Implicit enumeration of strongly connected components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 37-40, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Kavita Ravi, Fabio Somenzi |
Efficient Fixpoint Computation for Invariant Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 467-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Justin E. Harlow III, Franc Brglez |
Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 452-455, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs |
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 58-63, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska |
A hybrid methodology for switching activities estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4), pp. 357-366, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee |
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(4), pp. 600-625, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states |
9 | Ragavan Manian, Joanne Bechta Dugan, David Coppit, Kevin J. Sullivan |
Combining Various Solution Techniques for Dynamic Fault Tree Analysis of Computer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 3rd IEEE International Symposium on High-Assurance Systems Engineering (HASE '98), 13-14 November 1998, Washington, D.C, USA, Proceedings, pp. 21-28, 1998, IEEE Computer Society, 0-8186-9221-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Takayuki Fujinaga, Kousuke Moriwaki, Nobuhiro Inuzuka, Hidenori Itoh |
Evolving Cooperative Actions Among Heterogeneous Agents by an Evolutionary Programming Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEAL ![In: Simulated Evolution and Learning, Second Asia-Pacific Conference on Simulated Evolution and Learning, SEAL'98, Canberra, Australia, November 24-27 1998, Selected Papers, pp. 231-239, 1998, Springer, 3-540-65907-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Friedrich W. von Henke, Stephan Pfab, Holger Pfeifer, Harald Rueß |
Case Studies in Meta-Level Theorem Proving. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 11th International Conference, TPHOLs'98, Canberra, Australia, September 27 - October 1, 1998, Proceedings, pp. 461-478, 1998, Springer, 3-540-64987-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Enric Pastor, Jordi Cortadella |
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 790-795, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Petri nets, BDDs, symbolic analysis |
9 | Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton |
Combinational Verification based on High-Level Functional Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 803-808, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Combinational verification, Domain transformations, BDDs |
9 | Radu Negulescu |
Event-Driven Verification of Switch-Level Correctness Concerns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: 1st International Conference on Application of Concurrency to System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan, pp. 213-223, 1998, IEEE Computer Society, 0-8186-8350-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces |
9 | Tevfik Bultan, Richard Gerber 0001, Christopher League |
Verifying Systems with Integer Constraints and Boolean Predicates: A Composite Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSTA ![In: Proceedings of ACM SIGSOFT International Symposium on Software Testing and Analysis, ISSTA 1998, Clearwater Beach, Florida, USA, March 2-5, 1998, pp. 113-123, 1998, ACM, 0-89791-971-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Jan Behrens, Stephan Waack |
Equivalence Test and Ordering Transformation for Parity-OBDDs of Different Variable Ordering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 98, 15th Annual Symposium on Theoretical Aspects of Computer Science, Paris, France, February 25-27, 1998, Proceedings, pp. 227-237, 1998, Springer, 3-540-64230-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Apostolos A. Kountouris, Christophe Wolinski |
Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10313-10316, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Sela Mador-Haim, Limor Fix |
Input Elimination and Abstraction in Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Second International Conference, FMCAD '98, Palo Alto, California, USA, November 4-6, 1998, Proceedings, pp. 304-320, 1998, Springer, 3-540-65191-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz |
Hybrid Techniques for Fast Functional Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 664-667, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
ASIC verification, simulation, emulation |
9 | Aiguo Xie, Peter A. Beerel |
Efficient State Classification of Finite State Markov Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 605-610, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
model checking, verification, guided search |
9 | Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos |
Automatic verification of implementations of large circuits against HDL specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 217-228, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal |
Redundancy removal and test generation for circuits with non-Boolean primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1370-1377, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | M. Hira, Dipankar Sarkar 0001 |
Verification of Tempura specification of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4), pp. 362-375, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Maurizio Damiani |
The state reduction of nondeterministic finite-state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1278-1291, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Gianpiero Cabodi, Paolo Camurati |
Symbolic FSM traversals based on the transition relation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5), pp. 448-457, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Armin Biere |
µcke - Efficient µ-Calculus Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 468-471, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani |
Partial-Order Reduction in Symbolic State Space Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 340-351, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Yonit Kesten, Oded Maler, Monica Marcus, Amir Pnueli, Elad Shahar |
Symbolic Model Checking with Rich ssertional Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 424-435, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | David Cyrluk, M. Oliver Möller, Harald Rueß |
An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 60-71, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Marius Bozga, Oded Maler, Amir Pnueli, Sergio Yovine |
Some Progress in the Symbolic Verification of Timed Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings, pp. 179-190, 1997, Springer, 3-540-63166-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 514-520, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | MoonBae Song, Hoon Chang |
A variable reordering method for fast optimization of binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 228-233, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
variable reordering, distributed reordering algorithm, dynamic variable ordering, window permutation, optimization, binary decision diagrams, computation time, circuit optimisation |
9 | Christoph Scholl 0001, Rolf Drechsler, Bernd Becker 0001 |
Functional simulation using binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 8-12, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Binary Decision Diagrams, Functional simulation |
9 | Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello |
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA, pp. 70-, 1997, IEEE Computer Society, 0-8186-7904-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Nils Klarlund |
Mona & Fido: The Logic-Automaton Connection in Practice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSL ![In: Computer Science Logic, 11th International Workshop, CSL '97, Annual Conference of the EACSL, Aarhus, Denmark, August 23-29, 1997, Selected Papers, pp. 311-326, 1997, Springer, 3-540-64570-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley |
Formal Verification of FIRE: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 173-177, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee |
An Efficient Assertion Checker for Combinational Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 734-739, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi |
Markovian analysis of large finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12), pp. 1479-1493, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Jerry Chih-Yuan Yang, Giovanni De Micheli, Maurizio Damiani |
Scheduling and control generation with environmental constraints based on automata representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 166-183, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Masahiro Fujita |
Verification of Arithmetic Circuits by Comparing Two Similar Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 8th International Conference, CAV '96, New Brunswick, NJ, USA, July 31 - August 3, 1996, Proceedings, pp. 159-168, 1996, Springer, 3-540-61474-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, Sergei Ten |
A Structural Approach for the Analysis of Petri Nets by Reduced Unfoldings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1996, 17th International Conference, Osaka, Japan, June 24-28, 1996, Proceedings, pp. 346-365, 1996, Springer, 3-540-61363-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Krzysztof Bilinski, Erik L. Dagless |
High Level Synthesis of Synchronous Parallel Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1996, 17th International Conference, Osaka, Japan, June 24-28, 1996, Proceedings, pp. 93-112, 1996, Springer, 3-540-61363-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi |
Formal Verification Of Self-Testing Properties Of Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 119-122, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code |
9 | Julien Dunoyer, Nizar Abdallah, Pirouz Bazargan-Sabet |
A symbolic simulation approach in resolving signals' correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 29st Annual Simulation Symposium (SS '96), April 8-11, 1996, New Orleans, LA, USA, pp. 203-211, 1996, IEEE Computer Society, 0-8186-7432-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
signal resolution, signal correlation resolution, symbolic simulation approach, evaluation package, signal transition density, specification levels, first order clue, independent inputs, binary decision diagram concept, algorithms, VLSI, probability, logic CAD, digital simulation, design process, decision theory, circuit analysis computing, integrated circuit design, circuit CAD, digital circuits, subroutines, symbol manipulation, power dissipation, correlation methods, digital integrated circuits, signal probability, probabilistic approach, synthesis tools |
9 | Scott Woods, Giorgio Casinovi |
Efficient solution of systems of Boolean equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 542-546, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Boolean equations solution, gate-level logic simulation |
9 | Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose |
CTL model checking based on forward state traversal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 82-87, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
state traversal, partitioned transition relation, model checking, formal verification, CTL |
9 | Rajeev K. Ranjan 0001, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Binary decision diagrams on network of workstation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 358-364, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
memory resources, breadth-first technique, verification, Boolean functions, synthesis, binary decision diagram, network of workstations |
9 | Mitchell A. Thornton, V. S. S. Nair |
Efficient calculation of spectral coefficients and their applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11), pp. 1328-1341, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Bill Lin 0001, Srinivas Devadas |
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 974-985, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Henrik Reif Andersen, Bart Vergauwen |
Efficient Checking of Behavioural Relations and Modal Assertions using Fixed-Point Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 142-154, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | S. Rajan, Natarajan Shankar, Mandayam K. Srivas |
An Integration of Model Checking with Automated Proof Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 84-97, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Kenneth L. McMillan |
Trace Theoretic Verification of Asynchronous Circuits Using Unfoldings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 180-195, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Randal E. Bryant |
Multipliers and Dividers: Insights on Arithmetic Circuits Verification (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 1-3, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda |
An improved data parallel algorithm for Boolean function manipulation using BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 33-41, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Boolean function manipulation, parallel algorithms, parallel algorithm, Boolean functions, Binary Decision Diagrams, BDDs, SIMD architectures, CPU time, data parallel algorithm |
9 | Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken |
Efficient orthonormality testing for synthesis with pass-transistor selectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 256-263, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Edmund M. Clarke, Masahiro Fujita, Xudong Zhao 0005 |
Hybrid decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 159-163, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MTBDDs, arithmetic circuits verification, boolean vectors, hybrid decision diagrams, linear expressions, multi-terminal binary decision diagrams, symbolic model checking algorithms, computational complexity, time complexity, digital arithmetic, binary decision diagrams, circuit analysis computing, integers, BMDs |
9 | David Cyrluk, Mandayam K. Srivas |
Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 538-544, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
industrial hardware verification, industrial verification, formal verification, logic testing, theorem proving, theorem prover, hardware verification |
9 | Srimat T. Chakradhar, Steven G. Rothweiler |
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 12-19, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Andrew Seawright, Forrest Brewer |
Clairvoyant: a synthesis system for production-based specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(2), pp. 172-185, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill |
Symbolic model checking for sequential circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4), pp. 401-424, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Ted Stanion, Carl Sechen |
Boolean division and factorization using binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9), pp. 1179-1184, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Edmund M. Clarke |
Automatic Verification of Finite-state Concurrent Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1994, 15th International Conference, Zaragoza, Spain, June 20-24, 1994, Proceedings, pp. 1, 1994, Springer, 3-540-58152-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Mikko Tiusanen |
Symbolic, Symmetry, and Stubborn Set Searches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Application and Theory of Petri Nets ![In: Application and Theory of Petri Nets 1994, 15th International Conference, Zaragoza, Spain, June 20-24, 1994, Proceedings, pp. 511-530, 1994, Springer, 3-540-58152-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Christoph Meinel, Anna Slobodová |
On the Complexity of Constructing Optimal Ordered Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MFCS ![In: Mathematical Foundations of Computer Science 1994, 19th International Symposium, MFCS'94, Kosice, Slovakia, August 22 - 26, 1994, Proceedings, pp. 515-524, 1994, Springer, 3-540-58338-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Bill Lin 0001, Srinivas Devadas |
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 542-549, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Kenneth Y. Yun, Bill Lin 0001, David L. Dill, Srinivas Devadas |
Performance-driven synthesis of asynchronous controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 550-557, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton |
A redesign technique for combinational circuits based on gate reconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 632-637, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Susanne Graf, Claire Loiseaux |
A Tool for Symbolic Program Verification and Abstration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 71-84, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Edmund M. Clarke, Thomas Filkorn, Somesh Jha |
Exploiting Symmetry In Temporal Logic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 450-462, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Felice Balarin, Alberto L. Sangiovanni-Vincentelli |
An Iterative Approach to Language Containment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 29-40, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Robert P. Kurshan, Leslie Lamport |
Verification of a Multiplier: 64 Bits and Beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 166-179, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Farn Wang, Aloysius K. Mok, E. Allen Emerson |
Symbolic Model Checking for Distributed Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FME ![In: FME '93: Industrial-Strength Formal Methods, First International Symposium of Formal Methods Europe, Odense, Denmark, April 19-23, 1993, Proceedings, pp. 632-651, 1993, Springer, 3-540-56662-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Carl Pixley |
A theory and implementation of sequential hardware equivalence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12), pp. 1469-1478, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
9 | Reinhard Enders, Thomas Filkorn, Dirk Taubner |
Generating BDDs for Symbolic Model Checking in CCS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 3rd International Workshop, CAV '91, Aalborg, Denmark, July, 1-4, 1991, Proceedings, pp. 203-213, 1991, Springer, 3-540-55179-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
9 | Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill |
Sequential Circuit Verification Using Symbolic Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 46-51, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
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