Search results for "ESSCIRC"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong	A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Shunli Ma, Hao Yu 0001, Yang Shang, Wei Meng Lim, Junyan Ren	A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Peng Cong, Piyush Karande, Jonathan Landes, Rob Corey, Scott Stanslaski, Wesley Santa, Randy Jensen, Forrest Pape, Dan Moran, Tim Denison	A 32-channel modular bi-directional neural interface system with embedded DSP for closed-loop operation.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Seongwook Park, Gyeonghoon Kim, Junyoung Park 0002, Hoi-Jun Yoo	A 1.5nJ/pixel super-resolution enhanced FAST corner detection processor for high accuracy AR.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Peng Zhu, Xinpeng Xing, Georges G. E. Gielen	A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Shahbaz Abbasi, Ayman Shabra	1.8GHz 3rd order lowpass filter with programmable gain in 180nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Hooman Darabi, David Murphy, Mohyee Mikhemar, Ahmad Mirzaei	Blocker tolerant software defined receivers.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Aritra Banerjee, Rahmi Hezar, Lei Ding 0001, Nathan Schemm, Baher Haroun	A 29.5 dBm class-E outphasing RF power amplifier with performance enhancement circuits in 45nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Quan Pan 0002, Yipeng Wang 0003, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki, Patrick Chiang 0001, C. Patrick Yue	A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Abdelali El Amraoui, Marc Bocquet, F. Barros, Jean-Michel Portal, M. Charbonneau, Stéphanie Jacob, Jacqueline Bablet, Mohamed Benwadih, Vincent Fischer, Romain Coppard, R. Gwoziecky	Printed complementary organic thin film transistors based decoder for ferroelectric memory.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Debasish Behera, Nagendra Krishnapura	A 2-channel 1MHz BW, 80.5 dB DR ADC using a DS modulator and zero-ISI filter.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Chul Kim, Sohmyung Ha, Chris M. Thomas, Siddharth Joshi, Jongkil Park, Lawrence E. Larson, Gert Cauwenberghs	A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Pyoungwon Park, Kofi A. A. Makinwa, David Ruffieux	A resistor-based temperature sensor for a real time clock with ±2ppm frequency stability.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Greg Atwood, Scott DeBoer, Kirk Prall, Linda Somerville	A semiconductor memory development and manufacturing perspective.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Juergen Wittmann, Thoralf Rosahl, Bernhard Wicht	A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Yan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins	An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marco Garampazzi, Paulo M. Mendes, Nicola Codega, Danilo Manstretta, Rinaldo Castello	A 195.6dBc/Hz peak FoM P-N class-B oscillator with transformer-based tail filtering.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Yoshiaki Yoshihara, Hideaki Majima, Ryuichi Fujimoto	A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Kathleen Philips	Ultra Low Power short range radios: Covering the last mile of the IoT.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Hossein Kassiri, Arezu Bagheri, Nima Soltani, Karim Abdelhalim, Hamed Mazhab-Jafari, Muhammad Tariqus Salam, José Luis Pérez Velazquez, Roman Genov	Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Xicheng Jiang, Xinyu Yu, Fang Lin, Felix Cheung, Mike Inerfield, Kevin Li, Abhishek Kamath, Harsh Mehta, Jingbo Duan, Jing Yang, Gautham Krishnamurthy, Sumant Ranganathan, Darwin Cheung, Naga Radha Krishna Damaraju, Jianlong Chen, Dongtian Lu, Vinod Jayakumar, Leon Wang, Dario Soltesz, Hongwei Kong, Min Zhang, David Chang	A 28 nm analog and audio mixed-signal front end for 4G/LTE Cellular System-on-Chip.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx	A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Luca Ravezzi, Hamid Partovi, Dong Wang, C. Wang, Ronen Cohen, Matt Ashcraft, Alfred Yeung, Qawi Harvard, Russell Homer, John Ngai, Greg Favor	Clock and synchronization networks for a 3GHz 64bit ARMv8 8-core SoC.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Walter Snoeys	How chips helped discover the Higgs boson at CERN.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Piotr Maj, Pawel Grybos, Piotr Kmon, Robert Szczygiel	23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e- rms, 19 e- rms offset spread and 3% rms gain spread.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Nikola Krstajic, Richard Walker 0004, James Levitt, Simon P. Poland, David Day-Uei Li, Simon Ameer-Beg, Robert K. Henderson	A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensing.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Ugur Sonmez, Rui Quan, Fabio Sebastiano, Kofi A. A. Makinwa	A 0.008-mm2 area-optimized thermal-diffusivity-based temperature sensor in 160-nm CMOS for SoC thermal monitoring.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Jonas Lindstrand, Ivaylo Vasilev, Henrik Sjöland	A low band cellular terminal antenna impedance tuner in 130nm CMOS-SOI technology.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Achim Seidel, Marco Salvatore Costa, Joachim Joos, Bernhard Wicht	Bootstrap circuit with high-voltage charge storing for area efficient gate drivers in power management systems.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Myungjoon Choi, Inhee Lee, Tae-Kwang Jang, David T. Blaauw, Dennis Sylvester	A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx	A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Alaa Medra, Vito Giannini, Davide Guermandi, Piet Wambacq	A 79GHz variable gain low-noise amplifier and power amplifier in 28nm CMOS operating up to 125°C.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Takahiro Nakamura, Naoki Kitazawa, Kaoru Kohira, Hiroki Ishikuro	A SAW-less LTE transmitter with high-linearity modulator using BPF-based I/Q summing.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel	A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Assim Boukhayma, Jean-Pierre Rostaing, A. Mollard, Fabrice Guellec, Michele Benetti, Guillaume Ducournau, Jean-François Lampin, Antoine Dupret, Christian C. Enz, Michaël Tchagaspanian, J.-A. Nicolas	A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Abhirup Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda	A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Barend van Liempd, Jan Craninckx, R. Singh, Patrick Reynaert, Satoshi Malotaux, John R. Long	A dual-notch +27dBm Tx-power electrical-balance duplexer.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marcello De Matteis, Alessandro Pezzotta, Stefano D'Amico, Andrea Baschirotto	A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Jason Silver, Kannan A. Sankaragomathi, Brian P. Otis	An ultra-low-voltage all-digital PLL for energy harvesting applications.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Shayan Shahramian, Anthony Chan Carusone	A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Shiyuan Zheng, Howard C. Luong	A WCDMA/WLAN digital polar transmitter with low-noise ADPLL, wide-band PM/AM modulator and linearized PA in 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marco Vigilante, Patrick Reynaert	An E-Band low-noise Transformer-Coupled Quadrature VCO in 40 nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Enrico Temporiti, Gabriele Minoia, Matteo Repossi, Daniele Baldi, Andrea Ghilioni, Francesco Svelto	A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Paramartha Indirayanti, Tuba Ayhan, Marian Verhelst, Wim Dehaene, Patrick Reynaert	A 60GHz transmitter in 40nm CMOS achieving mm-precision for discrete-carrier localization.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Ali Fekri, Mohammad Reza Nabavi, Nikola Radeljic-Jakic, Zu-yao Chang, Michiel A. P. Pertijs, Stoyan N. Nihtianov	An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	André Mansano, Sumit Bagga, Wouter A. Serdijn	A 13.56/402 MHz autonomous wireless sensor node with -18.2 dBm sensitivity and temperature monitoring in 0.18 /im CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Abhishek Chowdhary, Alok Kaushik, Sajal Kumar Mandal, Sanjeev Chopra, Tapas Nandy, Vivek Uppal	A 8 Gbps blind oversampling CDR with frequency offset compensation over infinite burst.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Sanghyun Heo, Hyunggun Ma, Jae Joon Kim, Franklin Bien	Dynamic range enhanced readout circuit for a capacitive touch screen panel with current subtraction technique.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Rohan Sehgal, Frank M. L. van der Goes, Klaas Bult	A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Avishek Biswas, Yildiz Sinangil, Anantha P. Chandrakasan	A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Mohammed Abdulaziz, Markus Törmänen, Henrik Sjöland	A 4th order Gm-C filter with 10MHz bandwidth and 39dBm IIP3 in 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Michele Dini, Matteo Filippi, Aldo Romani, Marco Tartagni, Valeria Bottarel, Giulio Ricotti	A 40 nA/source energy harvesting power converter for multiple and heterogeneous sources.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, Chung-Chih Hung, Chin-Long Wey, Hsin-Yu Luo	Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Annachiara Spagnolo, Bob Verbruggen, Stefano D'Amico, Piet Wambacq	A 6.2mW 7b 3.5GS/s time interleaved 2-stage pipelined ADC in 40nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Youichi Momiyama, Atsushi Okamoto, Tsuyoshi Sakata, Makoto Takamiya, Takayasu Sakurai	An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Yunsup Lee, Andrew Waterman, Rimas Avizienis, Henry Cook, Chen Sun 0003, Vladimir Stojanovic, Krste Asanovic	A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Shin-Hao Chen, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Sheng Kang, Kevin Cheng 0002, Li-Ren Huang, Chao-Jen Huang, Hsin-Yu Luo	A Class-D amplifier powered by embedded single-inductor bipolar-output power module with low common noise and dynamic voltage boosting technique.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel	A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Xicheng Jiang, Narayan Prasad Ramachandran, Dae Woon Kang, Chee Kiong Chen, Mark Rutherford, Yonghua Cong, David Chang	Digitally-assisted analog and analog-assisted digital design techniques for a 28 nm mobile System-on-Chip.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Igor I. Izyumin, Mitchell Kline, Yu-Ching Yeh, Burak Eminoglu, Bernhard E. Boser	A 50 µW, 2.1 mdeg/s/√Hz frequency-to-digital converter for frequency-output MEMS gyroscopes.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Harald Kroll, Stefan Zwicky, Benjamin Weber, Christoph Roth, Christian Benkeser, Andreas Peter Burg, Qiuting Huang	An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Sechang Oh, Yoonmyung Lee, Jingcheng Wang, Zhiyoong Foo, Yejoong Kim, David T. Blaauw, Dennis Sylvester	Dual-slope capacitance to digital converter integrated in an implantable pressure sensing system.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Nicolo Sabatino, Gabriele Minoia, M. Roche, Daniele Baldi, Enrico Temporiti, Andrea Mazzanti	A 5th order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1		ESSCIRC 2014 - 40th European Solid State Circuits Conference, Venice Lido, Italy, September 22-26, 2014	ESSCIRC	2014	DBLP BibTeX RDF
1	Sudhir Satpathy, Sanu Mathew, Jiangtao Li 0001, Patrick Koeberl, Mark A. Anders 0001, Himanshu Kaul, Gregory K. Chen, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001	13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Benjamin Saft, Eric Schaefer, Andre Jager, Alexander Rolapp, Eckhard Hennig	An improved low-power CMOS thyristor-based micro-to-millisecond delay element.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Waclaw Godycki, Bo Sun, Alyssa B. Apsel	Part-time resonant switching for light load efficiency improvement of a 3-level fully integrated buck converter.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Mark Ingels, Xiaoqiang Zhang 0008, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx	A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Gabriele Devita, Alan Chi Wai Wong, Mark Dawkins, Kostas N. Glaros, U. Kiani, Franco Lauria, V. Madaka, Okundu C. Omeni, Johannes Schiff, A. Vasudevan, L. Whitaker, S. Yu, Alison J. Burdett	A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Athanasios Sarafianos, Michiel Steyaert	The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Pinar Basak Basyurt, Devrim Yilmaz Aksin, Edoardo Bonizzoni, Franco Maloberti	A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Mikko Englund, Kim B. Ostman, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Jussi Ryynänen, Kimmo Koli	A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Yu Pei 0002, Ying Chen, Domine M. W. Leenaerts, Bianca Slaats, A. Zamanifekri	A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamforming.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Clement Jany, Alexandre Siligaris, Jose-Luis Gonzalez Jimenez, Carolynn Bernier, Pierre Vincent, Philippe Ferrari	A novel ultra-low phase noise, programmable frequency multiplier-by-30 architecture. Application to 60-GHz frequency generation.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Manuel Suarez, Víctor M. Brea 0001, Jorge Fernández-Berni, Ricardo Carmona-Galán, Diego Cabello, Ángel Rodríguez-Vázquez	A 26.5 nJ/px 2.64 Mpx/s CMOS vision sensor for Gaussian pyramid extraction.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Ilkka Nissinen, Jan Nissinen, Jouni Holma, Juha Kostamovaara	A TDC-based 4×128 CMOS SPAD array for time-gated Raman spectroscopy.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Long Chen 0004, Arindam Sanyal, Ji Ma, Nan Sun 0001	A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Nima Maghari, Un-Ku Moon	Emerging analog-to-digital converters.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Oskar Andersson, Babak Mohammadi, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues	A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa	A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Dongju Lee, Minjae Lee	A 3 kHz flicker noise corner, odd-phase active mixer for direct conversion receivers.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Hanspeter Schmid, Alexander Huber, Dirk Sutterlin, Werner Tanner	A highly sensitive frontend IC for very robust capacitive vortex flowmeter sensors.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Luke Wang, Qiwei Wang, Anthony Chan Carusone	Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Ulrich Bihr, Jens Anders, J. Rickert, Martin Schuettler, A. Moeller, K. H. Boven, Joachim Becker, Maurits Ortmanns	A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chung-Hung Tsai	A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Manthena Vamshi Krishna, Anil Jain, Nasir Abdul Quadir, Paul D. Townsend, Peter Ossieur	A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Kentaro Yoshioka, Hiroki Ishikuro	A 13b SAR ADC with eye-opening VCO based comparator.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Jung-Woo Ha 0002, Bai-Sun Kong, Jung-Hoon Chun, Byeong-Ha Park	A fast response integrated current-sensing circuit for peak-current-mode buck regulator.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Yusuf Haque, Donald E. Lewis, Rex Hales, Ryan J. Kier, Tracy Johancsik, Paul T. Watkins, William Picken, Marcellus Harper, Shyam Dujari	Time interleaved 16 bit, 250MS/s ADC using a hybrid voltage/current mode architecture with foreground calibration.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marko Aleksic	A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx	A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Fabio Marchio, Boris Vittorelli, Roberto Colombo	Automotive electronics: Application & technology megatrends.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Stefano Perticaroli, Fabrizio Palma	A robust start-up Class-C CMOS VCO based on a common mode low frequency feedback loop.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Aravind Tharayil Narayanan, Kento Kimura, Wei Deng 0001, Kenichi Okada, Akira Matsuzawa	A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Marco Sautto, Davide Leone, Alessandro Savoia, Davide Ghisu, Fabio Quaglia, Giosuè Caliano, Andrea Mazzanti	A CMUT transceiver front-end with 100-V TX driver and 1-mW low-noise capacitive feedback RX amplifier in BCD-SOI technology.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Vincent Binet, Francois Amiard, Emmanuel Allier, Simon Valcin, Angelo Nagari	A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Ilter Özkaya, Cagri Gurleyuk, Atilim Ergul, Arda Akkaya, Devrim Yilmaz Aksin	A 50V input range 14bit 250kS/s ADC with 97.8dB SFDR and 80.2dB SNR.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Tzu-Chien Hsueh, Frank O'Mahony, Mozhgan Mansuri, Bryan Casper	An on-die all-digital power supply noise analyzer with enhanced spectrum measurements.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Sehat Sutardja	Slowing of Moore's law signals the beginning of Smart Everything.	ESSCIRC	2014	DBLP DOI BibTeX RDF
1	Carl Bryant, Henrik Sjöland	A 2.45GHz, 50uW wake-up receiver front-end with -88dBm sensitivity and 250kbps data rate.	ESSCIRC	2014	DBLP DOI BibTeX RDF

Publications at "ESSCIRC"( http://dblp.L3S.de/Venues/ESSCIRC )