Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
16	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	IOLTW	2002	DBLP DOI BibTeX RDF
16	Sumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna	A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs.	ASAP	2002	DBLP DOI BibTeX RDF	reconfigurable computing, embedded system design, energy optimization
16	Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia	On Routing Demand and Congestion Estimation for FPGAs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
16	Miron Abramovici, Charles E. Stroud, John Marty Emmert	Using embedded FPGAs for SoC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF
16	Oskar Mencer, Marco Platzner, Martin Morf, Michael J. Flynn	Object-oriented domain specific compilers for programming FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
16	Miguel A. Vega-Rodríguez, Juan Manuel Sánchez-Pérez, Juan Antonio Gómez Pulido	Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques.	DSD	2001	DBLP DOI BibTeX RDF
16	Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh	RPack: routability-driven packing for cluster-based FPGAs.	ASP-DAC	2001	DBLP DOI BibTeX RDF
16	Joerg Abke, Erich Barke	A New Placement Method for Direct Mapping into LUT-Based FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
16	Loïc Lagadec, Dominique Lavenier, Erwan Fabiani, Bernard Pottier	Placing, Routing, and Editing Virtual FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
16	James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer	System Level Tools for DSP in FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
16	Francisco Fernández 0001, Juan Manuel Sánchez-Pérez, Marco Tomassini	Placing and Routing Circuits on FPGAs by Means of Parallel and Distributed Genetic Programming.	ICES	2001	DBLP DOI BibTeX RDF
16	Mokhtar Nibouche, Ahmed Bouridane, Omar Nibouche, Danny Crookes	Rapid prototyping of orthonormal wavelet transforms on FPGAs.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
16	Miron Abramovici, John Marty Emmert, Charles E. Stroud	Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
16	Wolfgang Günther 0001, Rolf Drechsler	Performance Driven Optimization for MUX based FPGAs.	VLSI Design	2001	DBLP DOI BibTeX RDF
16	Kenneth Yan	Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks.	VLSI Design	2001	DBLP DOI BibTeX RDF
16	Steven J. E. Wilton	Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
16	Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein	Pipeline Reconfigurable FPGAs.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
16	Vijay Lakamraju, Russell Tessier	Tolerating operational faults in cluster-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
16	Jason Cong, Kenneth Yan	Synthesis for FPGAs with embedded memory blocks.	FPGA	2000	DBLP DOI BibTeX RDF
16	Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel	Power estimation approach for SRAM-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
16	Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh	Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
16	Alexander Marquardt, Vaughn Betz, Jonathan Rose	Timing-driven placement for FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
16	Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa	The Fastest Multiplier on FPGAs with Redundant Binary Representation.	FPL	2000	DBLP DOI BibTeX RDF
16	Hossam A. ElGindy, Martin Middendorf, Hartmut Schmeck, Bernd Schmidt	Task Rearrangement on Partially Reconfigurable FPGAs with Restricted Buffer.	FPL	2000	DBLP DOI BibTeX RDF
16	Christophe Bobda, Thomas Lehmann 0001	Efficient Building of Word Recongnizer in FPGAs for Term-Document Matrices Construction.	FPL	2000	DBLP DOI BibTeX RDF
16	Valery Sklyarov	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
16	Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier	Area-Optimized Technology Mapping for Hybrid FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
16	Chris Dick, Fred Harris 0001, Michael Rice	Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
16	L. Levinson, Reinhard Männer, M. Sessler, Harald Simmler	Preemptive Multitasking on FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
16	Wolfgang Günther 0001, Rolf Drechsler	ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.	EUROMICRO	2000	DBLP DOI BibTeX RDF
16	Nohpill Park, S. J. Ruiwale, Fabrizio Lombardi	Testing the Configurability of Dynamic FPGAs.	DFT	2000	DBLP DOI BibTeX RDF
16	Andreas Dandalis, Viktor K. Prasanna, José D. P. Rolim	A Comparative Study of Performance of AES Final Candidates Using FPGAs.	CHES	2000	DBLP DOI BibTeX RDF
16	Yao-Wen Chang, Yu-Tsang Chang	An architecture-driven metric for simultaneous placement and global routing for FPGAs.	DAC	2000	DBLP DOI BibTeX RDF
16	Min Xu, Fadi J. Kurdahi	Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
16	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
16	M. Kivioja, Jouni Isoaho, L. Vänskä	Design and Implementation of Viterbi Decoder with FPGAs.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
16	Nihar R. Mahapatra, Shantanu Dutt	Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs.	FTCS	1999	DBLP DOI BibTeX RDF
16	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
16	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
16	Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi	Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	FPGA, Fault Diagnosis, Fault Detection
16	Steve Casselman, John Schewel, Christophe Beaumont	IP Validation for FPGAs using Hardware Object TechnologyTM.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
16	Gerardo Orlando, Christof Paar	A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms.	FCCM	1999	DBLP DOI BibTeX RDF	Galois Fields multiplier, field programmable gate array application, cryptography, elliptic curve cryptography
16	José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías	Logic Restructuring for MUX-Based FPGAs.	EUROMICRO	1999	DBLP DOI BibTeX RDF
16	Shyue-Kung Lu, Cheng-Wen Wu	A novel approach to testing LUT-based FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
16	Igor Lemberski	Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
16	Parag K. Lala, Anup Singh, Alvernon Walker	A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	DCVSL, Stuck-ON/OFF, Stuck-at Faults, Self-testing
16	Wenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.	DFT	1999	DBLP DOI BibTeX RDF	Online Repair, Reassignment, Fault Tolerance, FPGA, Reconfiguration
16	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri	Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs.	DFT	1999	DBLP DOI BibTeX RDF	Self-checking systems, Field Programmable Gate Arrays, Artificial neural networks, Space applications
16	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito	Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.	DFT	1999	DBLP DOI BibTeX RDF
16	Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud	Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access.	VTS	1999	DBLP DOI BibTeX RDF
16	Jian Xu, Paifa Si, Wei-Kang Huang, Fabrizio Lombardi	A Novel Fault Tolerant Approach for SRAM-Based FPGAs.	PRDC	1999	DBLP DOI BibTeX RDF	FPGA, fault-tolerant routing, fault-tolerant architecture
16	Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
16	Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara	Universal Fault Diagnosis for Lookup Table FPGAs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
16	Glenn H. Chapman, Benoit Dufort	Using Laser Defect Avoidance to Build Large-Area FPGAs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
16	Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas	Managing Pipeline-Reconfigurable FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
16	Huiqun Liu, Kai Zhu 0001, D. F. Wong 0001	Circuit Partitioning with Complex Resource Constraints in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
16	Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek	Fast Module Mapping and Placement for Datapaths in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
16	Steven J. E. Wilton	SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays.	FPGA	1998	DBLP DOI BibTeX RDF
16	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Efficiently Supporting Fault-Tolerance in FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
16	Jordan S. Swartz, Vaughn Betz, Jonathan Rose	A Fast Routability-Driven Router for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
16	Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi	Novel Technique for Testing FPGAs.	DATE	1998	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, testing, reuse, diagnosis
16	Walter B. Ligon III, Scott McMillan, Greg Monn, Kevin Schoonover, Fred Stivers, Keith D. Underwood	A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs.	FCCM	1998	DBLP DOI BibTeX RDF
16	Valery Sklyarov, Nuno Lau, Ricardo Sal Monteiro, Andreia Melo, Arnaldo S. R. Oliveira, Konstantin Kondratjuk	Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs.	EUROMICRO	1998	DBLP DOI BibTeX RDF
16	Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi	On the Complexity of Sequential Testing in Configurable FPGAs.	DFT	1998	DBLP DOI BibTeX RDF	FPGA, pipeline, PLD, sequential testing, iterative array
16	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
16	Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi	In-Place Power Optimization for LUT-Based FPGAs.	DAC	1998	DBLP DOI BibTeX RDF
16	Neil W. Bergmann, Peter R. Sutton	A High-Performance Computing Module for a Low Earth Orbit Satellite Using Reconfigurable Logic.	FPL	1998	DBLP DOI BibTeX RDF
16	Andreas Dandalis, Viktor K. Prasanna	Space-efficient Mapping of 2D-DCT onto Dynamically Configurable Coarse-Grained Architectures.	FPL	1998	DBLP DOI BibTeX RDF
16	Frank-Michael Renner, Jürgen Becker 0001, Manfred Glesner	An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications.	FPL	1998	DBLP DOI BibTeX RDF
16	Wayne Luk, Steve McKeever	Pebble: A Language for Parametrised and Reconfigurable Hardware Design.	FPL	1998	DBLP DOI BibTeX RDF
16	Andreas C. Döring, Wolfgang Obelöer, Gunther Lustig	Programming and Implementation of Reconfigurable Routers.	FPL	1998	DBLP DOI BibTeX RDF
16	Tsutomu Maruyama, Terunobu Funatsu, Tsutomu Hoshino	A Field-Programmable Gate-Array System for Evolutionary Computation.	FPL	1998	DBLP DOI BibTeX RDF
16	J. Fischer, C. Müller, H. Kurz	A Co-simulation Concept for an Efficient Analysis of Complex Logic Designs.	FPL	1998	DBLP DOI BibTeX RDF
16	A. Abo Shosha, P. Reinhart, F. Rongen	Reconfigurable PCI-Bus Interface (RPCI).	FPL	1998	DBLP DOI BibTeX RDF
16	Ali Zakerolhosseini, Peter Lee 0002, Ed Horne	An FPFA Based Object Recognition Machine.	FPL	1998	DBLP DOI BibTeX RDF
16	Yuh-Sheng Lee, Allen C.-H. Wu	A performance and routability-driven router for FPGAs considering path delays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
16	Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi	A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programmable system, diagnosis, FPGA testing, XOR
16	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
16	Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel	ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL
16	Chris Dick, Fred Harris 0001	Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
16	Niklaus Wirth	The Language Lola, FPGAs and PLDs in Teaching Digital Circuit Design.	Ershov Memorial Conference	1996	DBLP DOI BibTeX RDF
16	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	A Test Methodology for Interconnect Structures of LUT-based FPGAs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Programmable Interconnect Structures, Cross Point Switch, Configurable Logic Block, FPGA, Test Pattern Generation
16	Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya	A new method to express functional permissibilities for LUT based FPGAs and its applications.	ICCAD	1996	DBLP DOI BibTeX RDF	look-up table (LUT), functional permissibility, optimization, FPGA, routing
16	Kevin A. Kwiat, Warren Debany, Salim Hariri	Software Fault Tolerance Using Dynamically Reconfigurable FPGAs.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
16	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
16	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
16	Kazuhiro Hayashi, Toshiaki Miyazaki, Kazuhiro Shirakawa, Kazuhisa Yamada, Naohisa Ohta	Reconfigurable real-time signal transport system using custom FPGAs.	FCCM	1995	DBLP DOI BibTeX RDF
16	Tanay Karnik, Sung-Mo Kang	An empirical model for accurate estimation of routing delay in FPGAs.	ICCAD	1995	DBLP DOI BibTeX RDF	Routing Delay, Modeling, FPGA, Estimation, Statistics
16	Hiroshi Sawada, Takayuki Suyama, Akira Nagoya	Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.	ICCAD	1995	DBLP DOI BibTeX RDF	support minimization, Boolean resubstitution, functional decomposition, look-up table, ordered binary decision diagram
16	Dwight D. Hill, Nam Sung Woo	The benefits of flexibility in lookup table-based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
15	Orsalia Georgia Hazapis, Elias S. Manolakos	Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time.	FPL	2011	DBLP DOI BibTeX RDF	Biochemical reaction networks, GillespieÂ¢s stochastic simulation algorithm, First Reaction Method, FPGAs, SoCs, Systems Biology
15	Tony M. Brewer	Instruction Set Innovations for the Convey HC-1 Computer.	IEEE Micro	2010	DBLP DOI BibTeX RDF	hybrid-core computing, FPGAs, reconfigurable computing, heterogeneous computing, accelerators, coprocessors, instruction set design
15	Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
15	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
15	John C. Lach, Vinu Vijay Kumar	Application-Specific Product Generics.	Computer	2009	DBLP DOI BibTeX RDF	Nonrecurring engineering costs, FPGAs, High-level synthesis, ASICs
15	Florian Dittmann 0001, Elmar Weber, Norma Montealegre	Implementation of the reconfiguration port scheduling on the erlangen slot machine.	FPGA	2009	DBLP DOI BibTeX RDF	erlangen slot machine, scheduling, fpgas, reconfiguration
15	Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf	A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.	FCCM	2009	DBLP DOI BibTeX RDF	Machine Learning, FPGAs, Support Vector Machines, Parallel Architectures, Hardware Acceleration
15	Kostas Theocharoulis, Charalampos Manifavas, Ioannis Papaefstathiou	High-End Reconfigurable Systems for Fast Windows' Password Cracking.	FCCM	2009	DBLP DOI BibTeX RDF	Security, FPGAs, Rainbow Tables
15	Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire	A Hardware Accelerated Simulation Environment for Spiking Neural Networks.	ARC	2009	DBLP DOI BibTeX RDF	FPGAs, reconfiguration, spiking neural networks, online training