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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1414 occurrences of 781 keywords
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Results
Found 2380 publication records. Showing 2380 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Akihiro Yamamoto |
Inductive Logic Programming: Yet Another Application of Logic. |
INAP |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Mary Jane Irwin |
Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
data compression, chip multiprocessors, optimizing compiler |
22 | Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti |
Hyperblock formation: a power/energy perspective for high performance VLIW architectures. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Esther Salamí, Mateo Valero |
A Vector-µSIMD-VLIW Architecture for Multimedia Applications. |
ICPP |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Mohamed A. Gomaa, T. N. Vijaykumar |
Opportunistic Transient-Fault Detection. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Stanley Kok, Pedro M. Domingos |
Learning the structure of Markov logic networks. |
ICML |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Jérôme Maloberti, Michèle Sebag |
Fast Theta-Subsumption with Constraint Satisfaction Algorithms. |
Mach. Learn. |
2004 |
DBLP DOI BibTeX RDF |
k-locality, constraint satisfaction, phase transition, relational learning, meta-learning |
22 | R. S. Milton, V. Uma Maheswari 0002, Arul Siromoney |
Rough Sets and Relational Learning. |
Trans. Rough Sets |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha |
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Jing Li 0002, Tao Jiang 0001 |
An exact solution for finding minimum recombinant haplotype configurations on pedigrees with missing data by integer linear programming. |
RECOMB |
2004 |
DBLP DOI BibTeX RDF |
missing data imputation, pedigree analysis, integer linear programming, branch-and-bound algorithm, recombination, haplotyping |
22 | Huibin Shi, Chris Bailey 0002 |
Investigating Available Instruction Level Parallelism for Stack Based Machine Architectures. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ruiming Li, Dian Zhou, Donglei Du |
Satisfiability and integer programming as complementary tools. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman |
Scaling the issue window with look-ahead latency prediction. |
ICS |
2004 |
DBLP DOI BibTeX RDF |
LHT, MNM, SILO, instruction sorting, CLP |
22 | Nagarajan Kandasamy, Dávid Hanák, Christopher P. van Buskirk, Himanshu Neema, Gabor Karsai |
Synthesis of robust task schedules for minimum disruption repair. |
SMC (6) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ajay Kumar Todimala, Byrav Ramamurthy |
Survivable Virtual Topology Routing under Shared Risk Link Groups in WDM Networks. |
BROADNETS |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Arathi Ramani, Igor L. Markov |
Automatically Exploiting Symmetries in Constraint Programming. |
CSCLP |
2004 |
DBLP DOI BibTeX RDF |
|
22 | David P. Enot, Ross D. King |
Application of Inductive Logic Programming to Structure-Based Drug Design. |
PKDD |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Lei Chen 0021, Steve Dropsho, David H. Albonesi |
Dynamic Data Dependence Tracking and its Application to Branch Prediction. |
HPCA |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ratthachat Chatpatanasiri, Boonserm Kijsirikul |
Learning First-Order Bayesian Networks. |
AI |
2003 |
DBLP DOI BibTeX RDF |
First-Order Bayesian Networks, Overfitting Problem, Propositionalisation, Feature Extraction, Inductive Logic Programming |
22 | Pen-Chung Yew |
Is There Exploitable Thread-Level Parallelism in General-Purpose Application Programs? |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Lal George, Matthias Blume |
Taming the IXP network processor. |
PLDI |
2003 |
DBLP DOI BibTeX RDF |
Intel IXA, bank assignment, programming languages, code generation, register allocation, integer linear programming, network processors |
22 | Pradeep Rao, S. K. Nandy 0001, M. N. V. Satya Kiran |
Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero |
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. |
ISHPC |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Cholwich Nattee, Sukree Sinthupinyo, Masayuki Numao, Takashi Okada |
Mining Chemical Compound Structure Data Using Inductive Logic Programming. |
Active Mining |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Yu Chen 0005, Puneet Gupta 0001, Andrew B. Kahng |
Performance-impact limited area fill synthesis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
VLSI manufacturability, coupling capacitance extraction, dummy fill problem, signal delay, linear programming, greedy method |
22 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Optimizing Loop Performance for Clustered VLIW Architectures. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Sam Rash, Dan Gusfield |
String barcoding: uncovering optimal virus signatures. |
RECOMB |
2002 |
DBLP DOI BibTeX RDF |
string barcoding, virus signatures, suffix trees, barcoding, testing set |
22 | Gayathri Krishnamurthy, Elana D. Granston, Eric Stotzer |
Affinity-based cluster assignment for unrolled loops. |
ICS |
2002 |
DBLP DOI BibTeX RDF |
affinity-based clustering (ABC) algorithms, homogeneous clusters, partitioned register files, software pipelining, loop optimizations, loop scheduling, VLIW architectures, loop unrolling, cluster assignment |
22 | Anupam Datta, Sidharth Choudhury, Anupam Basu |
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Optimal test access architectures for system-on-a-chip. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Kenji Watanabe, Wanming Chu, Yamin Li |
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading. |
ACSAC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng |
Estimation for maximum instantaneous current through supply lines for CMOS circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Kästner |
PROPAN: A Retargetable System for Postpass Optimisations and Analyses. |
LCTES |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh |
Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
test data bandwidth, linearization, test access mechanism (TAM), testing time, Embedded core testing, test bus |
22 | Valentin E. Brimkov, Stefan S. Dantchev |
On the Complexity of Integer Programming in the Blum-Shub-Smale Computational Model. |
IFIP TCS |
2000 |
DBLP DOI BibTeX RDF |
Integer programming, Knapsack problem, Algebraic complexity, Complexity bounds |
22 | Fumio Mizoguchi |
Anomaly Detection Using Visualization and Machine Learning. |
WETICE |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Krishnendu Chakrabarty |
Design of system-on-a-chip test access architectures under place-and-route and power constraints. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Saso Dzeroski, James Cussens, Suresh Manandhar |
An Introduction to Inductive Logic Programming and Learning Language in Logic. |
Learning Language in Logic |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Hayato Ohwada, Fumio Mizoguchi |
Parallel Execution for Speeding Up Inductive Logic Programming Systems. |
Discovery Science |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Vijay S. Pai, Sarita V. Adve |
Code Transformations to Improve Memory Parallelism. |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
22 | David I. August, John W. Sias, Jean-Michel Puiatti, Scott A. Mahlke, Daniel A. Connors, Kevin M. Crozier, Wen-mei W. Hwu |
The Program Decision Logic Approach to Predicated Execution. |
ISCA |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Yi-Min Jiang, Kwang-Ting Cheng |
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Hayato Ohwada, Makiko Daidoji, Shiroaki Shirato, Fumio Mizoguchi |
Learning First-Order Rules from Image Applied to Glaucoma Diagnosis. |
PRICAI |
1998 |
DBLP DOI BibTeX RDF |
|
22 | Soo-Mook Moon, Kemal Ebcioglu |
Parallelizing Nonnumerical Code with Selective Scheduling and Software Pipelining. |
ACM Trans. Program. Lang. Syst. |
1997 |
DBLP DOI BibTeX RDF |
global instruction scheduling, speculative code motion, instruction-level parallelism, software pipelining, VLIW, superscalar |
22 | Soohong P. Kim, Raymond Hoare, Henry G. Dietz |
VLIW Across Multiple Superscalar Processors on a Single Chip. |
IEEE PACT |
1997 |
DBLP DOI BibTeX RDF |
|
22 | Wim Van Laer, Luc De Raedt, Saso Dzeroski |
On Multi-class Problems and Discretization in Inductive Logic Programming. |
ISMIS |
1997 |
DBLP DOI BibTeX RDF |
Classification, Learning, Knowledge Discovery, Discretization, Inductive Logic Programming |
22 | Avaneendra Gupta, John P. Hayes |
Width minimization of two-dimensional CMOS cells using integer programming. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
leaf cell synthesis, two-dimensional layout, diffusion sharing, transistor chains, CMOS networks, Layout optimization, module generation |
22 | Arun Balakrishnan, Srimat T. Chakradhar |
Retiming with logic duplication transformation: theory and an application to partial scan. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function |
22 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
22 | Adrian Slowik, Georg Piepenbrock, Peter Pfahler |
Compiling Nested Loops for Limited Connectivity VLIWs. |
CC |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Irene Stahl |
Properties of Inductive Logic Programming in Function-Free Horn Logic. |
ECML |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Saso Dzeroski, Stephen H. Muggleton, Stuart Russell 0001 |
Learnability of Constrained Logic Programs. |
ECML |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Manoj Gupta 0001, Fermín Sánchez, Josep Llosa |
CSMT: Simultaneous Multithreading for Clustered VLIW Processors. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
clustered VLIW architectures, ILP, simultaneous multithreading, multithreaded processors, VLIW architectures |
17 | Michele Lombardi 0001, Luca Benini, Abhishek Garg, Giovanni De Micheli |
Methods for Designing Reliable Probe Arrays. |
BIBE |
2010 |
DBLP DOI BibTeX RDF |
Probe based sensors, Optimization, Microarrays, SAT, ILP |
17 | Tim De Pauw, Stijn Verstichel, Bruno Volckaert, Filip De Turck, Veerle Ongenae |
Resource-Aware Scheduling of Distributed Ontological Reasoning Tasks in Wireless Sensor Networks. |
SUTC/UMC |
2010 |
DBLP DOI BibTeX RDF |
simulation, scheduling, ontology, heuristic, reasoning, ILP |
17 | Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski |
Out-of-order issue logic using sorting networks. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
out-of-order processing, ILP, micro-architecture, issue queue, high speed circuits |
17 | Yixin Shou, Robert A. van Engelen |
Automatic SIMD vectorization of chains of recurrences. |
ICS |
2008 |
DBLP DOI BibTeX RDF |
chains of recurrences, short vector simd, vectorization, ILP |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Predictable Performance in SMT Processors: Synergy between the OS and SMTs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
real time, operating systems, performance predictability, ILP, thread-level parallelism, simultaneous multithreading, Multithreaded processors |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Architectural support for real-time task scheduling in SMT processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
scheduling, real time, multithreading, performance predictability, ILP, thread-level parallelism, SMT |
17 | Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev |
The Midlifekicker Microarchitecture Evaluation Metric. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
pipeline, microarchitecture, ILP |
17 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Removing communications in clustered microarchitectures through instruction replication. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
instruction replication, statically scheduled processors, ILP, modulo-scheduling, Clustered microarchitectures |
17 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Predictable performance in SMT processors. |
Conf. Computing Frontiers |
2004 |
DBLP DOI BibTeX RDF |
real time, operating systems, multithreading, performance predictability, ILP, thread-level parallelism, SMT |
17 | Hillery C. Hunter, Jaime H. Moreno |
A new look at exploiting data parallelism in embedded systems. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
sub-word parallelism, architecture, embedded, DSP, telecommunications, SIMD, VLIW, processor, ILP, media, DLP, data-level parallelism |
17 | Young Chul Sohn, N. H. Jung, Seung Ryoul Maeng |
Request Reordering to Enhance the Performance of Strict Consistency Models. |
IEEE Comput. Archit. Lett. |
2002 |
DBLP DOI BibTeX RDF |
multiprocessor, ILP, memory consistency model |
17 | Sunghyun Jee, Kannappan Palaniappan |
Dynamically Scheduling VLIW Instructions with Dependency Information. |
Interaction between Compilers and Computer Architectures |
2002 |
DBLP DOI BibTeX RDF |
DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP |
17 | Sunghyun Jee, Kannappan Palaniappan |
Compiler Processor Tradeoffs for DISVLIW Architecture. |
ISPAN |
2002 |
DBLP DOI BibTeX RDF |
Balanced Scheduling, DISVLIW, Processor architecture, ILP |
17 | Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio 0001, Jyotsna Sabarinathan |
Java Runtime Systems: Characterization and Architectural Implications. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
CPU and cache architectures, Java, performance evaluation, benchmarking, ILP, Java bytecodes |
17 | M. Balakrishnan, Heman Khanna |
Allocation of FIFO structures in RTL data paths. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
synthesis, RTL, ILP, FIFO, data path |
17 | Kang Su Gatlin, Larry Carter |
Faster FFTs via Architecture-Cognizance. |
IEEE PACT |
2000 |
DBLP DOI BibTeX RDF |
cache, feedback, memory hierarchy, compiler optimization, associativity, divide-and-conquer, ILP, runtime systems, registers, TLB |
17 | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
Design of Instruction Stream Buffer with Trace Support for X86 Processors. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache |
17 | Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte |
A Fast Interrupt Handling Scheme for VLIW Processors. |
IEEE PACT |
1998 |
DBLP DOI BibTeX RDF |
Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue |
17 | Erik Nystrom, Alexandre E. Eichenberger |
Effective Cluster Assignment for Modulo Scheduling. |
MICRO |
1998 |
DBLP DOI BibTeX RDF |
ILP, modulo scheduling, cluster architecture, cluster assignment |
17 | Keiko Shimazu, Koichi Furukawa |
Knowledge discovery in database by Progol-design, implementation and its application to expert system building. |
SAC |
1997 |
DBLP DOI BibTeX RDF |
KDD, ILP, datamining, ER model, E-mail-classification |
17 | David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha |
Early Zero Detection. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP |
17 | Soo-Mook Moon, Kemal Ebcioglu |
A study on the number of memory ports in multiple instruction issue machines. |
MICRO |
1993 |
DBLP DOI BibTeX RDF |
memory ports, speculative loads, ILP, static scheduling, memory disambiguation |
16 | Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung |
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP) |
16 | C. Li, J. M. van den Akker, Sjaak Brinkkemper, Guido Diepen |
Integrated Requirement Selection and Scheduling for the Release Planning of a Software Product. |
REFSQ |
2007 |
DBLP DOI BibTeX RDF |
Requirement Selection, Requirement Scheduling, Simulation, Release Planning, Integer Linear Programming (ILP) |
16 | Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Benjemaa |
An Adaptive On-Line HW/SW Partitioning for Soft Real Time Reconfigurable Systems. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
ILP formulation, Dynamic Scheduling, real time constraints, HW/SW Partitioning |
16 | Jeremy R. Johnson, Werner Krandick, Anatole D. Ruslanov |
Architecture-aware classical Taylor shift by 1. |
ISSAC |
2005 |
DBLP DOI BibTeX RDF |
ILP scheduling, Taylor shift, delayed carry propagation, multiprecision arithmetic, register tiling, high-performance computing, code generation, memory hierarchy, polynomials, performance tuning, loop unrolling |
16 | Andrea Lodi 0001, Silvano Martello, Daniele Vigo |
Models and Bounds for Two-Dimensional Level Packing Problems. |
J. Comb. Optim. |
2004 |
DBLP DOI BibTeX RDF |
ILP models, packing, cutting |
16 | Hui Zang, Canhui Ou, Biswanath Mukherjee |
Path-protection routing and wavelength assignment (RWA) in WDM mesh networks under duct-layer constraints. |
IEEE/ACM Trans. Netw. |
2003 |
DBLP DOI BibTeX RDF |
optical network, protection, wavelength-division multiplexing (WDM), lightpath, wavelength routing, integer linear program (ILP), shared risk link group |
16 | Octavian Cret, Kalman Pusztai, Cristian Vancea, Balint Szente |
CREC: A Novel Reconfigurable Computing Design Methodology. |
IPDPS |
2003 |
DBLP DOI BibTeX RDF |
general-purpose reconfigurable systems, Hardware / Software CoDesign, multiple execution units, FPGA, VHDL, RISC, Instruction Level Parallelism (ILP) |
16 | Donald Chai, Andreas Kuehlmann |
A fast pseudo-boolean constraint solver. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
0-1 ILP, pseudo-boolean, satisfiability |
16 | Aneesh Aggarwal, Manoj Franklin |
Hierarchical Interconnects for On-Chip Clustering. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP) |
16 | Waleed Meleis, Alexandre E. Eichenberger, Ivan D. Baev |
Scheduling Superblocks with Bound-Based Branch Trade-Offs. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
ILP compiler technique, lower bound, scheduling heuristic, Superblock |
16 | Simonjit Dutta, Manoj Franklin |
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors. |
IEEE Trans. Parallel Distributed Syst. |
1999 |
DBLP DOI BibTeX RDF |
Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP) |
16 | David López 0001, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. |
ICPP |
1999 |
DBLP DOI BibTeX RDF |
ILP limits, multiply-add fused, performance/cost evaluation, software pipelining, VLIW architectures, numerical code |
16 | Kai Wang, Manoj Franklin |
Highly Accurate Data Value Prediction Using Hybrid Predictors. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
Instruction-level parallel (ILP) processing Speculative execution, Stride-based prediction, Two-level prediction, Data speculation |
16 | Krishna K. Sundararaman, Manoj Franklin |
Multiscalar Execution along a Single Flow of Control. |
ICPP |
1997 |
DBLP DOI BibTeX RDF |
multiple control flows, branch prediction, control dependence, instruction-level parallelism (ILP) |
16 | Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau |
Region-based compilation: an introduction and motivation. |
MICRO |
1995 |
DBLP DOI BibTeX RDF |
ILP compilation, code expansion, compilation time complexity, function inlining, region-based compilation |
16 | Nicolas Lachiche, Christel Vrain (eds.) |
Late Breaking Papers of the 27th International Conference on Inductive Logic Programming, Orléans, France, September 4-6, 2017. |
ILP (Late Breaking Papers) |
2018 |
DBLP BibTeX RDF |
|
16 | Nunung Nurul Qomariyah, Dimitar Kazakov |
Learning from Ordinal Data with Inductive Logic Programming in Description Logic. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Yulong Gu, Paolo Missier |
Adaptive Incremental Learning for Statistical Relational Models Using Gradient-Based Boosting. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Jáchym Barvínek, Filip Zelezný |
A First-Order Axiomatization for Transition Learning with Rich Constraints. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Ahmed Samet, Thomas Guyet, Benjamin Négrevergne |
Mining Rare Sequential Patterns with ASP. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | James Cussens, Alessandra Russo (eds.) |
Proceedings of the 26th International Conference on Inductive Logic Programming (Short papers), London, UK, 2016. |
ILP (Short Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Tomoyuki Uchida, Satoshi Matsumoto, Takayoshi Shoudai, Yusuke Suzuki, Tetsuhiro Miyahara |
Learning of Primitive Formal Systems Defining Labelled Ordered Tree Languages via Queries. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Yin Jun Phua, Tony Ribeiro, Sophie Tourret, Katsumi Inoue |
Learning Logic Program Representation for Delayed Systems With Limited Training Data. |
ILP (Late Breaking Papers) |
2017 |
DBLP BibTeX RDF |
|
16 | Hendrik Blockeel, Svetlana Valevich |
A Simple Framework for Theta-Subsumption Testing in Prolog. |
ILP (Short Papers) |
2016 |
DBLP BibTeX RDF |
|
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