Search results for "ISQED"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, Shanq-Jang Ruan	Configurable redundant via-aware standard cell design considering multi-via mechanism.	ISQED	2013	DBLP DOI BibTeX RDF
1	Kentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe	Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology.	ISQED	2013	DBLP DOI BibTeX RDF
1	Sadiq M. Sait, Abdalrahman M. Arafeh	Tabu search based cells placement in nanofabric architectures with restricted connectivity.	ISQED	2013	DBLP DOI BibTeX RDF
1	Sandeep Koranne	Analysis of very large resistive networks using low distortion embedding.	ISQED	2013	DBLP DOI BibTeX RDF
1	Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas	CMOS inverter delay model based on DC transfer curve for slow input.	ISQED	2013	DBLP DOI BibTeX RDF
1	Errikos Lourandakis, Stefanos Stefanou, Konstantinos Nikellis, Sotiris Bantas	RF passive device modeling and characterization in 65nm CMOS technology.	ISQED	2013	DBLP DOI BibTeX RDF
1	Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato	Multi-trap RTN parameter extraction based on Bayesian inference.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jingwei Lu, Chiu-Wing Sham	LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ku He, Andreas Gerstlauer, Michael Orshansky	Low-energy digital filter design based on controlled timing error acceptance.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero	On the selection of adder unit in energy efficient vector processing.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang	Impacts of NBTI and PBTI effects on ternary CAM.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon	Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jiaqi Yan, Zuying Luo, Liang Tang	Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yanzhi Wang, Maryam Triki, Xue Lin, Ahmed Chiheb Ammari, Massoud Pedram	Hierarchical dynamic power management using model-free reinforcement learning.	ISQED	2013	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islands.	ISQED	2013	DBLP DOI BibTeX RDF
1	Dheepakkumaran Jayaraman, Spyros Tragoudas	Performance validation through implicit removal of infeasible paths of the behavioral description.	ISQED	2013	DBLP DOI BibTeX RDF
1	Rishik Bazaz, Jianyong Xie, Madhavan Swaminathan	Electrical and thermal analysis for design exchange formats in three dimensional integrated circuits.	ISQED	2013	DBLP DOI BibTeX RDF
1	Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato	High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA.	ISQED	2013	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop.	ISQED	2013	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Arnaud Virazel, Etienne Auvray	Effect-cause intra-cell diagnosis at transistor level.	ISQED	2013	DBLP DOI BibTeX RDF
1	Vinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Jacob A. Abraham	On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ting Yu 0007, Martin D. F. Wong	A novel and efficient method for power pad placement optimization.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee 0001, Prakash R. Apte	Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimization.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yuko Hara-Azumi, Hiroyuki Tomiyama	Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation.	ISQED	2013	DBLP DOI BibTeX RDF
1	Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda	A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shigetaka Kumashiro	A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand	An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001	Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags.	ISQED	2013	DBLP DOI BibTeX RDF
1	Soumyajit Chatterjee, Hafizur Rahaman 0001, Tuhina Samanta	Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jun Yong Shin, Nikil D. Dutt, Fadi J. Kurdahi	Vision-inspired global routing for enhanced performance and reliability.	ISQED	2013	DBLP DOI BibTeX RDF
1	Nan Wang 0003, Song Chen 0001, Takeshi Yoshimura	Min-cut based leakage power aware scheduling in high-level synthesis.	ISQED	2013	DBLP DOI BibTeX RDF
1	Valeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto	Enabling sizing for enhancing the static noise margins.	ISQED	2013	DBLP DOI BibTeX RDF
1	Hanif Fatemi, Peivand Tehrani	Crosstalk timing windows overlap in statistical static timing analysis.	ISQED	2013	DBLP DOI BibTeX RDF
1	Rishi Todani, Ashis Kumar Mal	A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yanzhi Wang, Shuang Chen 0001, Hadi Goudarzi, Massoud Pedram	Resource allocation and consolidation in a multi-core server cluster using a Markov decision process model.	ISQED	2013	DBLP DOI BibTeX RDF
1	Gong Chen 0002, Yu Zhang, Bo Yang 0004, Qing Dong 0002, Shigetoshi Nakatake	A comparator energy model considering shallow trench isolation stress by geometric programming.	ISQED	2013	DBLP DOI BibTeX RDF
1	Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li 0002	Reliability-constrained die stacking order in 3DICs under manufacturing variability.	ISQED	2013	DBLP DOI BibTeX RDF
1	Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori	Aging-aware timing analysis considering combined effects of NBTI and PBTI.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jiyuan Luan, Michael DiVita	Analysis and reliability test to improve the data retention performance of EPROM circuits.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai	Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yinhe Han 0001, Song Jin, Jibing Qiu, Qiang Xu 0001, Xiaowei Li 0001	On predicting NBTI-induced circuit aging by isolating leakage change.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yue Hu, Shaoming Chen, Lu Peng 0001, Edward Song, Jin-Woo Choi	Effective thermal control techniques for liquid-cooled 3D multi-core processors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Suming Lai, Peng Li 0001	A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulation.	ISQED	2013	DBLP DOI BibTeX RDF
1	Kwang Sub Yoon, Keon Lee	A CMOS high dimming ratio power-LED driver with a preloading inductor current method.	ISQED	2013	DBLP DOI BibTeX RDF
1	Chung-Kai Hsu, Kun-Lin Tsai, Jing-Fu Jheng, Shanq-Jang Ruan, Chung-An Shen	A low power detection routing method for bufferless NoC.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ahmet Ceyhan, Azad Naeemi	Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devices.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yi Xiang, Sudeep Pasricha	Thermal-aware semi-dynamic power management for multicore systems with energy harvesting.	ISQED	2013	DBLP DOI BibTeX RDF
1	Avijit Dutta, Neil Tuttle, Krishnan Anandh	Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance.	ISQED	2013	DBLP DOI BibTeX RDF
1	Wulong Liu, Haixiao Du, Yu Wang 0002, Yuchun Ma, Yuan Xie 0001, Jinguo Quan, Huazhong Yang	TSV-aware topology generation for 3D Clock Tree Synthesis.	ISQED	2013	DBLP DOI BibTeX RDF
1	Tun Li, Yang Guo 0003, Wanwei Liu, Chiyuan Ma	Efficient translation validation of high-level synthesis.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shrikanth Ganapathy, Ramon Canal, Antonio González 0001, Antonio Rubio 0001	Effectiveness of hybrid recovery techniques on parametric failures.	ISQED	2013	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen	Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jinbo Wan, Hans G. Kerkhoff	An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulations.	ISQED	2013	DBLP DOI BibTeX RDF
1	Mohammad Shokrolah Shirazi, Brendan Morris, Henry Selvaraj	Fast FPGA-based fault injection tool for embedded processors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Zihao Chen, Hailong Yao, Yici Cai	SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.	ISQED	2013	DBLP DOI BibTeX RDF
1	Martin D. F. Wong	Advances in wire routing.	ISQED	2013	DBLP DOI BibTeX RDF
1	Chih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan	Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanning.	ISQED	2013	DBLP DOI BibTeX RDF
1	Bao Liu 0001, Lu Wang	Input-aware statistical timing analysis-based delay test pattern generation.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shan Cao, Zhaolin Li, Zhixiang Chen 0003, Guoyue Jiang, Shaojun Wei	Compiler-assisted leakage energy optimization of media applications on stream architectures.	ISQED	2013	DBLP DOI BibTeX RDF
1	Nicolo Testi, Yang Xu 0017	A 0.2nJ/sample 0.01mm2 ring oscillator based temperature sensor for on-chip thermal management.	ISQED	2013	DBLP DOI BibTeX RDF
1	Hong Zhu 0009, Volkan Kursun	Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yiqiang Ding, Wei Zhang 0002	On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Dinesh Ganta, Leyla Nazhandali	Easy-to-build Arbiter Physical Unclonable Function with enhanced challenge/response set.	ISQED	2013	DBLP DOI BibTeX RDF
1	Na Gong, Jinhui Wang, Ramalingam Sridhar	Application-driven power efficient ALU design methodology for modern microprocessors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi	Welcome to ISQED 2013.	ISQED	2013	DBLP DOI BibTeX RDF
1		International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013	ISQED	2013	DBLP BibTeX RDF
1	Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar	Flexible data allocation for scratch-pad memories to reduce NBTI effects.	ISQED	2013	DBLP DOI BibTeX RDF
1	Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa	Suspicious timing error prediction with in-cycle clock gating.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yong Zou 0001, Sudeep Pasricha	Reliability-aware and energy-efficient synthesis of NoC based MPSoCs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Animesh Datta, Mohamed H. Abu-Rahma, Sachin Dileep Dasnurkar, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu	Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technology.	ISQED	2013	DBLP DOI BibTeX RDF
1	Rahul Krishnan, Wei Wu, Fang Gong, Lei He 0001	Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy.	ISQED	2013	DBLP DOI BibTeX RDF
1	Chenyun Pan, Ahmet Ceyhan, Azad Naeemi	System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Qiaosha Zou, Jing Xie 0006, Yuan Xie 0001	Cost-driven 3D design optimization with metal layer reduction technique.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera	Analysis and comparison of XOR cell structures for low voltage circuit design.	ISQED	2013	DBLP DOI BibTeX RDF
1	Zhi Li 0016, Jingweijia Tan, Xin Fu	Hybrid CMOS-TFET based register files for energy-efficient GPGPUs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Krishna Srinivasan, Jonathan Rosenfeld	Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detector.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jacob Murray, Rajath Hegde, Teng Lu, Partha Pratim Pande, Behrooz A. Shirazi	Sustainable dual-level DVFS-enabled NoC with on-chip wireless links.	ISQED	2013	DBLP DOI BibTeX RDF
1	Kasyab P. Subramaniyan, Per Larsson-Edefors	Manufacturable nanometer designs using standard cells with regular layout.	ISQED	2013	DBLP DOI BibTeX RDF
1	Mrigank Sharad, Karthik Yogendra, Kon-Woo Kwon, Kaushik Roy 0001	Design of ultra high density and low power computational blocks using nano-magnets.	ISQED	2013	DBLP DOI BibTeX RDF
1	Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu	A system-level solution for managing spatial temperature gradients in thinned 3D ICs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jing Xie 0006, Yang Du, Yuan Xie 0001	CPDI: Cross-power-domain interface circuit design in monolithic 3D technology.	ISQED	2013	DBLP DOI BibTeX RDF
1	Young-Ho Gong, Hyung Beom Jang, Sung Woo Chung	Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay.	ISQED	2013	DBLP DOI BibTeX RDF
1	Alexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel	A virtualization approach for MIPS-based MPSoCs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue	Framework for analog test coverage.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ken Yano, Takanori Hayashida, Toshinori Sato	Improving timing error tolerance without impact on chip area and power consumption.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jongpil Jung, Kyungsu Kang, Giovanni De Micheli, Chong-Min Kyung	Runtime 3-D stacked cache management for chip-multiprocessors.	ISQED	2013	DBLP DOI BibTeX RDF
1	Satyanarayana Telikepalli, Madhavan Swaminathan, David C. Keezer	Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signaling.	ISQED	2013	DBLP DOI BibTeX RDF
1	Ahish Mysore Somashekar, Spyros Tragoudas	Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements.	ISQED	2013	DBLP DOI BibTeX RDF
1	Yuriy Shiyanovskii, Christos A. Papachristou, Cheng-Wen Wu	Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs.	ISQED	2013	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Garima Thakral	Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study.	ISQED	2013	DBLP DOI BibTeX RDF
1	Zheng Wang 0020, Chao Chen, Anupam Chattopadhyay	Fast reliability exploration for embedded processors via high-level fault injection.	ISQED	2013	DBLP DOI BibTeX RDF
1	Amaravati Anvesha, Maryam Shojaei Baghini	A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioning.	ISQED	2013	DBLP DOI BibTeX RDF
1	Adrian Evans, Michael Nicolaidis, Shi-Jie Wen, Thiago Asis	Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flops.	ISQED	2013	DBLP DOI BibTeX RDF
1	Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun	A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability.	ISQED	2013	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Gi-Joon Nam, Shayak Banerjee	Wire delay variability in nanoscale technology and its impact on physical design.	ISQED	2013	DBLP DOI BibTeX RDF
1	Jifeng Chen, Mohammad Tehranipoor	A novel flow for reducing clock skew considering NBTI effect and process variations.	ISQED	2013	DBLP DOI BibTeX RDF
1	Mrigank Sharad, Deliang Fan, Kaushik Roy 0001	Low power and compact mixed-mode signal processing hardware using spin-neurons.	ISQED	2013	DBLP DOI BibTeX RDF
1	Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif	SRAM bit-line electromigration mechanism and its prevention scheme.	ISQED	2013	DBLP DOI BibTeX RDF
1	Dheepakkumaran Jayaraman, Spyros Tragoudas	A method to determine the sensitization probability of a non-robustly testable path.	ISQED	2013	DBLP DOI BibTeX RDF

Publications at "ISQED"( http://dblp.L3S.de/Venues/ISQED )