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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Colin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic |
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. |
ISSCC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino |
Ultra-compact binary neural networks for human activity recognition on RISC-V processors. |
CF |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic |
A comparative survey of open-source application-class RISC-V processor implementations. |
CF |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Hepp, Georg Sigl |
Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. |
CF |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. |
ICCD |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard |
HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. |
AsiaCCS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara |
Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores. |
LCPC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Lorenzo Lamberti, Manuele Rusci, Marco Fariselli, Francesco Paci, Luca Benini |
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David |
RISC-V Barrel Processor for Deep Neural Network Acceleration. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini |
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Camilo Rojas, Hanssel Morales, Elkim Roa |
A Low-Cost Bug Hunting Verification Methodology for RISC-V-Based Processors. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Süleyman Savas, Endri Bezati, Jörn W. Janneck |
Generating hardware and software for RISC-V cores generated with Rocket Chip generator. |
SoCC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Rei Watanabe, Jubee Tada, Keiichi Sato |
An Implementation of a World Grid Square Codes Generator on a RISC-V Processor. |
CANDAR (Workshops) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Dai-Duong Tran, Thi Giang Truong, Truong Giang Do, The Duc Do |
Risc-V Random Test Generator. |
ACOMP |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Ben Marshall, Daniel Page, Thinh Hung Pham |
A lightweight ISE for ChaCha on RISC-V. |
ASAP |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mingjian Sun, Yuan Li, Song Chen 0001, Yi Kang |
A Low Power Branch Prediction for Deep Learning on RISC-V Processor. |
ASAP |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Shihang Wang, Jianghan Zhu, Qi Wang 0051, Can He, Terry Tao Ye |
Customized Instruction on RISC-V for Winograd-Based Convolution Acceleration. |
ASAP |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Augusto Pedraza |
Reliability Evaluation of RISC-V and ARM Microprocessors Through a New Fault Injection Tool. |
LATS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Tobias Faller, Philipp Scholl, Tobias Paxian, Bernd Becker 0001 |
Towards SAT-Based SBST Generation for RISC-V Cores. |
LATS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Marouene Boubakri, Fausto Chiatante, Belhassen Zouari |
Open Portable Trusted Execution Environment framework for RISC-V. |
EUC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib |
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V. |
ACM Great Lakes Symposium on VLSI |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Xinyu Qin, Xudong Liu, Jun Han 0003 |
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC. |
ASICON |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jiyuan Bai, Xiang Wang, Zikang Zhang, Chang Cai, Gengsheng Chen |
A Hierarchical Fault Injection System for RISC-V Processors Targeting Single Event Upsets in Flip-Flops. |
ASICON |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Austin Harris 0001, Tarunesh Verma, Shijia Wei, Lauren Biernacki, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd M. Austin |
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. |
HOST |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri |
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. |
DFT |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Zahra Kazemi, Amin Norollah, Afef Kchaou, Mahdi Fazeli, David Hély, Vincent Beroulle |
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack. |
DFT |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone |
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor. |
DFT |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain |
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. |
DFT |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mohd Nizam Mohd Najib, Dzati Athiar Ramli |
Analysis of Smart IoT Portal Based on Advanced RISC Machines (ARM) Processor for Fanless Heat Maintenance. |
RoViSP |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sabine Pircher, Johannes Geier, Alexander Zeh, Daniel Mueller-Gritschneder |
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem. |
ISQED |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Avani Dave, Nilanjan Banerjee, Chintan Patel |
CARE: Lightweight Attack Resilient Secure Boot Architecture with Onboard Recovery for RISC-V based SOC. |
ISQED |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jaekyung Im, Seokhyeong Kang |
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham |
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Wooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han |
K-means Clustering-specific Lightweight RISC-V processor. |
ISOCC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Stefan Steinegger, David Schrammel, Samuel Weiser, Pascal Nasahl, Stefan Mangard |
SERVAS! Secure Enclaves via RISC-V Authenticryption Shield. |
ESORICS (2) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Peter Sewell |
Engineering with Full-scale Formal Architecture: Morello, CHERI, Armv8-A, and RISC-V. |
FMCAD |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Dapeng Gao, Tom Melham |
End-to-End Formal Verification of a RISC-V Processor Extended with Capability Pointers. |
FMCAD |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Carlton Shepherd, Konstantinos Markantonakis, Georges-Axel Jaloyan |
LIRA-V: Lightweight Remote Attestation for Constrained RISC-V Devices. |
SP (Workshops) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su |
Implement 32-bit RISC-V Architecture Processor using Verilog HDL. |
ISPACS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sarah L. Harris, David M. Harris |
Digital Design and RISC-V Computer Architecture Textbook. |
WCAE |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Stephen A. Zekany, Jielun Tan, James A. Connolly |
Teaching Out-of-Order Processor Design with the RISC-V ISA. |
WCAE |
2021 |
DBLP DOI BibTeX RDF |
|
13 | P. S. Babu, Snehashri Sivaraman, Deepa N. Sarma, Tripti S. Warrier |
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers |
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Shota Matsuno, Masashi Tawada, Nozomu Togawa |
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. |
ICCE |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alessandro Cilardo |
Memory Encryption Support for an FPGA-based RISC-V Implementation. |
DTIS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Luca Zulberti, Pietro Nannipieri, Luca Fanucci |
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. |
DTIS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo |
Characterization of a RISC-V System-on-Chip under Neutron Radiation. |
DTIS |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu, Thomas Benz, Timo Schneider, Jakub Beránek, Luca Benini, Torsten Hoefler |
A RISC-V in-network accelerator for flexible high-performance low-power packet processing. |
ISCA |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Eike Hahn, Dominik Kalinowski, Waldemar Müller, Mohamed Abdelawwad, Josef Börcsök |
RISC-V Based Safety System-on-Chip with Hardware Comparator. |
CECNet |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Brad Green, Dillon Todd, Jon C. Calhoun, Melissa C. Smith |
TIGRA: A Tightly Integrated Generic RISC-V Accelerator Interface. |
CLUSTER |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Hsu-Kang Dow, Tuo Li 0001, William Miles, Sri Parameswaran |
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. |
DAC |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Xinchao Zhong, Chiu-Wing Sham, Longyu Ma |
A Highly Integrated RISC-V Based SoC for On-Board Unit in ETC System. |
GCCE |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Erfan Gholizadehazari, Tuba Ayhan, Berna Örs |
An FPGA Implementation of a RISC-V Based SoC System for Image Processing Applications. |
SIU |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz, Sung Kyu Lim |
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. |
IEEE Comput. Archit. Lett. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Daniel Petrisko, Farzam Gilani, Mark Wyse, Dai Cheol Jung, Scott Davidson 0004, Paul Gao 0001, Chun Zhao, Zahra Azad, Sadullah Canakci, Bandhav Veluri, Tavio Guarino, Ajay Joshi, Mark Oskin, Michael Bedford Taylor |
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. |
IEEE Micro |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Nguyen My Qui, Chang Hong Lin, Poki Chen |
Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA. |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Ahmed Kamaleldin, Salma Hesham, Diana Göhringer |
Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators. |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini |
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. |
IEEE Trans. Very Large Scale Integr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | John Charles Wright, Colin Schmidt 0001, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic |
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. |
IEEE Trans. Very Large Scale Integr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Vinay B. Y. Kumar, Suman Deb, Naina Gupta 0001, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson |
Towards Designing a Secure RISC-V System-on-Chip: ITUS. |
J. Hardw. Syst. Secur. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Xiaoyang Xie, Zhihan Fang, Yang Wang 0015, Fan Zhang 0019, Desheng Zhang |
RISC: Resource-Constrained Urban Sensing Task Scheduling Based on Commercial Fleets. |
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Seungmin Jung |
Image Processor and RISC MCU Embedded Single Chip Fingerprint Sensor. |
J. Sens. Actuator Networks |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Yuzhi Zhou, Xi Jin 0002, Tian Xiang, Daolu Zha |
Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. |
Microprocess. Microsystems |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Asmit De, Aditya Basu, Swaroop Ghosh, Trent Jaeger |
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Isaías B. Felzmann, João Fabrício Filho, Lucas Francisco Wanner |
Risk-5: Controlled Approximations for RISC-V. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Cristóbal Ramírez, César-Alejandro Hernández-Calderón, Oscar Palomar, Osman S. Unsal, Marco Antonio Ramírez, Adrián Cristal |
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. |
ACM Trans. Archit. Code Optim. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik |
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. |
J. Electron. Test. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Ronny García-Ramírez, Alfonso Chacon-Rodriguez, Roberto Molina-Robles, Reinaldo Castro-Gonzalez, Egdar Solera-Bolanos, Gabriel Madrigal-Boza, Marco Oviedo-Hernández, Diego Salazar-Sibaja, Dayhana Sanchez-Jimenez, Melissa Fonseca-Rodriguez, Johan Arrieta-Solorzano, Renato Rimolo-Donadio, Alfredo Arnaud, Matías R. Miguez, Joel Gak |
Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Hiroaki Kaneko, Akinori Kanasugi |
An integrated machine code monitor for a RISC-V processor on an FPGA. |
Artif. Life Robotics |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Mitul S. Nagar, Haresh A. Suthar, Chintan Panchal |
RISC micrprocessor verification. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise |
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue |
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Ömer Faruk Irmak, Arda Yurdakul |
An Embedded RISC-V Core with Fast Modular Multiplication. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Junya Miura, Hiromu Miyazaki, Kenji Kise |
A portable and Linux capable RISC-V computer system in Verilog HDL. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Florian Zaruba, Fabian Schuiki, Luca Benini |
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard |
HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim |
Vortex: OpenCL Compatible RISC-V GPGPU. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Garrett Gu, Hovav Shacham |
Return-Oriented Programming in RISC-V. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Marius Monton |
A RISC-V SystemC-TLM simulator. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise |
RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi |
Efficient Sealable Protection Keys for RISC-V. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers |
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Leonardo Ravaglia, Manuele Rusci, Alessandro Capotondi, Francesco Conti 0001, Lorenzo Pellegrini, Vincenzo Lomonaco, Davide Maltoni, Luca Benini |
Memory-Latency-Accuracy Trade-offs for Continual Learning on a RISC-V Extreme-Edge Node. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini |
Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos |
Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser |
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Xuan Guo, Robert D. Mullins |
Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Takuto Kanamori, Hiromu Miyazaki, Kenji Kise |
RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
13 | Samuel Greengard |
Will RISC-V revolutionize computing? |
Commun. ACM |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise |
RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining. |
IEICE Trans. Inf. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Tim Fritzmann, Georg Sigl, Johanna Sepúlveda |
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. |
IACR Trans. Cryptogr. Hardw. Embed. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Erdem Alkim, Hülya Evkan, Norman Lahr, Ruben Niederhagen, Richard Petri 0001 |
ISA Extensions for Finite Field Arithmetic Accelerating Kyber and NewHope on RISC-V. |
IACR Trans. Cryptogr. Hardw. Embed. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
13 | Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf |
The design of scalar AES Instruction Set Extensions for RISC-V. |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
|
13 | Tim Fritzmann, Georg Sigl, Johanna Sepúlveda |
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
|
13 | Latif Akçay, Berna Örs Yalçin |
Comparison of RISC-V and transport triggered architectures for a post-quantum cryptography application. |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
|
13 | Erdem Alkim, Hülya Evkan, Norman Lahr, Ruben Niederhagen, Richard Petri 0001 |
ISA Extensions for Finite Field Arithmetic - Accelerating Kyber and NewHope on RISC-V. |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
|
13 | Markku-Juhani O. Saarinen, G. Richard Newell, Ben Marshall |
Building a Modern TRNG: An Entropy Source Interface for RISC-V. |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
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13 | Fabio Campos, Lars Jellema, Mauk Lemmen, Lars Müller 0006, Amber Sprenkels, Benoît Viguier |
Assembly or Optimized C for Lightweight Cryptography on RISC-V? |
IACR Cryptol. ePrint Arch. |
2020 |
DBLP BibTeX RDF |
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