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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 851 occurrences of 523 keywords
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Results
Found 2201 publication records. Showing 2201 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
13 | Colin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woo-Rham Bae, Sean Huang, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic |
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2021, San Francisco, CA, USA, February 13-22, 2021, pp. 58-60, 2021, IEEE, 978-1-7281-9549-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Francesco Daghero, Chen Xie, Daniele Jahier Pagliari, Alessio Burrello, Marco Castellano, Luca Gandolfi, Andrea Calimera, Enrico Macii, Massimo Poncino |
Ultra-compact binary neural networks for human activity recognition on RISC-V processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021, pp. 3-11, 2021, ACM, 978-1-4503-8404-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Alexander Dörflinger, Mark Albers, Benedikt Kleinbeck, Yejun Guan, Harald Michalik, Raphael Klink, Christopher Blochwitz, Anouar Nechi, Mladen Berekovic |
A comparative survey of open-source application-class RISC-V processor implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021, pp. 12-20, 2021, ACM, 978-1-4503-8404-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Alexander Hepp, Georg Sigl |
Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CF ![In: CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021, pp. 213-220, 2021, ACM, 978-1-4503-8404-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Nazareno Bruschi, Germain Haugou, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 39th IEEE International Conference on Computer Design, ICCD 2021, Storrs, CT, USA, October 24-27, 2021, pp. 409-416, 2021, IEEE, 978-1-6654-3219-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard |
HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaCCS ![In: ASIA CCS '21: ACM Asia Conference on Computer and Communications Security, Virtual Event, Hong Kong, June 7-11, 2021., pp. 187-199, 2021, ACM, 978-1-4503-8287-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Birk Martin Magnussen, Tohma Kawasumi, Hiroki Mikami, Keiji Kimura, Hironori Kasahara |
Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing - 34th International Workshop, LCPC 2021, Newark, DE, USA, October 13-14, 2021, Revised Selected Papers, pp. 50-64, 2021, Springer, 978-3-030-99371-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Lorenzo Lamberti, Manuele Rusci, Marco Fariselli, Francesco Paci, Luca Benini |
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David |
RISC-V Barrel Processor for Deep Neural Network Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini |
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Camilo Rojas, Hanssel Morales, Elkim Roa |
A Low-Cost Bug Hunting Verification Methodology for RISC-V-Based Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Süleyman Savas, Endri Bezati, Jörn W. Janneck |
Generating hardware and software for RISC-V cores generated with Rocket Chip generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021, pp. 89-94, 2021, IEEE, 978-1-6654-2931-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Rei Watanabe, Jubee Tada, Keiichi Sato |
An Implementation of a World Grid Square Codes Generator on a RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANDAR (Workshops) ![In: Ninth International Symposium on Computing and Networking, CANDAR 2021 - Workshops, Matsue, Japan, 23-26 November 2021, pp. 309-312, 2021, IEEE, 978-1-6654-1218-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Dai-Duong Tran, Thi Giang Truong, Truong Giang Do, The Duc Do |
Risc-V Random Test Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACOMP ![In: 15th International Conference on Advanced Computing and Applications, ACOMP 2021, Ho Chi Minh City, Vietnam, November 24-26, 2021, pp. 150-155, 2021, IEEE, 978-1-6654-0639-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ben Marshall, Daniel Page, Thinh Hung Pham |
A lightweight ISE for ChaCha on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 25-32, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Mingjian Sun, Yuan Li, Song Chen 0001, Yi Kang |
A Low Power Branch Prediction for Deep Learning on RISC-V Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 203-206, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Shihang Wang, Jianghan Zhu, Qi Wang 0051, Can He, Terry Tao Ye |
Customized Instruction on RISC-V for Winograd-Based Convolution Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 65-68, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Alexander Aponte-Moreno, Felipe Restrepo-Calle, Cesar Augusto Pedraza |
Reliability Evaluation of RISC-V and ARM Microprocessors Through a New Fault Injection Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-2057-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Tobias Faller, Philipp Scholl, Tobias Paxian, Bernd Becker 0001 |
Towards SAT-Based SBST Generation for RISC-V Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 22nd IEEE Latin American Test Symposium, LATS 2021, Punta del Este, Uruguay, October 27-29, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-2057-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Marouene Boubakri, Fausto Chiatante, Belhassen Zouari |
Open Portable Trusted Execution Environment framework for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: 19th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2021, Shenyang, China, October 20-22, 2021, pp. 1-8, 2021, IEEE, 978-1-6654-0036-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib |
Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '21: Great Lakes Symposium on VLSI 2021, Virtual Event, USA, June 22-25, 2021., pp. 409-414, 2021, ACM, 978-1-4503-8393-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Xinyu Qin, Xudong Liu, Jun Han 0003 |
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Jiyuan Bai, Xiang Wang, Zikang Zhang, Chang Cai, Gengsheng Chen |
A Hierarchical Fault Injection System for RISC-V Processors Targeting Single Event Upsets in Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Austin Harris 0001, Tarunesh Verma, Shijia Wei, Lauren Biernacki, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd M. Austin |
Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2021, Tysons Corner, VA, USA, December 12-15, 2021, pp. 226-238, 2021, IEEE, 978-1-6654-1357-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri |
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1609-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Zahra Kazemi, Amin Norollah, Afef Kchaou, Mahdi Fazeli, David Hély, Vincent Beroulle |
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1609-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Corrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone |
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1609-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Sébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain |
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-1609-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
13 | Mohd Nizam Mohd Najib, Dzati Athiar Ramli |
Analysis of Smart IoT Portal Based on Advanced RISC Machines (ARM) Processor for Fanless Heat Maintenance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RoViSP ![In: Proceedings of the 11th International Conference on Robotics, Vision, Signal Processing and Power Applications - Enhancing Research and Innovation through the Fourth Industrial Revolution, RoViSP 2021, Penang, Malaysia, 5-6 April 2021., pp. 612-617, 2021, Springer, 978-981-16-8128-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sabine Pircher, Johannes Geier, Alexander Zeh, Daniel Mueller-Gritschneder |
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 401-407, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Avani Dave, Nilanjan Banerjee, Chintan Patel |
CARE: Lightweight Attack Resilient Secure Boot Architecture with Onboard Recovery for RISC-V based SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 516-521, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jaekyung Im, Seokhyeong Kang |
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 59-60, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham |
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 375-376, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Wooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han |
K-means Clustering-specific Lightweight RISC-V processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021, pp. 391-392, 2021, IEEE, 978-1-6654-0174-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Stefan Steinegger, David Schrammel, Samuel Weiser, Pascal Nasahl, Stefan Mangard |
SERVAS! Secure Enclaves via RISC-V Authenticryption Shield. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESORICS (2) ![In: Computer Security - ESORICS 2021 - 26th European Symposium on Research in Computer Security, Darmstadt, Germany, October 4-8, 2021, Proceedings, Part II, pp. 370-391, 2021, Springer, 978-3-030-88427-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Peter Sewell |
Engineering with Full-scale Formal Architecture: Morello, CHERI, Armv8-A, and RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer Aided Design, FMCAD 2021, New Haven, CT, USA, October 19-22, 2021, pp. 12, 2021, IEEE, 978-3-85448-046-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Dapeng Gao, Tom Melham |
End-to-End Formal Verification of a RISC-V Processor Extended with Capability Pointers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer Aided Design, FMCAD 2021, New Haven, CT, USA, October 19-22, 2021, pp. 24-33, 2021, IEEE, 978-3-85448-046-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Carlton Shepherd, Konstantinos Markantonakis, Georges-Axel Jaloyan |
LIRA-V: Lightweight Remote Attestation for Constrained RISC-V Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SP (Workshops) ![In: IEEE Security and Privacy Workshops, SP Workshops 2021, San Francisco, CA, USA, May 27, 2021, pp. 221-227, 2021, IEEE, 978-1-6654-3732-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su |
Implement 32-bit RISC-V Architecture Processor using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2021, Hualien City, Taiwan, November 16-19, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-1951-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Sarah L. Harris, David M. Harris |
Digital Design and RISC-V Computer Architecture Textbook. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: ACM/IEEE Workshop on Computer Architecture Education, WCAE 2021, Raleigh, NC, USA, June 17, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-0001-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Stephen A. Zekany, Jielun Tan, James A. Connolly |
Teaching Out-of-Order Processor Design with the RISC-V ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: ACM/IEEE Workshop on Computer Architecture Education, WCAE 2021, Raleigh, NC, USA, June 17, 2021, pp. 1-8, 2021, IEEE, 978-1-6654-0001-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | P. S. Babu, Snehashri Sivaraman, Deepa N. Sarma, Tripti S. Warrier |
Evaluation of Bit Manipulation Instructions in Optimization of Size and Speed in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 54-59, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers |
ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, VLSID 2021, Guwahati, India, February 20-24, 2021, pp. 270-275, 2021, IEEE, 978-1-6654-4087-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Shota Matsuno, Masashi Tawada, Nozomu Togawa |
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2021, Las Vegas, NV, USA, January 10-12, 2021, pp. 1-6, 2021, IEEE, 978-1-7281-9766-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Alessandro Cilardo |
Memory Encryption Support for an FPGA-based RISC-V Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, June 28-30, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-3654-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Luca Zulberti, Pietro Nannipieri, Luca Fanucci |
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, June 28-30, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-3654-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo |
Characterization of a RISC-V System-on-Chip under Neutron Radiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2021, Montpellier, France, June 28-30, 2021, pp. 1-6, 2021, IEEE, 978-1-6654-3654-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Salvatore Di Girolamo, Andreas Kurth, Alexandru Calotoiu, Thomas Benz, Timo Schneider, Jakub Beránek, Luca Benini, Torsten Hoefler |
A RISC-V in-network accelerator for flexible high-performance low-power packet processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Virtual Event / Valencia, Spain, June 14-18, 2021, pp. 958-971, 2021, IEEE, 978-1-6654-3333-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Eike Hahn, Dominik Kalinowski, Waldemar Müller, Mohamed Abdelawwad, Josef Börcsök |
RISC-V Based Safety System-on-Chip with Hardware Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CECNet ![In: Proceedings of CECNet 2021 - The 11th International Conference on Electronics, Communications and Networks (CECNet), November 18-21, 2021, Virtual Event / Beijing, China, pp. 362-368, 2021, IOS Press, 978-1-64368-240-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Brad Green, Dillon Todd, Jon C. Calhoun, Melissa C. Smith |
TIGRA: A Tightly Integrated Generic RISC-V Accelerator Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: IEEE International Conference on Cluster Computing, CLUSTER 2021, Portland, OR, USA, September 7-10, 2021, pp. 779-782, 2021, IEEE, 978-1-7281-9666-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Hsu-Kang Dow, Tuo Li 0001, William Miles, Sri Parameswaran |
SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, pp. 289-294, 2021, IEEE, 978-1-6654-3274-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Xinchao Zhong, Chiu-Wing Sham, Longyu Ma |
A Highly Integrated RISC-V Based SoC for On-Board Unit in ETC System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCCE ![In: 10th IEEE Global Conference on Consumer Electronics, GCCE 2021, Kyoto, Japan, October 12-15, 2021, pp. 302-303, 2021, IEEE, 978-1-6654-3676-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Erfan Gholizadehazari, Tuba Ayhan, Berna Örs |
An FPGA Implementation of a RISC-V Based SoC System for Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIU ![In: 29th Signal Processing and Communications Applications Conference, SIU 2021, Istanbul, Turkey, June 9-11, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3649-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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13 | Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz, Sung Kyu Lim |
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 19(1), pp. 51-54, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Daniel Petrisko, Farzam Gilani, Mark Wyse, Dai Cheol Jung, Scott Davidson 0004, Paul Gao 0001, Chun Zhao, Zahra Azad, Sadullah Canakci, Bandhav Veluri, Tavio Guarino, Ajay Joshi, Mark Oskin, Michael Bedford Taylor |
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 40(4), pp. 93-102, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Nguyen My Qui, Chang Hong Lin, Poki Chen |
Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 172996-173007, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Ahmed Kamaleldin, Salma Hesham, Diana Göhringer |
Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 148812-148826, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini |
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(2), pp. 530-543, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | John Charles Wright, Colin Schmidt 0001, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic |
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(12), pp. 2721-2725, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Vinay B. Y. Kumar, Suman Deb, Naina Gupta 0001, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson |
Towards Designing a Secure RISC-V System-on-Chip: ITUS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Hardw. Syst. Secur. ![In: J. Hardw. Syst. Secur. 4(4), pp. 329-342, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Xiaoyang Xie, Zhihan Fang, Yang Wang 0015, Fan Zhang 0019, Desheng Zhang |
RISC: Resource-Constrained Urban Sensing Task Scheduling Based on Commercial Fleets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. ![In: Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 4(2), pp. 62:1-62:20, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Seungmin Jung |
Image Processor and RISC MCU Embedded Single Chip Fingerprint Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sens. Actuator Networks ![In: J. Sens. Actuator Networks 9(4), pp. 51, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Yuzhi Zhou, Xi Jin 0002, Tian Xiang, Daolu Zha |
Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 77, pp. 103140, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Asmit De, Aditya Basu, Swaroop Ghosh, Trent Jaeger |
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12), pp. 4453-4465, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Isaías B. Felzmann, João Fabrício Filho, Lucas Francisco Wanner |
Risk-5: Controlled Approximations for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11), pp. 4052-4063, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Cristóbal Ramírez, César-Alejandro Hernández-Calderón, Oscar Palomar, Osman S. Unsal, Marco Antonio Ramírez, Adrián Cristal |
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 17(4), pp. 38:1-38:30, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik |
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 36(1), pp. 87-103, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Ronny García-Ramírez, Alfonso Chacon-Rodriguez, Roberto Molina-Robles, Reinaldo Castro-Gonzalez, Egdar Solera-Bolanos, Gabriel Madrigal-Boza, Marco Oviedo-Hernández, Diego Salazar-Sibaja, Dayhana Sanchez-Jimenez, Melissa Fonseca-Rodriguez, Johan Arrieta-Solorzano, Renato Rimolo-Donadio, Alfredo Arnaud, Matías R. Miguez, Joel Gak |
Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 98, pp. 104753, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Hiroaki Kaneko, Akinori Kanasugi |
An integrated machine code monitor for a RISC-V processor on an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Life Robotics ![In: Artif. Life Robotics 25(3), pp. 427-433, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Mitul S. Nagar, Haresh A. Suthar, Chintan Panchal |
RISC micrprocessor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.00223, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2011.14325, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise |
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.03568, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue |
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2003.05315, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Ömer Faruk Irmak, Arda Yurdakul |
An Embedded RISC-V Core with Fast Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.14685, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Junya Miura, Hiromu Miyazaki, Kenji Kise |
A portable and Linux capable RISC-V computer system in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.03576, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Florian Zaruba, Fabian Schuiki, Luca Benini |
Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2008.06502, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Pascal Nasahl, Robert Schilling, Mario Werner, Stefan Mangard |
HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.05262, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim |
Vortex: OpenCL Compatible RISC-V GPGPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.12151, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Garrett Gu, Hovav Shacham |
Return-Oriented Programming in RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2007.14995, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Marius Monton |
A RISC-V SystemC-TLM simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2010.10119, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Md. Ashraful Islam, Hiromu Miyazaki, Kenji Kise |
RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2010.16171, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi |
Efficient Sealable Protection Keys for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2012.02715, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Gianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi |
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2010.04073, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers |
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2006.00364, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Leonardo Ravaglia, Manuele Rusci, Alessandro Capotondi, Francesco Conti 0001, Lorenzo Pellegrini, Vincenzo Lomonaco, Davide Maltoni, Luca Benini |
Memory-Latency-Accuracy Trade-offs for Continual Learning on a RISC-V Extreme-Edge Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2007.13631, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini |
Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2006.14256, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Nikolaos Charalampos Papadopoulos, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Dionisios N. Pnevmatikatos |
Enabling Virtual Memory Research on RISC-V with a Configurable TLB Hierarchy for the Rocket Chip Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2009.07723, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser |
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2005.02193, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Xuan Guo, Robert D. Mullins |
Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2005.11357, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Takuto Kanamori, Hiromu Miyazaki, Kenji Kise |
RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2011.11246, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Samuel Greengard |
Will RISC-V revolutionize computing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 63(5), pp. 30-32, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Hiromu Miyazaki, Takuto Kanamori, Md. Ashraful Islam, Kenji Kise |
RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 103-D(12), pp. 2494-2503, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Tim Fritzmann, Georg Sigl, Johanna Sepúlveda |
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(4), pp. 239-280, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Erdem Alkim, Hülya Evkan, Norman Lahr, Ruben Niederhagen, Richard Petri 0001 |
ISA Extensions for Finite Field Arithmetic Accelerating Kyber and NewHope on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(3), pp. 219-242, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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13 | Ben Marshall, G. Richard Newell, Dan Page, Markku-Juhani O. Saarinen, Claire Wolf |
The design of scalar AES Instruction Set Extensions for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 930, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Tim Fritzmann, Georg Sigl, Johanna Sepúlveda |
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 446, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Latif Akçay, Berna Örs Yalçin |
Comparison of RISC-V and transport triggered architectures for a post-quantum cryptography application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 746, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Erdem Alkim, Hülya Evkan, Norman Lahr, Ruben Niederhagen, Richard Petri 0001 |
ISA Extensions for Finite Field Arithmetic - Accelerating Kyber and NewHope on RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 49, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Markku-Juhani O. Saarinen, G. Richard Newell, Ben Marshall |
Building a Modern TRNG: An Entropy Source Interface for RISC-V. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 866, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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13 | Fabio Campos, Lars Jellema, Mauk Lemmen, Lars Müller 0006, Amber Sprenkels, Benoît Viguier |
Assembly or Optimized C for Lightweight Cryptography on RISC-V? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2020, pp. 836, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
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