Search results for "delay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan	Robust analytical gate delay modeling for low voltage circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
17	Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.	FPL	2006	DBLP DOI BibTeX RDF
17	Kou Yamada, Hiroshi Takenaga	The Parametrization of All Stabilizing Smith Predictors for Certain Class of Non-Minimum Phase Time-Delay Plants.	ICICIC (1)	2006	DBLP DOI BibTeX RDF
17	Stijn De Vuyst, Sabine Wittevrongel, Herwig Bruneel	Parametric delay differentiation between packet flows using multiple reserved spaces.	VALUETOOLS	2006	DBLP DOI BibTeX RDF
17	Xiaomin Dong, Miao Yu, Changrong Liao, Weimin Chen, Hong Hui Zhang, Shanglian Huang	Adaptive Fuzzy Neural Network Control for Transient Dynamics of Magneto-rheological Suspension with Time-Delay.	ISNN (2)	2006	DBLP DOI BibTeX RDF
17	Run-Nian Ma, Guoqiang Bai 0001	Stability Conditions for Discrete Hopfield Neural Networks with Delay.	ICIC (1)	2006	DBLP DOI BibTeX RDF
17	Dan Jurca, Pascal Frossard	Media Streaming with Conservative Delay on Variable Rate Channels.	ICME	2006	DBLP DOI BibTeX RDF
17	Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
17	Vasilis F. Pavlidis, Eby G. Friedman	Via placement for minimum interconnect delay in three-dimensional (3D) circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Sang-Seon Byun, Chuck Yoo	Reducing Delivery Delay in HRM Tree.	ICCSA (2)	2006	DBLP DOI BibTeX RDF
17	Praveen Ghanta, Sarma B. K. Vrudhula	Variational Interconnect Delay Metrics for Statistical Timing Analysis.	ISQED	2006	DBLP DOI BibTeX RDF
17	Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski	Delay Fault Diagnosis for Non-Robust Test.	ISQED	2006	DBLP DOI BibTeX RDF
17	Zhengang Pan, Jingxiu Liu, Lan Chen, Kenichi Higuchi, Mamoru Sawahashi	Multi-degree Random Cyclic Delay Diversity in MISO Systems with Frequency-Domain Scheduling.	APCCAS	2006	DBLP DOI BibTeX RDF
17	Run-Nian Ma, Guoqiang Bai 0001	Convergence Study of Discrete Neural Networks with Delay.	ICONIP (1)	2006	DBLP DOI BibTeX RDF
17	Wei Luo, Krishna Balachandran, Sanjiv Nanda, K. K. Chang	Delay analysis of selective-repeat ARQ with applications to link adaptation in wireless packet data systems.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
17	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Gate oxide leakage and delay tradeoffs for dual-Tox circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
17	Xiang Lu, Zhuo Li 0001, Wangqi Qiu, D. M. H. Walker, Weiping Shi	Longest-path selection for delay test under process variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Delay-fault diagnosis using timing information.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
17	Sunthiti Patchararungruang, Saman K. Halgamuge, Nirmala Shenoy	Optimized rule-based delay proportion adjustment for proportional differentiated services.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
17	Hyung Seok Kim, Tarek F. Abdelzaher, Wook Hyun Kwon	Dynamic delay-constrained minimum-energy dissemination in wireless sensor networks.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Sensor network, multicast, energy
17	Heng Wang, Narayan B. Mandayam	Opportunistic file transfer over a fading channel under energy and delay constraints.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
17	Trong Thua Huynh, Choong Seon Hong	An Energy*Delay Efficient Routing Scheme for Wireless Sensor Networks.	MMNS	2005	DBLP DOI BibTeX RDF
17	Haihua Yan, Adit D. Singh, Gefu Xu	Delay Defect Characterization Using Low Voltage Test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	T. M. Mak	Limitation of structural scan delay test.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
17	Gaoming Huang, Luxi Yang, Zhenya He	Application of Blind Source Separation to Time Delay Estimation in Interference Environments.	ISNN (2)	2005	DBLP DOI BibTeX RDF
17	Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
17	Chien-Cheng Tseng	Improved design of fractional order differentiator using fractional sample delay.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
17	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	Estimated Path Selection for the Delay Constrained Least Cost Path.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
17	Irith Pomeranz, Sudhakar M. Reddy	Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.	VLSI Design	2005	DBLP DOI BibTeX RDF
17	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Sequential delay budgeting with interconnect prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
17	Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo	Probabilistic crosstalk delay estimation for ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	Andrew B. Kahng, Xu Xu 0001	Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
17	William S. Evans, David G. Kirkpatrick	Optimally scheduling video-on-demand to minimize delay when server and receiver bandwidth may differ.	SODA	2004	DBLP BibTeX RDF
17	Runnian Ma, Youmin Xi, Hangshan Gao	Stability of Discrete Hopfield Networks with Delay in Serial Mode.	ISNN (1)	2004	DBLP DOI BibTeX RDF
17	Zaiping Chen, Liang Liu, Jiangfeng Zhang	Observer based networked control systems with network-induced time delay.	SMC (4)	2004	DBLP DOI BibTeX RDF
17	Daisuke Maruyama, Akira Kanuma, Takashi Mochiyama, Hiroaki Komatsu, Yaroku Sugiyama, Noriyuki Ito	Detection of multiple transitions in delay fault test of SPARC64 microprocessor.	ICCAD	2004	DBLP DOI BibTeX RDF
17	Moonseong Kim, Young-Cheol Bang, Hyunseung Choo	On Balancing Delay and Cost for Routing Paths.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
17	Haining Liu, Magda El Zarki	Adaptive Delay and Synchronization Control for Wi-Fi Based AV Conferencing.	QSHINE	2004	DBLP DOI BibTeX RDF
17	Goran Molnar, Mladen Vucic	Design of constant-delay systems based on symmetry of time-domain response.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
17	Young-Cheol Bang, Inki Hong, Sungchang Lee, ByungJun Ahn	On Algorithms for Minimum-Cost Quickest Paths with Multiple Delay-Bounds.	ICCSA (1)	2004	DBLP DOI BibTeX RDF
17	M. L. Yan, C. K. Li	Delay-Differentiable Fair Queueing (D2FQ): A Low Complexity Scheduling Algorithm for Packet-Switched Networks.	AINA (1)	2004	DBLP DOI BibTeX RDF
17	Shahdad Irajpour, Sandeep K. Gupta 0001, Melvin A. Breuer	Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.	ITC	2004	DBLP DOI BibTeX RDF
17	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
17	Madhu Mutyam	Preventing Crosstalk Delay using Fibonacci Representation.	VLSI Design	2004	DBLP DOI BibTeX RDF
17	Puneet Gupta 0001, Andrew B. Kahng	Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling.	VLSI Design	2004	DBLP DOI BibTeX RDF
17	N. V. Arvind, K. A. Rajagopal, H. S. Ajith, Das Suparna	Path Based Approach for Crosstalk Delay Analysis.	VLSI Design	2004	DBLP DOI BibTeX RDF
17	Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu 0001, Sani R. Nassif, Sarma B. K. Vrudhula	Variational delay metrics for interconnect timing analysis.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design
17	Qiong Li, David L. Mills	The Implication of Short-Range Dependency on Delay Variation Measurement.	NCA	2003	DBLP DOI BibTeX RDF
17	Ulrich Seidl, Klaus Eckl, Frank M. Johannes	Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information.	DATE	2003	DBLP DOI BibTeX RDF
17	Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman	Reduced Delay Uncertainty in High Performance Clock Distribution Networks.	DATE	2003	DBLP DOI BibTeX RDF
17	Huawei Li 0001, Yue Zhang, Xiaowei Li 0001	Delay Test Pattern Generation Considering Crosstalk-Induced Effects.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
17	Venkatesan Rajappan, Sachin S. Sapatnekar	An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk.	ICCD	2003	DBLP DOI BibTeX RDF
17	Lai Yin Ngan, Yuntao Wu, Hing-Cheung So, Pak-Chung Ching, Siu Wa Lee	Joint time delay and pitch estimation for speaker localization.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
17	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu	A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
17	Sayed Vahid Azhari, Nasser Yazdani, Ali Mohammad Zareh Bidoki	Providing Delay Guarantee in Input Queued Switches: A Comparative Analysis of Scheduling Algorithms.	ICOIN	2003	DBLP DOI BibTeX RDF
17	SangSik Yoon, Deokjai Choi	A Constrained Multi-path Finding Mechanism Considering Available Bandwidth and Delay of MPLS LSP.	ICOIN	2003	DBLP DOI BibTeX RDF
17	Arun Krishnamachary, Jacob A. Abraham	Effects of Multi-cycle Sensitization on Delay Tests.	VLSI Design	2003	DBLP DOI BibTeX RDF
17	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung	A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.	IWSOC	2003	DBLP DOI BibTeX RDF
17	Constantinos Dovrolis, Dimitrios Stiliadis, Parameswaran Ramanathan	Proportional differentiated services: delay differentiation and packet scheduling.	IEEE/ACM Trans. Netw.	2002	DBLP DOI BibTeX RDF	Dynamic priorities, resource management algorithms, quality of service
17	Mustafa Türkboylari, Vijay K. Madisetti	Effect of handoff delay on the system performance of TDMA cellular systems.	MWCN	2002	DBLP DOI BibTeX RDF
17	Hasan Ural, Keqin Zhu	Fault Recovery for a Distributed SP-Based Delay Constrained Multicast Routing Algorithm.	IPDPS	2002	DBLP DOI BibTeX RDF
17	Frank Liu 0001, Chandramouli V. Kashyap, Charles J. Alpert	A delay metric for RC circuits based on the Weibull distribution.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis	Multi-objective circuit partitioning for cutsize and path-based delay minimization.	ICCAD	2002	DBLP DOI BibTeX RDF
17	Cliff C. N. Sze, Ting-Chi Wang	Optimal circuit clustering with variable interconnect delay.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
17	Yuan-Cheng Lai, Wei-Hsi Li, Arthur Chang	A Novel Scheduler for the Proportional Delay Differentiation Model by Considering Packet Transmission Time.	ICOIN (1)	2002	DBLP DOI BibTeX RDF
17	Sung-Ho Hwang, Ki Jun Han	A Fast Access Scheme to Meet Delay Requirement for Wireless Access Network.	ADVIS	2002	DBLP DOI BibTeX RDF
17	Kazuhito Ito, Daisuke Suzuki	A high-level synthesis method for simultaneous placement and scheduling considering data communication delay.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
17	Sabine Bostelmann	Categorization of Time Delay by Means of Neural Networks.	Fuzzy Days	2001	DBLP DOI BibTeX RDF
17	Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo	Test Generation for Multiple-Threshold Gate-Delay Fault Model.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
17	Akihiko Machizawa, Kazunori Sugiura, Takahiro Komine, Haruo Okazawa, Shin-ichi Nakagawa	On the Delay and Quality of DV Transmission Systems Using ATM Networks.	ICOIN	2001	DBLP DOI BibTeX RDF
17	Róbert Szabó, Peter Barta, Felician Németh, József Bíró	Worst-Case Deterministic Delay Bounds for Arbitrary Weighted Generalized Processor Sharing Schedulers.	NETWORKING	2000	DBLP DOI BibTeX RDF
17	Tung Chong Wong, Jon W. Mark, Kee Chaing Chua	Delay jitter performance of video traffic in a cellular wireless ATM network.	WOWMOM	2000	DBLP DOI BibTeX RDF
17	Rajeev Murgai	Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization.	VLSI Design	2000	DBLP DOI BibTeX RDF
17	Soha Hassoun	Critical path analysis using a dynamically bounded delay model.	DAC	2000	DBLP DOI BibTeX RDF
17	Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar	Convex delay models for transistor sizing.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
17	Tomoyuki Yoda, Atsushi Takahashi 0001, Yoji Kajitani	Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.	ASP-DAC	1999	DBLP DOI BibTeX RDF
17	Antti Mäntyniemi, Timo Rahkonen, Juha Kostamovaara	A high resolution digital CMOS time-to-digital converter based on nested delay locked loops.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
17	Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi	S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
17	Jayabrata Ghosh-Dastidar, Nur A. Touba	Adaptive Techniques for Improving Delay Fault Diagnosis.	VTS	1999	DBLP DOI BibTeX RDF
17	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang	On circuit clustering for area/delay tradeoff under capacity and pin constraints.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
17	Cheng-Wen Wu, Chih-Yuang Su	A Probabilistic Model for Path Delay Faults.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
17	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
17	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer Insertion for Noise and Delay Optimization.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
17	Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez	A delay budgeting algorithm ensuring maximum flexibility in placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Hannah Honghua Yang, Martin D. F. Wong	Circuit clustering for delay minimization under area and pin constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Kwang-Ting Cheng, Hsi-Chuan Chen	Classification and identification of nonrobust untestable path delay faults.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri	NEST: a nonenumerative test generation method for path delay faults in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
17	Irith Pomeranz, Sudhakar M. Reddy	An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
17	Weiwei Mao, Michael D. Ciletti	Reducing correlation to improve coverage of delay faults in scan-path design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
17	Andrzej Krasniewski, Leszek B. Wronski	Coverage of Delay Faults: When 13% and 99% Mean the Same.	EDCC	1994	DBLP DOI BibTeX RDF
17	Andrew B. Kahng, Chung-Wen Albert Tsao	Low-cost single-layer clock trees with exact zero Elmore delay skew.	ICCAD	1994	DBLP DOI BibTeX RDF
17	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
17	Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang	Computation of floating mode delay in combinational circuits: practice and implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
17	Srinivas Devadas, Kurt Keutzer, Sharad Malik	Computation of floating mode delay in combinational circuits: theory and algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
17	Srinivas Devadas, Kurt Keutzer	Synthesis of robust delay-fault-testable circuits: theory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
17	Carlos H. Díaz, Sung-Mo Kang, Yusuf Leblebici	An accurate analytical delay model for BiCMOS driver circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
17	Subhash C. Agrawal, Ravi Ramaswamy	Analysis of the Resequencing Delay for M/M/m Systems.	SIGMETRICS	1987	DBLP DOI BibTeX RDF	SNA
17	Vaishali P. Sadaphal, Bijendra N. Jain	Random and Periodic Sleep Schedules for Target Detection in Sensor Networks.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	energy conservation, target detection, sleep schedule