Search results for "nanoscale"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Ernesto Sánchez 0001	Increasing reliability of safety critical applications through functional based solutions.	DTIS	2018	DBLP DOI BibTeX RDF
14	Dan Kreiser, Zoya Dyka, Ievgen Kabin, Peter Langendörfer	Low-energy key exchange for automation systems.	DTIS	2018	DBLP DOI BibTeX RDF
14	Zoran Stamenkovic	A novel MAC protocol for industrial WLAN: Hardware aspects.	DTIS	2018	DBLP DOI BibTeX RDF
14	Bastien Deveautour, Arnaud Virazel, Patrick Girard 0001, Serge Pravossoudovitch, Valentin Gherman	Is aproximate computing suitable for selective hardening of arithmetic circuits?	DTIS	2018	DBLP DOI BibTeX RDF
14	Ales Chvála, Lukás Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Satka, Michal Blaho, Dagmar Gregusová, Ján Kuzmík	Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell.	DTIS	2018	DBLP DOI BibTeX RDF
14	Carmen G. Almudéver, Nader Khammassi, Louis Hutin, Maud Vinet, Masoud Babaie, Fabio Sebastiano, Edoardo Charbon, Koen Bertels	Towards a scalable quantum computer.	DTIS	2018	DBLP DOI BibTeX RDF
14	Islam Ahmed, Hassan Mostafa, Ahmed Nader Mohieldin	Dynamic partial reconfiguration verification using assertion based verification.	DTIS	2018	DBLP DOI BibTeX RDF
14	Antoine Bouvet, Nicolas Bruneau, Adrien Facon, Sylvain Guilley, Damien Marion 0001	Give me your binary, I'll tell you if it leaks.	DTIS	2018	DBLP DOI BibTeX RDF
14	Hassen Aziza, Christian Dufaza, Annie Pérez	A configurable operational amplifier based on oxide resistive RAMs.	DTIS	2018	DBLP DOI BibTeX RDF
14	Adam Crha, Václav Simek, Richard Ruzicka	Towards novel format for representation of polymorphic circuits.	DTIS	2018	DBLP DOI BibTeX RDF
14	Tillmann Krauss, Frank Wessely, Udo Schwalke	Reconfigurable electrostatically doped 2.5-gate planar field-effect transistors for dopant-free CMOS.	DTIS	2018	DBLP DOI BibTeX RDF
14	Petr Fiser, Václav Simek	Optimum polymorphic circuits synthesis method.	DTIS	2018	DBLP DOI BibTeX RDF
14	Ievgen Kabin, Zoya Dyka, Dan Kreiser, Peter Langendörfer	Unified field multiplier for ECC: Inherent resistance against horizontal SCA attacks.	DTIS	2018	DBLP DOI BibTeX RDF
14	Michelangelo Grosso, Salvatore Rinaudo, Edoardo Patti, Andrea Acquaviva	An energy-autonomous wireless sensor network development platform.	DTIS	2018	DBLP DOI BibTeX RDF
14	Benjamin Willsch, Marius te Heesen, Julia Hauser, Stefan Dreiner, Holger Kappert, Holger Vogt	Evaluation of a median threshold based EEPROM-PUF concept implemented in a high temperature SOI CMOS technology.	DTIS	2018	DBLP DOI BibTeX RDF
14	Michael K. Tsiampas, Nestor E. Evmorfopoulos, Konstantis Daloukas, John Moondanos, Georgios I. Stamoulis	A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine.	DTIS	2018	DBLP DOI BibTeX RDF
14	Dennis Noll, Udo Schwalke	Ammonia sensors based on in situ fabricated nanocrystalline graphene field-effect devices.	DTIS	2018	DBLP DOI BibTeX RDF
14	Ioannis Voyiatzis, Constantinos Efstathiou, Cleo Sgouropoulou	Programmable logic for single-output functions.	DTIS	2018	DBLP DOI BibTeX RDF
14	Jing Yang, Nianxiong Tan, Ching-Kae Harris Tzou	A resource-efficient FFT/IFFT architecture for PRIME PLC systems.	DTIS	2018	DBLP DOI BibTeX RDF
14	Andrea Floridia, Davide Piumatti, Ernesto Sánchez 0001, Sergio de Luca, Alessandro Sansonetti	Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers.	DTIS	2018	DBLP DOI BibTeX RDF
14	Binghua Lu, Selina Sha, Jincheng Wang, Zhigao Zhang, Fanjin Meng, Dragon Hsu, Rick Fisette	The test cost reduction benefits of combining a hierarchical DFT methodology with EDT channel sharing - A case study.	DTIS	2018	DBLP DOI BibTeX RDF
14	Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre	SI ECCS: SECure context saving for IoT devices.	DTIS	2018	DBLP DOI BibTeX RDF
14	Lukás Kohútka, Viera Stopjaková	A novel hardware-accelerated real-time task scheduler based on robust earliest deadline algorithm.	DTIS	2018	DBLP DOI BibTeX RDF
14	Chithra Liz Palson, Deepti Das Krishna, Jimson Mathew, Babita Roslind Jose, Marco Ottavi, Vishal Gupta 0002	Memristor based adaptive impedance and frequency tuning network.	DTIS	2018	DBLP DOI BibTeX RDF
14	Ramy Ahmed, Hassan Mostafa, Ahmed H. Khalil	Impact of dynamic partial reconfiguration on CONNECT Network-on-Chip for FPGAs.	DTIS	2018	DBLP DOI BibTeX RDF
14	Emna Farjallah, Valentin Gherman, Jean-Marc Armani, Luigi Dilillo	Evaluation of the temperature influence on SEU vulnerability of DICE and 6T-SRAM cells.	DTIS	2018	DBLP DOI BibTeX RDF
14	Andrzej Daniluk	RHEED intensities from two-dimensional heteroepitaxial nanoscale systems of GaN on a 3C-SiC(111) surface.	Comput. Phys. Commun.	2017	DBLP DOI BibTeX RDF
14	Yaakov Mandelbaum, Ilan Gadasi, Avraham Chelly, Zeev Zalevsky, Avi Karsenty	Small Signals' Study of Thermal Induced Current in Nanoscale SOI Sensor.	J. Sensors	2017	DBLP DOI BibTeX RDF
14	Yaakov Mandelbaum, Ariel Zev, Avraham Chelly, Zeev Zalevsky, Avi Karsenty	Study of the Photo- and Thermoactivation Mechanisms in Nanoscale SOI Modulator.	J. Sensors	2017	DBLP DOI BibTeX RDF
14	Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang	Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Jing Guo 0004, Lei Zhu 0004, Wenyi Liu, Hai Huang, Shanshan Liu 0001, Tianqi Wang, Liyi Xiao, Zhigang Mao	Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Karsten Beckmann, Harika Manem, Nathaniel C. Cady	Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices.	IEEE Trans. Emerg. Top. Comput.	2017	DBLP DOI BibTeX RDF
14	Bernd Rieger, Sjoerd Stallinga	Data Fusion at the Nanoscale: Imaging at Resolutions Better than Wavelength/100.	ERCIM News	2017	DBLP BibTeX RDF
14	Toufik Bentrcia, Fayçal Djeffal, Elasaad Chebaki	Approach for designing and modelling of nanoscale DG MOSFET devices using Kriging metamodelling technique.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
14	Yan Zhou, Jibin Li 0001	Exact Solutions and Dynamics of the Raman Soliton Model in Nanoscale Optical Waveguides, with Metamaterials, Having Polynomial Law Nonlinearity.	Int. J. Bifurc. Chaos	2017	DBLP DOI BibTeX RDF
14	Qingcheng Yang, Albert C. To	Multiresolution molecular mechanics: Surface effects in nanoscale materials.	J. Comput. Phys.	2017	DBLP DOI BibTeX RDF
14	Sedigheh Farhadtoosky, Ali Jahanian 0001	Customized Placement Algorithm of Nanoscale DNA Logic Circuits.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
14	Daniel Eth	The Technological Landscape Affecting Artificial General Intelligence and the Importance of Nanoscale Neural Probes.	Informatica (Slovenia)	2017	DBLP BibTeX RDF
14	Rishab Mehra, Vikash Kumar, Aminul Islam 0002, Brajesh Kumar Kaushik	Variation-aware widely tunable nanoscale design of CMOS active inductor-based RF bandpass filter.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
14	Aibin Yan, Zhengfeng Huang, Xiangsheng Fang, Yiming Ouyang, Honghui Deng	Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Jacob Torrejon, Mathieu Riou, Flavio Abreu Araujo, Sumito Tsunegi, Guru Khalsa, Damien Querlioz, Paolo Bortolotti, Vincent Cros, Akio Fukushima, Hitoshi Kubota, Shinji Yuasa, Mark D. Stiles, Julie Grollier	Neuromorphic computing with nanoscale spintronic oscillators.	CoRR	2017	DBLP BibTeX RDF
14	Burhan Gulbahar, Gorkem Memisoglu	CSSTag: Optical Nanoscale Radar and Particle Tracking for In-Body and Microfluidic Systems with Vibrating Graphene and Resonance Energy Transfer.	CoRR	2017	DBLP BibTeX RDF
14	Ramin Rajaei	Highly reliable and low-power magnetic full-adder designs for nanoscale technologies.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Meng Chuan Lee, Hin Yong Wong	Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Qi-Lin Gu, Peng Zhang, Yi Ru, Hao Song, Wen-Sheng Zhao, Wen-Yan Yin	A comparative study on electrothermal characteristics of nanoscale multiple gate MOSFETs.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Andras Dezso, George Kaptay	On the Configurational Entropy of Nanoscale Solutions for More Accurate Surface and Bulk Nano-Thermodynamic Calculations.	Entropy	2017	DBLP DOI BibTeX RDF
14	Tiefeng Peng, Qibin Li, Longhua Xu, Chao He, Liqun Luo	Surface Interaction of Nanoscale Water Film with SDS from Computational Simulation and Film Thermodynamics.	Entropy	2017	DBLP DOI BibTeX RDF
14	Dogu Arifler	Connectivity Properties of Free Diffusion-Based Molecular Nanoscale Communication Networks.	IEEE Trans. Commun.	2017	DBLP DOI BibTeX RDF
14	Dongyeob Shin, Jongsun Park 0001, Jangwon Park, Somnath Paul, Swarup Bhunia	Adaptive ECC for Tailored Protection of Nanoscale Memory.	IEEE Des. Test	2017	DBLP DOI BibTeX RDF
14	Chien Y. Lin, Jung Y. Huang, Leu-Wei Lo	Depicting Binding-Mediated Translocation of HIV-1 Tat Peptides in Living Cells with Nanoscale Pens of Tat-Conjugated Quantum Dots.	Sensors	2017	DBLP DOI BibTeX RDF
14	Stephen F. Bush	Interoperable Nanoscale Communication [Future Directions].	IEEE Consumer Electron. Mag.	2017	DBLP DOI BibTeX RDF
14	Chun-Yu Lin 0001, Meng-Ting Lin	Improved stacked-diode ESD protection in nanoscale CMOS technology.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
14	Muhammad A. Elmessary, Daniel Nagy, Manuel Aldegunde, Antonio J. García-Loureiro, Karol Kalna	Study of strained effects in nanoscale GAA nanowire FETs using 3D Monte Carlo simulations.	ESSDERC	2017	DBLP DOI BibTeX RDF
14	George A. Stanciu, Denis E. Tranca, Stefan G. Stanciu, Catalin Stoichita, Radu Hristu	Nanoscale imaging by using label free microscopy techniques.	ICTON	2017	DBLP DOI BibTeX RDF
14	Misha Sumetsky	Optical and acoustic modes in a bottle resonator with nanoscale radius variation.	ICTON	2017	DBLP DOI BibTeX RDF
14	Thomas Hollstein, Jaan Raik, Sergei Kostin, Anton Tsertov, Ian O'Connor, Ricardo Reis 0001 (eds.)	VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability - 24th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016, Revised Selected Papers	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
14	Trang C. Mai, Tiep Minh Hoang, Hoang Duong Tuan, Marco Di Renzo, Trung Quang Duong	Modeling and Analysis of Interference for Diffusion-Based Nanoscale Networks with Spatially Distributed Transmitters.	VTC Spring	2017	DBLP DOI BibTeX RDF
14	Boliang Yu, Loriane Weber, Alexandra Pacureanu, Max Langer, Cécile Olivier, Peter Cloetens, Françoise Peyrin	Phase retrieval in 3D X-ray magnified phase nano CT: Imaging bone tissue at the nanoscale.	ISBI	2017	DBLP DOI BibTeX RDF
14	Francesco Maria Puglisi	Measuring and analyzing Random Telegraph Noise in Nanoscale Devices: The case of resistive random access memories.	NVMTS	2017	DBLP DOI BibTeX RDF
14	Burhan Gulbahar, Gorkem Memisoglu	Nanoscale optical communications modulator and acousto-optic transduction with vibrating graphene and resonance energy transfer.	ICC	2017	DBLP DOI BibTeX RDF
14	Pedram Johari, Josep Miquel Jornet	Nanoscale optical channel modeling for in vivo wireless nanosensor networks: A geometrical approach.	ICC	2017	DBLP DOI BibTeX RDF
14	Qun Jia, Chao Zhou 0002, Lu Deng, Zhangming Du, Zhiqiang Cao	Research on nanoscale displacement online modeling and control of PCA.	ROBIO	2017	DBLP DOI BibTeX RDF
14	Engin Afacan, Mustafa Berke Yelten, Günhan Dündar	Review: Analog design methodologies for reliability in nanoscale CMOS circuits.	SMACD	2017	DBLP DOI BibTeX RDF
14	Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, Pengpeng Ren, Yangyuan Wang, Siyu Liao, Chunyi Huang, Tianlei Guo, Alvin Chen, Jushan Xie, Ru Huang	Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.	ICCAD	2017	DBLP DOI BibTeX RDF
14		IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017	NANOARCH	2017	DBLP BibTeX RDF
14	Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram K. Krishnamurthy	Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies.	CICC	2017	DBLP DOI BibTeX RDF
14	Zhaoying Hu, Shu-Jen Han	Creating security primitive by nanoscale manipulation of carbon nanotubes.	HOST	2017	DBLP DOI BibTeX RDF
14	Rekib Uddin Ahmed, Prabir Saha	Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime.	iNIS	2017	DBLP DOI BibTeX RDF
14	Ming Zhu, Yingtao Jiang, Mei Yang, Xiaohang Wang 0001	Building temperature-insensitive nanoscale CMOS circuits with adaptive voltage power supplies.	CCECE	2017	DBLP DOI BibTeX RDF
14	Alan Davy, John F. Federici (eds.)	Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, NANOCOM 2017, Washington, DC, USA, September 27-29, 2017	NANOCOM	2017	DBLP DOI BibTeX RDF
14	Milena Djukanovic, Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti	Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications.	AFRICACRYPT	2017	DBLP DOI BibTeX RDF
14		12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, DTIS 2017, Palma de Mallorca, Spain, April 4-6, 2017	DTIS	2017	DBLP BibTeX RDF
14	Avhishek Chatterjee, Lav R. Varshney	Energy-reliability limits in nanoscale neural networks.	CISS	2017	DBLP DOI BibTeX RDF
14	Farnaz Niroui	Engineering at the limits of the nanoscale.		2017	RDF
14	Wafi Danesh, Mostafizur Rahman	Linear regression based multi-state logic decomposition approach for efficient hardware implementation.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Jiajun Shi, Mingyu Li, Csaba Andras Moritz	Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Sachin Bhat, Sourabh Kulkami, Jiajun Shi, Mingyu Li, Csaba Andras Moritz	SkyNet: Memristor-based 3D IC for artificial neural networks.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Zhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan	High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Mohammed Affan Zidan, YeonJoo Jeong, Wei D. Lu	Hybrid neural network using binary RRAM devices.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Shaloo Rakheja, N. Kani	Polymorphic spintronic logic gates for hardware security primitives - Device design and performance benchmarking.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Arne Heittmann, Tobias G. Noll	Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Elena Ioana Vatajelu, Lorena Anghel	Fully-connected single-layer STT-MTJ-based spiking neural network under process variability.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Liang Chang 0002, Zhaohao Wang, Youguang Zhang, Weisheng Zhao	Reconfigurable processing in memory architecture based on spin orbit torque.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Kelsey Scharnhorst, Walt Woods, Christof Teuscher, Adam Z. Stieg, James K. Gimzewski	Non-temporal logic performance of an atomic switch network.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit	A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf	CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Mohammad Mahmoud A. Taha, Christof Teuscher	Naive Bayesian inference of handwritten digits using a memristive associative memory.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Mingyu Li, Jiajun Shi, Sachin Bhat, Csaba Andras Moritz	Fine-grained 3D reconfigurable computing fabric with RRAM.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Zuodong Zhang, Lang Zeng, Tianqi Gao, Deming Zhang, Xiaowan Qin, Mingzhi Long, Youguang Zhang, Haiming Yu, Weisheng Zhao	Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana	Low cost multi-error correction for 3D polyhedral memories.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Xiaowan Qin, Lang Zeng, Tianqi Gao, Deming Zhang, Mingzhi Long, Youguang Zhang, Weisheng Zhao	Proposal for novel magnetic memory device with spin momentum locking materials.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi	A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	S. J. Dat Tran, Christof Teuscher	Memcapacitive reservoir computing.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Naveen Kumar Macha, Sandeep Geedipally, Mostafizur Rahman	Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Nishtha Sharma, Andrew Marshall, Jonathan Bird	Verilog - A compact model of a ME-MTJ based XNOR/NOR gate.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Karthik Yogendra, Minsuk Koo, Kaushik Roy 0001	Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Xuan Hu, Joseph S. Friedman	Transient model with interchangeability for dual-gate ambipolar CNTFET logic design.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal	Architecture, design and technology guidelines for crosspoint memories.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Guanda Wang, Yue Zhang 0010, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao	Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Dwaipayan Chakraborty, Sunny Raj, Sumit Kumar Jha 0001	A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge.	NANOARCH	2017	DBLP DOI BibTeX RDF