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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 14 keywords
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Results
Found 29 publication records. Showing 29 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
191 | François Pêcheux, Christophe Lallement, Alain Vachoux |
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 204-225, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
77 | Sri Chandra |
Driving Analog Mixed Signal Verification through Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 731, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
71 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov |
Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012, pp. 351-356, 2012, ACM, 978-1-4503-1244-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
56 | Ming-Ta Hsieh, Gerald E. Sobelman |
Modeling and verification of high-speed wired links with Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001 |
Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSC ![In: Proceedings of the 2007 Summer Computer Simulation Conference, SCSC 2007, San Diego, California, USA, July 16-19, 2007, pp. 551-558, 2007, Simulation Councils, Inc., 1-56555-316-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS |
35 | Francesco Tosoni 0002, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi |
A Framework for Modeling and Concurrently Simulating Mechanical and Electrical Faults in Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on Specification & Design Languages, FDL 2022, Linz, Austria, September 14-16, 2022, pp. 1-8, 2022, IEEE, 978-1-6654-7332-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
35 | Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi |
Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 39-44, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
35 | Nicola Dall'Ora, Enrico Fraccaroli, Sara Vinco, Franco Fummi |
Multi-Discipline Fault Modeling with Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPS ![In: 4th IEEE International Conference on Industrial Cyber-Physical Systems, ICPS 2021, Victoria, BC, Canada, May 10-12, 2021, pp. 237-243, 2021, IEEE, 978-1-7281-6207-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
35 | Nicola Dall'Ora, Sara Vinco, Franco Fummi |
Functionality and Fault Modeling of a DC Motor with Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDIN ![In: 18th IEEE International Conference on Industrial Informatics, INDIN 2020, Warwick, United Kingdom, July 20-23, 2020, pp. 35-40, 2020, IEEE, 978-1-7281-4964-6. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
35 | Bo Li 0056, Yonglei Zhao, Guoyong Shi |
A novel design of memristor-based bidirectional associative memory circuits using Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neurocomputing ![In: Neurocomputing 330, pp. 437-448, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
35 | Saraju P. Mohanty, Elias Kougianos |
iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1905.12812, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
35 | David Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez |
VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, pp. 19-22, 2018, IEEE, 978-1-5386-6365-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
35 | Vicente Yair Ponce-Hinestroza, Victor R. Gonzalez-Diaz |
System-Level Behavioral Model of a 12-Bit 1.5-Bit Per Stage Pipelined ADC Based on Verilog®=-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMACD ![In: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2018, Prague, Czech Republic, July 2-5, 2018, pp. 301-304, 2018, IEEE, 978-1-5386-5153-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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35 | Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi |
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12), pp. 2758-2763, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
35 | Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi |
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017, Austin, TX, USA, May 23-25, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-4502-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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35 | Poorna Marthi, Nazir Hossain, Huan Wang 0009, Jean-François Millithaler, Martin Margala, Ignacio Iñiguez-de-la-Torre, Javier Mateos, Tomás González |
Design and Analysis of High Performance Ballistic Nanodevice-Based Sequential Circuits Using Monte Carlo and Verilog AMS Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12), pp. 2236-2244, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
35 | Anders Jakobsson, Adriana Serban, Shaofang Gong |
Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3), pp. 680-688, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
35 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah |
Polynomial Metamodel integrated Verilog-AMS for memristor-based mixed-signal system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 916-919, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
35 | Mahmoud Fawzy Wagdy, Sandesh Maraliga Jayaram |
A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Tenth International Conference on Information Technology: New Generations, ITNG 2013, 15-17 April, 2013, Las Vegas, Nevada, USA, pp. 217-222, 2013, IEEE Computer Society, 978-0-7695-4967-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
35 | Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah |
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013, Washington, DC, USA, June 5-7, 2013, pp. 75-78, 2013, IEEE Computer Society, 978-1-4799-0494-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
35 | Beatriz Blanco-Filgueira, Paula López 0001, Juan Bautista Roldán |
A Verilog-AMS photodiode model including lateral effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 43(12), pp. 980-984, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
35 | Zhipeng Ye, Wenbin Chen, Michael Peter Kennedy |
Modeling and Simulation of Delta-Sigma Fractional-N PLL Frequency Synthesizer in Verilog-AMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10), pp. 2141-2147, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Peter Frey, Donald O'Riordan |
Verilog-AMS: Mixed-Signal Simulation and Cross Domain Connect Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMAS ![In: 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, BMAS 2000, Orlando, Florida, USA, 18-20 October 2000, pp. 103-108, 2000, IEEE Computer Society, 0-7695-0893-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Scott Little, Alper Sen 0001, Chris J. Myers |
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 109-115, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong |
Guess, solder, measure, repeat: how do I get my mixed-signal chip right? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 520-521, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification |
28 | Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu |
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA, pp. 70-75, 2008, IEEE Computer Society, 978-0-7695-3155-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Verilog-AMS, Static timing analysis, Look-up table |
21 | Nathaniel J. August |
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 423-428, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pre-silicon, validation, mixed-signal |
21 | Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu |
An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 286-290, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Monte Mar, Bert Sullam |
Modeling and verification of a programmable mixed-signal device using Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 902-905, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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