Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
47 | Erwin Halim, Nadira Altera, Placide Poba-Nzaou |
The Impact of Perceived Risks to Continuance Intention on Using NFC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT ![In: 29th International Conference on Telecommunications, ICT 2023, Toba, Indonesia, November 8-9, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-6110-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
47 | Altera |
User-configurable adapter interface chips for PS/2 micro channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 14(5), pp. 306-317, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
44 | Richard H. Stern |
West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 27(1), pp. 124-126, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
antitrust violation, Semiconductor Chip Protection Act, chip piracy, monopoly, Altera, Clear Logic, reverse engineering, ASICs, law, bitstream |
44 | Petr Pfeifer |
Multifunctional Programmable Single-Board CAN Monitoring Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 163-168, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Student Papers, FPL2000, programmable device, ALTERA, FLEX6000, EPF6016, SJA1000, PC/104, CAN |
38 | Jay Kraut |
Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 2013-2016, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | P. Moore, Máire McLoone, Sakir Sezer |
Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICT/SAPIR/ELETE ![In: Telecommunications 2005: Advanced Industrial Conference on Telecommunications / Service Assurance with Partial and Intermittent Resources Conference / E-Learning on Telecommunications Workshop (AICT / SAPIR / ELETE 2005), 17-22 July 2005, Lisbon, Portugal, pp. 296-299, 2005, IEEE Computer Society, 0-7695-2388-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard |
High Performance True Random Number Generator in Altera Stratix FPLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 555-564, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | François Charot, Eslam Yahya, Charles Wagner |
Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 282-291, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Omar A. Al Rayahi, Mohammed A. S. Khalid |
UWindsor Nios II: A soft-core processor for design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 451-457, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Arias Tanti Hapsari, Eniman Y. Syamsudin, Imron Pramana |
Design of vehicle position tracking system using short message services and its implementation on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 19-20, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Hong Wang 0007, Robert A. Walker 0001 |
Implementing a Scalable ASC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 267, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Ahmad Mouri Zadeh Khaki, Ebrahim Farshidi, Karim Ansari-Asl, Sawal Hamid Md. Ali, Masuri Othman |
Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 128117-128125, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Matej Bartík |
Reverse Engineering of Arrow USB Programmer2 JTAG Adapter for Intel/Altera FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 9th Mediterranean Conference on Embedded Computing, MECO 2020, Budva, Montenegro, June 8-11, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-6949-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
27 | Qasem Abu Al-Haija, Ibrahim Marouf, Mohammad M. Asad, Pankaj Mishra |
Pipelined Implementation of Millar-Rabin Primality Tester Using Altera FPGA Kit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSCC ![In: Security in Computing and Communications - 7th International Symposium, SSCC 2019, Trivandrum, India, December 18-21, 2019, Revised Selected Papers, pp. 237-246, 2019, Springer, 978-981-15-4824-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Mohammad M. Asad, Ibrahim Marouf, Qasem Abu Al-Haija, Abdullah AlShuaibi |
Performance Analysis of 128-bit Modular Inverse Based Extended Euclidean Using Altera FPGA Kit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUSPN/ICTH ![In: The 10th International Conference on Emerging Ubiquitous Systems and Pervasive Networks (EUSPN 2019) / The 9th International Conference on Current and Future Trends of Information and Communication Technologies in Healthcare (ICTH-2019) / Affiliated Workshops, Coimbra, Portugal, November 4-7, 2019., pp. 543-548, 2019, Elsevier. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Pan Li 0001, Rui Zhang, Jing Zhang, Jie Li, Guanxing Zhao, Hua Li |
Design of Radar Electromagnetic Environment Simulation System Based on Altera Stratix® III Series FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAI ![In: 5th International Conference on Systems and Informatics, ICSAI 2018, Nanjing, China, November 10-12, 2018, pp. 56-60, 2018, IEEE, 978-1-7281-0120-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Umut Ulutas, Mustafa Tosun, Vecdi Emre Levent, Duygu Büyükaydin, Toygar Akgün, H. Fatih Ugurdag |
FPGA Implementation of a Dense Optical Flow Algorithm Using Altera OpenCL SDK. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICT Innovations ![In: ICT Innovations 2017 - Data-Driven Innovation. 9th International Conference, ICT Innovations 2017, Skopje, Macedonia, September 18-23, 2017, Proceedings, pp. 89-101, 2017, Springer, 978-3-319-67596-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
27 | Harald Homulle, Edoardo Charbon |
Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field Programmable Technology, FPT 2017, Melbourne, Australia, December 11-13, 2017, pp. 25-31, 2017, IEEE, 978-1-5386-2656-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
27 | Qing Y. Tang, Mohammed A. S. Khalid |
Acceleration of k-Means Algorithm Using Altera SDK for OpenCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 10(1), pp. 6:1-6:19, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Ricardo Tapiador, Antonio Rios-Navarro, Alejandro Linares-Barranco, Minkyu Kim 0001, Deepak Kadetotad, Jae-sun Seo |
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1609.09296, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
27 | Ian Janik, Mohammed A. S. Khalid |
Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0916-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Derek Chiou |
Intel Acquires Altera: How Will the World of FPGAs be Affected? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016, pp. 148, 2016, ACM, 978-1-4503-3856-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Zhenzhong Xiao, Dirk Koch, Mikel Luján |
A partial reconfiguration controller for Altera Stratix V FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016, pp. 1-4, 2016, IEEE, 978-2-8399-1844-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner |
Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, Washington, DC, USA, May 1-3, 2016, pp. 21-24, 2016, IEEE Computer Society, 978-1-5090-2356-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Hiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato |
An acceleration of a random forest classification using Altera SDK for OpenCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, December 7-9, 2016, pp. 289-292, 2016, IEEE, 978-1-5090-5602-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Naraig Manjikian |
Retargeting and enhancing a compact multitasking kernel for the Altera Nios II processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: 2016 IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2016, Vancouver, BC, Canada, May 15-18, 2016, pp. 1-5, 2016, IEEE, 978-1-4673-8721-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Pawel Swierczynski, Amir Moradi 0001, David F. Oswald, Christof Paar |
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 7(4), pp. 34:1-34:23, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Ian Janik, Qing Y. Tang, Mohammed A. S. Khalid |
An overview of Altera SDK for OpenCL: A user perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: IEEE 28th Canadian Conference on Electrical and Computer Engineering, CCECE 2015, Halifax, NS, Canada, May 3-6, 2015, pp. 559-564, 2015, IEEE, 978-1-4799-5827-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
27 | Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner |
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014, pp. 326-329, 2014, IEEE, 978-1-4799-6245-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
27 | Linus Feiten, Andreas Spilla, Matthias Sauer 0002, Tobias Schubert 0001, Bernd Becker 0001 |
Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Secur. J. A Glob. Perspect. ![In: Inf. Secur. J. A Glob. Perspect. 22(5-6), pp. 265-273, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Athanasios Kalantzopoulos, Emmanouil Galetakis, Christos Katsenos, Evangelos Zigouris |
An Interactive Remote Laboratory on Basic Computer Architecture Using Altera DE2 Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Online Eng. ![In: Int. J. Online Eng. 9(5), pp. 9-16, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling |
Harnessing the power of FPGAs using altera's OpenCL compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013, pp. 5-6, 2013, ACM, 978-1-4503-1887-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Amir Moradi 0001, David F. Oswald, Christof Paar, Pawel Swierczynski |
Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013, pp. 91-100, 2013, ACM, 978-1-4503-1887-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif |
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2012, pp. 368, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
27 | Phani Balaji Swamy Tangellapalli, Syed Rafay Hasan |
Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 55th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2012, Boise, ID, USA, August 5-8, 2012, pp. 422-425, 2012, IEEE, 978-1-4673-2526-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
27 | Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj |
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings, pp. 491-506, 2011, Springer, 978-3-642-23950-2. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Christophe Alias, Alain Darte, Alexandru Plesco |
Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010, pp. 329-332, 2010, IEEE Computer Society, 978-1-4244-6967-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
27 | Bassam Shaer, Steven Silvester, Darrell Card |
LADAR System Development Using the Altera DE1 Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2010 International Conference on Embedded Systems & Applications, ESA 2010, July 12-15, 2010, Las Vegas Nevada, USA, pp. 98-104, 2010, CSREA Press, 1-60132-141-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
27 | Dan Mansur |
Newest additions to Altera's integrated transceiver portfolio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Chips Symposium ![In: 2009 IEEE Hot Chips 21 Symposium (HCS), Stanford, CA, USA, August 23-25, 2009, pp. 1-18, 2009, IEEE, 978-1-4673-8873-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Coral Gonzalez-Concejero, Victoria Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda |
An FFT/IFFT Design versus Altera and Xilinx Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 337-342, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Hamid R. Zarandi, Seyed Ghassem Miremadi |
Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 47(2-3), pp. 461-470, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu |
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing - IWDC 2004, 6th International Workshop, Kolkata, India, December 27-30, 2004, Proceedings, pp. 353-360, 2004, Springer, 3-540-24076-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Marcin Rogawski |
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR cs.CR/0312035, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
27 | Marcin Rogawski |
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2003, pp. 258, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
27 | Razak Mohammedali |
Altera FPGA Technology Provides Innovative Solutions for Evolving Market Needs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Engineering of Reconfigurable Systems and Algorithms ![In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 41-47, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
27 | Karl Rihaczek |
Audiatur et altera pars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Datenschutz und Datensicherheit ![In: Datenschutz und Datensicherheit 26(8), 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
27 | Alex Panato, Marcelo Barcelos, Ricardo Reis 0001 |
An IP of an Advanced Encryption Standard for Altera" Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2002, Porto Alegre, Brazil, September 9-14, 2002, pp. 197-202, 2002, IEEE Computer Society, 0-7695-1807-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
27 | James O. Hamblen, Gregory E. Ruhl |
Using the Altera UP-1 Board for Prototyping and VGA Video Display Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 16-17, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Andrzej Hlawiczka, Jacek Binda |
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 120-122, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | André Klindworth |
A Tool-Set for Simulating Altera-PLDs Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 306-308, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
22 | Scott Cromar, Jaeho Lee, Deming Chen |
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 838-843, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch power, FPGA, high-level synthesis, power reduction |
22 | Michael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck |
Fpga-based data acquisition system for a positron emission tomography (PET) scanner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 264, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, positron emission tomography |
22 | Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong |
Place-and-Route Impact on the Security of DPL Designs in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings, pp. 26-32, 2008, IEEE Computer Society, 978-1-4244-2401-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Kevin Oo Tinmaung, David Howland, Russell Tessier |
Power-aware FPGA logic synthesis using binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 148-155, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, binary decision diagram, dynamic power |
22 | Stevan M. Bererber, Chih-Hong Wang, Kevin K. Wei |
Design of a CDMA System in FPGA Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 3061-3065, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan |
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 340-348, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar |
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 848-853, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier |
An adaptive Reed-Solomon errors-and-erasures decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 150-158, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, power reduction, Reed-Solomon |
22 | Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown |
A Multithreaded Soft Processor for SoPC Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 131-142, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown |
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 3-8, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Martin Simka, Milos Drutarovský, Viktor Fischer, J. Fayolle |
Model of a true random number generator aimed at cryptographic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
Design of a radix-2m hybrid array multiplier using carry save adder format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 172-177, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hybrid multiplier, low power, carry save adder |
22 | H. G. Epassa, François R. Boyer, Yvon Savaria |
Implementation of a cycle by cycle variable speed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3335-3338, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Paul Metzgen |
A high performance 32-bit ALU for programmable logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 61-70, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ALU, Apex 20KE, Nios, FPGA, programmable logic, soft processors |
22 | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
Performance-driven mapping for CPLD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10), pp. 1424-1431, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson |
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 237, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland |
Implementing Asynchronous Circuits on LUT Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 36-46, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana |
A Sum of Absolute Differences Implementation in FPGA Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 28th EUROMICRO Conference 2002, 4-6 September 2002, Dortmund, Germany, pp. 183-188, 2002, IEEE Computer Society, 0-7695-1787-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Charles Eric LaForest, J. Gregory Steffan |
Efficient multi-ported memories for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 41-50, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, parallel, memory, multi-port |
11 | Behzad Mahdavikhah, Ramin Mafi, Shahin Sirouspour, Nicola Nicolici |
Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 189-198, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
conjugate gradient (CG), finite-element modeling (FEM), field-programmable gate array (FPGA) |
11 | Flavius Opritoiu, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu |
A high-speed AES architecture implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 95-96, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cryptochip, optimization, fpga, hardware, aes |
11 | Shiuh-Jer Huang, Shian-Shin Wu |
Vision-Based Robotic Motion Control for Non-autonomous Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 54(5), pp. 733-754, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Self-organizing fuzzy control, FPGA chip, Visual servo, Robotic system |
11 | Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung |
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 10:1-10:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Testing, configuration, delay measurement |
11 | G. Seetharaman, B. Venkataramani |
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 11:1-11:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, SOC, CORDIC, wave-pipelining, DAA |
11 | Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane |
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 19(2), pp. 237-249, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Michael Dyer, Saeid Nooshabadi, David S. Taubman |
Design and Analysis of System on a Chip Encoder for JPEG2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 19(2), pp. 215-225, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Miad Faezipour, Mehrdad Nourani, Rina Panigrahy |
A hardware platform for efficient worm outbreak detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 49:1-49:29, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
shared counters, worm outbreak, hashing, false positive, Network Intrusion Detection System, false negative, polymorphic worm |
11 | Sanad Bushnaq, Toru Nakura, Makoto Ikeda, Kunihiro Asada |
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 206-209, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Xin Xiao, Erdal Oruklu, Jafar Saniie |
Fast memory addressing scheme for radix-4 FFT implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 437-440, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Mohammed A. S. Abdallah, Omar S. Elkeelany, Ali T. Alouani |
Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 281, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
adc, sd card, fpga, real-time, multiplexing, data acquisition, fft |
11 | Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau |
Measuring and modeling variabilityusing low-cost FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 286, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
variability |
11 | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
Towards automated ECOs in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 3-12, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
pst, optimization, fpga, boolean satisfiability, resynthesis |
11 | Taehoon Kim, Sungwoo Tak |
A real-time hardware-software codesign technique of network protocols to provide QoS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 67-70, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
QoS communications architecture, real-time scheduling, network protocols, hardware-software codesign |
11 | Robson Dornelles, Felipe Sampaio, Daniel Palomino 0001, Luciano Volcan Agostini |
Transforms and quantization design targeting the H.264/AVC intra prediction constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
IQ modules, Q, T, IT, video coding, high performance, H.264/AVC, VLSI design, low latency, intra-prediction |
11 | Valerij Matrose, Carsten Gremzow |
Improved placement for hierarchical FPGAs exploiting local interconnect resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, placement |
11 | Jie Zhou 0007, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang |
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 110-122, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller |
Design and Implementation of a Radix-4 Complex Division Unit with Prescaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA, pp. 83-90, 2009, IEEE Computer Society, 978-0-7695-3732-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani |
VLSI architectures of perceptual based video watermarking for real-time copyright protection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 527-534, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Te Su, Chun-Yang Hu, Tzuu-Hseng S. Li |
FPGA-Based Vocabulary Recognition Module for Humanoid Robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FIRA ![In: Advances in Robotics, FIRA RoboWorld Congress 2009, Incheon, Korea, August 16-20, 2009. Proceedings, pp. 151-160, 2009, Springer, 978-3-642-03982-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA-based, humanoid robot |
11 | J. Manikandan, B. Venkataramani, V. Avanthi |
FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 347-352, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Kimmo U. Järvinen, Jorma Skyttä |
On Parallelization of High-Speed Processors for Elliptic Curve Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1162-1175, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Joshua Noseworthy, Miriam Leeser |
Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 1083-1090, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung |
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(10), pp. 1268-1280, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle |
Radio frequency identification prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 29:1-29:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
low-power, RFID, prototyping, Design automation |
11 | Eero Aho, Jarno Vanne, Timo D. Hämäläinen |
Configurable Data Memory for Multimedia Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 50(2), pp. 231-249, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
stride access, configurable, parallel memory, skewing scheme, SIMD processing |
11 | Jason Yu, Guy G. Lemieux, Christopher Eagleston |
Vector processing as a soft-core CPU accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 222-232, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism |
11 | Jeremy Buboltz, Taskin Koçak |
Front End Device for Content Networking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1456-1461, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1256-1261, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Carlo Brandolese, William Fornaciari |
Measurement, Analysis and Modeling of RTOS System Calls Timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 618-625, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Weijun Zhang, Yujie Dun, Weixiang Shi, Baogang Miao, Bingo Zhang |
High Productivity Computing System Based on FPGA and Its Application on Plasma Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 10th IEEE International Conference on High Performance Computing and Communications, HPCC 2008, 25-27 Sept. 2008, Dalian, China, pp. 756-761, 2008, IEEE Computer Society, 978-0-7695-3352-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|