Search results for "Buses"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Susumu Matsumae, Nobuki Tokura	Simulating a Mesh with Separable Buses by a Mesh with Partitioned Buses.	ISPAN	1999	DBLP DOI BibTeX RDF	two-dimensional mesh-connected computer, mesh with separable buses, mesh with partitioned buses, broadcasting, propagation delay, simulation algorithm
89	Susumu Matsumae	Optimal Simulation of Meshes with Dynamically Separable Buses by Meshes with Statically Partitioned Buses.	ISPAN	2004	DBLP DOI BibTeX RDF
89	Susumu Matsumae	Simulation of Meshes with Separable Buses by Meshes with Multiple Partitioned Buses.	IPDPS	2003	DBLP DOI BibTeX RDF
84	Jeffrey A. Floyd, Matt Perry	Real-time on-board bus testing.	VTS	1995	DBLP DOI BibTeX RDF	on-board bus testing, wide buses, computer buses, board layout, full-fault testing, multiple speeds, pseudo-random pattern generation, characteristic equations, IEEE JTAG protocol, real-time systems, protocols, logic testing, automatic testing, system buses, operating environments, multiple seed, clock speeds
82	Kazuo Iwama, Eiji Miyano	Oblivious Routing Algorithms on the Mesh of Buses.	IPPS	1997	DBLP DOI BibTeX RDF
66	Mounir Hamdi, J. Tong, C. W. Kin	Fast sorting algorithms on reconfigurable array of processors with optical buses.	ICPADS	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, optical buses, parallel algorithms, parallel architectures, sorting, reconfigurable architectures, optical interconnections, system buses, sorting algorithms, reconfigurable array, reconfigurable arrays, parallel sorting algorithm
66	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	An energy-efficient temporal encoding circuit technique for on-chip high performance buses.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	on-chip buses, energy-efficient, encoding, repeaters
66	Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001	Semigroup and Prefix Computations on Improved Generalized Mesh-Connected Computers with Multiple Buses.	IPDPS	2000	DBLP DOI BibTeX RDF	mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, bus, mesh-connected computer
65	Nihar R. Mahapatra, Jiangjiang Liu 0002, Krishnan Sundaresan	Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.	ICCD	2003	DBLP DOI BibTeX RDF
58	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
57	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
57	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
57	Jihong Ren, Mark R. Greenstreet	Synthesizing optimal filters for crosstalk-cancellation for high-speed buses.	DAC	2003	DBLP DOI BibTeX RDF	equalizing filters, optimal synthesis, crosstalk, buses
57	Biing-Feng Wang, Stephan Olariu	On the Power of the Mesh with Hybrid Buses.	ISPAN	1997	DBLP DOI BibTeX RDF	Mesh with Hybrid Buses, Mesh with Multiple Broadcasting, simulation, parallel algorithms, PRAM, reconfigurable mesh
57	Zicheng Guo, Rami G. Melhem	Embedding Binary X-Trees and Pyramids in Processor Arrays with Spanning Buses.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	binaryX-trees, spanning buses, 2-D arrayarchitectures, routing step, parallel architectures, multiprocessor interconnection networks, embedding, network routing, binary trees, processor arrays, pyramids, network embeddings
57	Mauricio J. Serrano, Behrooz Parhami	Optimal Architectures and Algorithms for Mesh-Connected Parallel Computers with Separable Row/Column Buses.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	mesh-connected, separable row and column buses, parallel algorithms, computational complexity, parallel computers, parallel architectures, time complexity, processing elements, data routing, two-dimensional mesh, prefix computation, semigroup computation
50	Jong Hyuk Choi, Bong Wan Kim, Kyu Ho Park, Kwang-Il Park	A Bandwidth-Efficient Implementation of Mesh with Multiple Broadcasting.	ICPP	1999	DBLP DOI BibTeX RDF	Mesh with Buses, Parallel Computing, Multicast, Interconnection Network, Broadcast, Collective Communication
50	Jongmin Lee, Eujoon Byun, Hanmook Park, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh	CPS-SIM: configurable and accurate clock precision solid state drive simulator.	SAC	2009	DBLP DOI BibTeX RDF	SSD (solid state drive), clock precision SSD simulator, configurability, NAND flash memory, FTL (flash translation layer)
50	Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong	OPC-Friendly Bus Driven Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
50	Marcello Coppola	Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network.	IOLTS	2006	DBLP DOI BibTeX RDF
50	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	Propagation Delay Minimization on RLC-Based Bus with Repeater Insertion.	APCCAS	2006	DBLP DOI BibTeX RDF
50	Sotirios G. Ziavras	Performance Analysis for an Important Class of Parallel-Processing Networks.	ISPAN	1996	DBLP DOI BibTeX RDF	complexity of algorithms, parallel algorithms, broadcasting, cost analysis, mesh architecture
50	Cauligi S. Raghavendra	HMESH: A VLSI Architecture for Parallel Processing.	CONPAR	1986	DBLP DOI BibTeX RDF
50	Sanguthevar Rajasekaran	Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	mesh with reconfigurable buses, mesh with fixed buses, k?k routing, k?k sorting, parallel computing, randomized algorithms, sorting, mesh, packet routing, Reconfigurable networks
50	Kuo-Liang Chung, Yu-Chih Lin	A Parametric Algorithm for Semigroup Computation on Mesh with Buses.	Computing	1996	DBLP DOI BibTeX RDF	mesh-connected computers with segmented buses, reconfigurable buses, parametric parallel algorithm, broadcasting, Semigroup computation
49	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
49	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters In bidirectional buses.	DAC	2003	DBLP DOI BibTeX RDF	delay, interconnect, noise, repeaters, buses
49	Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
49	Yi Pan 0001, Si-Qing Zheng, Keqin Li 0001, Hong Shen 0001	An Improved Generalization of Mesh-Connected Computers with Multiple Buses.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	mesh-connected computer with multiple buses, parallel algorithm, parallel computing, parallel architecture, processor array, Bus, mesh-connected computer
49	Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang	The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems
49	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
49	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
49	Krishnan Sundaresan, Nihar R. Mahapatra	An Accurate Energy and Thermal Model for Global Signal Buses.	VLSI Design	2005	DBLP DOI BibTeX RDF
49	Claudia Kretzschmar, André K. Nieuwland, Dietmar Müller 0001	Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work.	DATE	2004	DBLP DOI BibTeX RDF
49	Himanshu Kaul, Dennis Sylvester, Mark A. Anders 0001, Ram Krishnamurthy 0001	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses.	ISLPED	2004	DBLP DOI BibTeX RDF
49	Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne H. Wolf	A dictionary-based en/decoding scheme for low-power data buses.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
49	Amos Beimel, Shlomi Dolev	Buses for Anonymous Message Delivery.	J. Cryptol.	2003	DBLP DOI BibTeX RDF	Privacy, Traffic analysis, Anonymous communication
49	William Fornaciari, M. Polentarutti, Donatella Sciuto, Cristina Silvano	Power optimization of system-level address buses based on software profiling.	CODES	2000	DBLP DOI BibTeX RDF
49	Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen	ESD buses for whole-chip ESD protection.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
49	Sanguthevar Rajasekaran	Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing, Sorting, and Selection.	ESA	1993	DBLP DOI BibTeX RDF
42	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt, Min Xu	A comprehensive estimation technique for high-level synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	HLS benchmarks, RT level components, RTL datapaths, estimation technique, delays, high level synthesis, high-level synthesis, timing, design space exploration, granularity, hardware description languages, data flow graphs, registers, system buses, timing model, buses, behavioral description, layout area
42	Mircea R. Stan, Wayne P. Burleson	Coding a terminated bus for low power.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	pull-up terminators, bus liner, limited-weight codes, parallel terminated buses, Rambus, perfect k/2-limited weight code, nonperfect 3-limited weight code, error correction codes, encoding, decoding, power dissipation, random-access storage, system buses
41	Anu G. Bourgeois, Jerry L. Trahan	Relating Two-Dimensional Reconfigurable Meshes with Optically Pipelined Buses.	IPDPS	2000	DBLP DOI BibTeX RDF	Reconfigurable models, optical buses, complexity, model simulations
41	Sandy Pavel, Selim G. Akl	Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses.	IPPS	1996	DBLP DOI BibTeX RDF	arrays with reconfigurable optical buses, Hough transform
41	Mounir Hamdi, Yi Pan 0001	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
41	Jop F. Sibeyn, Michael Kaufmann 0001, Rajeev Raman	Randomized Routing on Meshes with Buses.	ESA	1993	DBLP DOI BibTeX RDF	algorithms, parallel computation, lower bounds, meshes, randomization, coloring, packet routing, buses
40	Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie 0001	Delay and Energy Efficient Data Transmission for On-Chip Buses.	ISVLSI	2006	DBLP DOI BibTeX RDF
40	Krishnan Sundaresan, Nihar R. Mahapatra	Value-based bit ordering for energy optimization of on-chip global signal buses.	DATE	2006	DBLP DOI BibTeX RDF
40	Boon-Chong Seet, Chiew Tong Lau, Wen-Jing Hsu, Bu-Sung Lee	A Mobile System of Super-Peers Using City Buses.	PerCom Workshops	2005	DBLP DOI BibTeX RDF
40	Liang Zhang 0038, John M. Wilson 0002, Rizwan Bashirullah, Lei Luo 0006, Jian Xu, Paul D. Franzon	Driver pre-emphasis techniques for on-chip global buses.	ISLPED	2005	DBLP DOI BibTeX RDF	current sensing, peak current, pre-emphasis, low-power, crosstalk, differential, on-chip bus
40	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	A tunable bus encoder for off-chip data buses.	ISLPED	2005	DBLP DOI BibTeX RDF	TUBE, data bus, data bus encoding, tunable bus encoder
40	Yi Zhao, Sujit Dey, Li Chen	Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
40	Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson	An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.	PATMOS	2004	DBLP DOI BibTeX RDF
40	Jiangjiang Liu 0002, Nihar R. Mahapatra, Krishnan Sundaresan	Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.	ISVLSI	2003	DBLP DOI BibTeX RDF
40	Dinesh C. Suresh, Jun Yang 0002, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar	FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.	HiPC	2003	DBLP DOI BibTeX RDF
40	Susumu Matsumae	An Efficient Scaling-Simulation Algorithm of Reconfigurable Meshes by Meshes with Partitioned Buses.	IPDPS	2003	DBLP DOI BibTeX RDF
40	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding
40	Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy	System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.	ISSS	2002	DBLP DOI BibTeX RDF	voltage/frequency scaling, embedded systems, design space, power-performance trade-offs
40	Yi Zhao, Li Chen, Sujit Dey	On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.	ITC	2002	DBLP DOI BibTeX RDF
40	Wei-Cheng Lai, Jing-Reng Huang, Kwang-Ting (Tim) Cheng	Embedded-Software-Based Approach to Testing Crosstalk-Induced Faults at On-Chip Buses.	VTS	2001	DBLP DOI BibTeX RDF
40	Kazuo Iwama, Eiji Miyano, Satoshi Tajima, Hisao Tamaki	Efficient Randomized Routing Algorithms on the Two-Dimensional Mesh of Buses.	COCOON	1998	DBLP DOI BibTeX RDF
40	Ville Leppänen	Embedding and Emulation Results for Static Multichannel Mesh of Optical Buses.	Euro-Par	1997	DBLP DOI BibTeX RDF
40	Kuo-Liang Chung	Prefix Computations on a Generalized Mesh-Connected Computer with Multiple Buses.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
40	Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj	Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
40	Kazuo Iwama, Eiji Miyano	Routing Problems on the Mesh of Buses.	ISAAC	1992	DBLP DOI BibTeX RDF
34	Andrew Tjang, Michael Pagliorola, Hiral Patel, Xiaoyan Li, Richard P. Martin	Active Tapes: Bus-Based Sensor Networks.	LCN	2004	DBLP DOI BibTeX RDF	Power buses, Data buses, Sensor networks
34	Russ Miller, Quentin F. Stout	Simulating Essential Pyramids.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	essential pyramids, pyramid algorithms, mesh with row and column buses, mesh with reconfigurable buses, pyramid computer, simulation, image processing, parallel processing, virtual machines, hypercube, mesh, computerised picture processing, optimal algorithms, PRAM, mesh-of-trees
34	Masaru Takesue	Psi-Cubes: Recursive Bused Fat-Hypercubes for Multilevel Snoopy Caches.	ISPAN	1999	DBLP DOI BibTeX RDF	Bused networks, recursive networks, trees of buses, multilevel caches, coherence directories, clustering, Hamming codes
33	Tilen Ma, Evangeline F. Y. Young	TCG-based multi-bend bus driven floorplanning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
33	Xiaolan Zhang 0003, Jim Kurose, Brian Neil Levine, Donald F. Towsley, Honggang Zhang 0003	Study of a bus-based disruption-tolerant network: mobility modeling and impact on routing.	MobiCom	2007	DBLP DOI BibTeX RDF	mobility trace modeling, DTN, epidemic routing
33	Edwin Naroska, Shanq-Jang Ruan, Uwe Schwiegelshohn	Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
33	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
33	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn	Simultaneous Wire Permutation, Inversion, and Spacing with Genetic Algorithm for Energy-Efficient Bus Design.	IPDPS	2005	DBLP DOI BibTeX RDF
33	Mahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt	Adaptive low-power address encoding techniques using self-organizing lists.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
33	Makoto Sugihara, Hiroto Yasuura	Optimization of Test Accesses with a Combined BIST and External Test Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	external test, CBET, test access, external pins, BIST, test scheduling, test time, test bus
33	Chittaranjan A. Mandal, R. M. Zimmer	A Genetic Algorithm for the Synthesis of Structured Data Paths.	VLSI Design	2000	DBLP DOI BibTeX RDF	Data Path Synthesis (DPS), Scheduling, High-Level Synthesis (HLS), Allocation
33	Friedhelm Meyer auf der Heide, Harald Räcke, Matthias Westermann	Data management in hierarchical bus networks.	SPAA	2000	DBLP DOI BibTeX RDF
33	Aurobindo Dasgupta, Ramesh Karri	High-reliability, low-energy microarchitecture synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
33	Scott T. Leutenegger, Mary K. Vernon	A Mean-Value Performance Analysis of a New Multiprocessor Architecture.	SIGMETRICS	1988	DBLP DOI BibTeX RDF
33	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
33	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
33	Michel Dubois 0001	Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	shared interleaved memory, cache-based multiprocessors, general-purpose computing, dynamic instruction mix statistics, performance evaluation, performance, throughput, multiprocessing systems, buffer storage, multitasking, private cache, multiple buses
32	Antoine Courtay, Johann Laurent, Olivier Sentieys, Nathalie Julien	Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses.	PATMOS	2008	DBLP DOI BibTeX RDF
32	Tomoya Kitani, Takashi Shinkawa, Naoki Shibata, Keiichi Yasumoto, Minoru Ito, Teruo Higashino	Efficient VANET-Based Traffic Information Sharing using Buses on Regular Routes.	VTC Spring	2008	DBLP DOI BibTeX RDF
32	Michel Sede, Xu Li 0009, Da Li, Min-You Wu, Minglu Li 0001, Wei Shu	Routing in Large-Scale Buses Ad Hoc Networks.	WCNC	2008	DBLP DOI BibTeX RDF
32	Dirk Koch, Christian Haubelt, Jürgen Teich	Efficient Reconfigurable On-Chip Buses for FPGAs.	FCCM	2008	DBLP DOI BibTeX RDF
32	Karthik Duraisami, Enrico Macii, Massimo Poncino	Energy efficiency bounds of pulse-encoded buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	power reduction., pulse wave transmission, high-speed interconnect, transition activity
32	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
32	David C. Keezer, Dany Minier, Patrice Ducharme	Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	control structure reliability, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection, fault tolerance, testing
32	Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor	Physical design implementation of segmented buses to reduce communication energy.	ASP-DAC	2006	DBLP DOI BibTeX RDF
32	Yeow Meng Chee, Charles J. Colbourn, Alan C. H. Ling	Optimal memoryless encoding for low power off-chip data buses.	ICCAD	2006	DBLP DOI BibTeX RDF
32	Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri	Memory-based crosstalk canceling CODECs for on-chip buses.	ISCAS	2006	DBLP DOI BibTeX RDF
32	Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra	Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	address bus, low power, encoding, energy dissipation
32	Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen	Language-Based High Level Transaction Extraction on On-chip Buses.	ISQED	2006	DBLP DOI BibTeX RDF
32	Qingli Zhang, Jinxiang Wang 0001, Yizheng Ye	Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses.	APCCAS	2006	DBLP DOI BibTeX RDF
32	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters in bidirectional buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
32	Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura	A variation-aware low-power coding methodology for tightly coupled buses.	ASP-DAC	2005	DBLP DOI BibTeX RDF
32	Teck Meng Lim, Boon-Chong Seet, Bu-Sung Lee, Chai Kiat Yeo, Andreas Kassler	Pervasive Communication for Commuters in Public Buses.	PerCom Workshops	2005	DBLP DOI BibTeX RDF
32	Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang 0002	VALVE: Variable Length Value Encoder for Off-Chip Data Buses..	ICCD	2005	DBLP DOI BibTeX RDF
32	Maged Ghoneima, Yehea I. Ismail	Accurate decoupling of capacitively coupled buses.	ISCAS (4)	2005	DBLP DOI BibTeX RDF