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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 44 occurrences of 32 keywords
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Results
Found 181 publication records. Showing 181 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
108 | Yoonjin Kim, Rabi N. Mahapatra |
Hierarchical reconfigurable computing arrays for efficient CGRA-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 826-831, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), computing hierarchy, embedded systems |
97 | Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis |
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 48(2), pp. 115-151, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques |
97 | Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek |
SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 776-782, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
78 | Yoonjin Kim, Rabi N. Mahapatra |
A New Array Fabric for Coarse-Grained Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 584-591, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
78 | Song Li-Guo, Jiang Yu-Xian |
A Route System Based on Ant Colony for Coarse-Grain Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (2) ![In: Advances in Natural Computation, Second International Conference, ICNC 2006, Xi'an, China, September 24-28, 2006. Proceedings, Part II, pp. 215-221, 2006, Springer, 3-540-45907-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Yongjun Park 0001, Hyunchul Park 0001, Scott A. Mahlke |
CGRA express: accelerating execution using dynamic operation fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 271-280, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
latency-constrained, subgraph accelerator, modulo scheduling, coarse-grained reconfigurable architecture |
58 | Yoonjin Kim, Rabi N. Mahapatra |
Dynamic context management for low power coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 33-38, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
context word, embedded systems, system-on-chip (soc), digital signal processing, coarse-grained reconfigurable architecture, configuration cache |
58 | Yan Guo, Sanyou Zeng, Lishan Kang, Gang Liu, Nannan Hu, Kuo Zhao |
A Route System Based on Genetic Algorithm for Coarse-Grain Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISICA ![In: Advances in Computation and Intelligence, 4th International Symposium, ISICA 2009, Huangshi, China, Ocotober 23-25, 2009, Proceedings, pp. 11-17, 2009, Springer, 978-3-642-04842-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
resources-constrained multi-pair shortest path problem in directed graphs, Multi-pair path encoding, Genetic algorithm, Coarse-grain reconfigurable architecture |
58 | Yoonjin Kim, Rabi N. Mahapatra |
Dynamically compressible context architecture for low power coarse-grained reconfigurable array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 395-400, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
58 | Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001 |
QUKU: A Two-Level Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 109-116, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Sunil Shukla, Neil W. Bergmann, Jürgen Becker 0001 |
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 93-98, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula |
Enabling Multithreading on CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: International Conference on Parallel Processing, ICPP 2011, Taipei, Taiwan, September 13-16, 2011, pp. 255-264, 2011, IEEE Computer Society, 978-1-4577-1336-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique |
43 | Rong Zhu, Bo Wang, Dajiang Liu |
RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pp. 262-267, 2022, IEEE, 978-3-9819263-6-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
43 | Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang 0003, Tianyi Yu |
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 156-162, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
43 | S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson |
CGRA-ME: A unified framework for CGRA modelling and exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 28th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2017, Seattle, WA, USA, July 10-12, 2017, pp. 184-189, 2017, IEEE Computer Society, 978-1-5090-4825-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
39 | Taewook Oh, Bernhard Egger 0002, Hyunchul Park 0001, Scott A. Mahlke |
Recurrence cycle aware modulo scheduling for coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 21-30, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
software pipelining, placement and routing, coarse-grained reconfigurable architectures |
39 | Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1334-1339, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Yoonjin Kim, Rabi N. Mahapatra |
Reusable context pipelining for low power coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Thomas Lenart, Henrik Svensson, Viktor Öwall |
Modeling and exploration of a reconfigurable architecture for digital holographic imaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 248-251, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Hyunchul Park 0001, Kevin Fan, Manjunath Kudlur, Scott A. Mahlke |
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 136-146, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
graph embedding, modulo scheduling, coarse-grained reconfigurable architecture |
28 | Leipo Yan, Thambipillai Srikanthan, Niu Gang |
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'06), Ottawa, Ontario, Canada, June 14-16, 2006, pp. 182-188, 2006, ACM, 1-59593-362-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CGRA, VLIW, hardware/software partitioning, delay estimation, area estimation |
28 | Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek |
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 310-315, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping |
21 | Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang |
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(3), pp. 505-518, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Dan Wu, Peng Chen 0027, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra |
Flip: Data-centric Edge CGRA Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 29(1), pp. 22:1-22:25, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Dajiang Liu, Yuxin Xia, Jiaxing Shang, Jiang Zhong, Peng Ouyang, Shouyi Yin |
E2EMap: End-to-End Reinforcement Learning for CGRA Compilation via Reverse Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High-Performance Computer Architecture, HPCA 2024, Edinburgh, United Kingdom, March 2-6, 2024, pp. 46-60, 2024, IEEE, 979-8-3503-9313-2. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Chen Yin, Naifeng Jing, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao |
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3), pp. 874-886, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin |
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8), pp. 2552-2565, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Satyajit Das, Kevin J. M. Martin, Thomas Peyret, Philippe Coussy |
An Efficient and Flexible Stochastic CGRA Mapping Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 22(1), pp. 8:1-8:24, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Reza Kazerooni-Zand, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 28(4), pp. 66:1-66:25, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Haojia Hui, Jiangyuan Gu, Xunbo Hu, Yang Hu 0001, Leibo Liu, Shaojun Wei, Shouyi Yin |
WindMill: A Parameterized and Pluggable CGRA Implemented by DIAG Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.01273, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dan Wu, Peng Chen 0027, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra |
Flip: Data-Centric Edge CGRA Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2309.10623, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Hans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi |
Generating CGRA Processing Element Hardware with CGRAgen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 26th Euromicro Conference on Digital System Design, DSD 2023, Golem, Albania, September 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-4419-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima |
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MCSoC ![In: 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023, pp. 419-425, 2023, IEEE, 979-8-3503-9361-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson |
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023, pp. 305-310, 2023, IEEE, 979-8-3503-4151-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Rui Rodrigues de Mello Junior, Gabriel Antoine Louis Paillard, Leandro Santiago de Araújo, Pedro C. Diniz, Felipe M. G. França |
GSink - A Runtime for Gamma Programs and its CGRA Mapping Proposal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023, pp. 444-451, 2023, IEEE, 979-8-3503-1199-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano |
Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023, pp. 452-459, 2023, IEEE, 979-8-3503-1199-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Omar Ragheb, Rami Beidas, Jason Helge Anderson |
Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS 2023 - Workshops, St. Petersburg, FL, USA, May 15-19, 2023, pp. 468-475, 2023, IEEE, 979-8-3503-1199-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yuan Dai, Yunhui Qiu, Qilong Zhu, Jingyuan Li, Wenbo Yin, Lingli Wang |
UPTRA: An Ultra-Parameterized Temporal CGRA Modeling and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023, pp. 208, 2023, IEEE, 979-8-3503-1205-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima |
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
candar ![In: Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28 - Dec. 1, 2023, pp. 189-195, 2023, IEEE, 979-8-3503-0670-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Cheng Tan 0002, Deepak Patil, Antonino Tumeo, Gabriel Weisz, Steven K. Reinhardt, Jeff Zhang 0001 |
VecPAC: A Vectorizable and Precision-Aware CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, pp. 1-9, 2023, IEEE, 979-8-3503-2225-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh |
FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, pp. 1-9, 2023, IEEE, 979-8-3503-2225-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tomoya Akabe, Ryotaro Funai, Yasuhiko Nakashima |
Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Felix Böseler, Jörg Walter 0001 |
A Flexible Graph Language for a Model-Based Semi-Automatic CGRA Compilation Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on Specification & Design Languages, FDL 2023, Turin, Italy, September 13-15, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-0737-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jiangnan Li, Chang Cai, Yaya Zhao, Yazhou Yan, Wenbo Yin, Lingli Wang |
GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFPT ![In: International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023, pp. 26-34, 2023, IEEE, 979-8-3503-5911-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Qilong Zhu, Yuhang Cao, Yunhui Qiu, Xuchen Gao, Wenbo Yin, Lingli Wang |
A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFPT ![In: International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023, pp. 298-299, 2023, IEEE, 979-8-3503-5911-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Tobias Kaiser, Friedel Gerfers |
A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-3201-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Jingyuan Li, Yunhui Qiu, Guowei Zhu, Qilong Zhu, Wenbo Yin, Lingli Wang |
THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, pp. 1-5, 2023, IEEE, 978-1-6654-5109-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Mingyang Chen, Yunhui Qiu, Kaixiang Zhu, Lingli Wang |
An Automatic Optimization Method of Combinational Logic Loops in CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-1298-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Dajiang Liu, Di Mou, Rong Zhu, Yan Zhuang, Jiaxing Shang, Jiang Zhong, Shouyi Yin |
DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yixuan Luo, Cheng Tan 0002, Nicolas Bohm Agostini, Ang Li 0006, Antonino Tumeo, Nirav Dave, Tong Geng |
ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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21 | Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu 0001, Leibo Liu, Shaojun Wei, Shouyi Yin |
RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Liao Huang, Dajiang Liu |
Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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21 | Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele |
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10), pp. 3290-3303, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Baofen Yuan, Jianfeng Zhu 0001, Xingchen Man, Zijiao Ma, Shouyi Yin, Shaojun Wei, Leibo Liu |
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9), pp. 2929-2942, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Zhaoying Li, Dhananjaya Wijerathne, Xianzhang Chen, Anuj Pathania, Tulika Mitra |
ChordMap: Automated Mapping of Streaming Applications Onto CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(2), pp. 306-319, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Luca Zulberti, Matteo Monopoli, Pietro Nannipieri, Luca Fanucci |
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 17th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2022, Villasimius, SU, Italy, June 12-15, 2022, pp. 373-376, 2022, IEEE, 978-1-6654-6700-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Tobias Kaiser, Friedel Gerfers |
Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings, pp. 33-47, 2022, Springer, 978-3-031-21866-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Rami Beidas, Jason Helge Anderson |
CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 616-622, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Kevin J. M. Martin |
Twenty Years of Automated Methods for Mapping Applications on CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS Workshops 2022, Lyon, France, May 30 - June 3, 2022, pp. 679-686, 2022, IEEE, 978-1-6654-9747-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Ilan Tayari |
CGRA4HPC 2022 Invited Speaker: Practical, scalable, and easy-to-use CGRA for HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS Workshops 2022, Lyon, France, May 30 - June 3, 2022, pp. 630, 2022, IEEE, 978-1-6654-9747-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Takuya Kojima, Boma A. Adhi, Carlos Cortes, Yiyu Tan, Kentaro Sano |
An Architecture- Independent CGRA Compiler enabling OpenMP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: IEEE International Parallel and Distributed Processing Symposium, IPDPS Workshops 2022, Lyon, France, May 30 - June 3, 2022, pp. 631-638, 2022, IEEE, 978-1-6654-9747-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Yan Zhuang, Zhihao Zhang, Dajiang Liu |
Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, pp. 61:1-61:9, 2022, ACM, 978-1-4503-9217-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano |
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-5336-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano |
Body Bias Control on a CGRA based on Convex Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2022, Tokyo, Japan, April 20-22, 2022, pp. 1-3, 2022, IEEE, 978-1-6654-1989-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Lei Dai, Ying Wang 0001, Cheng Liu, Fuping Li, Huawei Li, Xiaowei Li |
Reexamining CGRA Memory Sub-system for Higher Memory Utilization and Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022, pp. 42-49, 2022, IEEE, 978-1-6654-6186-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Long Tan, Mingyu Yan, Duo Wang, Wenming Li, Xiaochun Ye, Dongrui Fan |
MatGraph: An Energy-Efficient and Flexible CGRA Engine for Matrix-Based Graph Analytics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP ![In: Algorithms and Architectures for Parallel Processing - 22nd International Conference, ICA3PP 2022, Copenhagen, Denmark, October 10-12, 2022, Proceedings, pp. 351-372, 2022, Springer, 978-3-031-22676-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Long Tan, Mingyu Yan, Xiaochun Ye, Dongrui Fan |
HetGraph: A High Performance CPU-CGRA Architecture for Matrix-based Graph Analytics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6 - 8, 2022, pp. 387-391, 2022, ACM, 978-1-4503-9322-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Nikhil Sambhus, Tarek S. Abdelrahman |
Reuse-Aware Partitioning of Dataflow Graphs on a Tightly-Coupled CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA/BDCloud/SocialCom/SustainCom ![In: IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking, ISPA/BDCloud/SocialCom/SustainCom 2022, Melbourne, Australia, December 17-19, 2022, pp. 458-467, 2022, IEEE, 978-1-6654-6497-0. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh |
REVAMP: a systematic framework for heterogeneous CGRA realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022 - 4 March 2022, pp. 918-932, 2022, ACM, 978-1-4503-9205-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao |
GEML: GNN-based efficient mapping method for large loop applications on CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 337-342, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra |
PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022, pp. 127-132, 2022, ACM, 978-1-4503-9142-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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21 | Mark Wijtvliet, Henk Corporaal, Akash Kumar 0001 |
CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 14(4), pp. 19:1-19:28, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Clark W. Barrett, Mark Horowitz, Pat Hanrahan, Priyanka Raina |
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2104.14155, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
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21 | Dennis Wolf 0001, Andreas Engel 0003, Tajas Ruschke, Andreas Koch 0001, Christian Hochberger |
UltraSynth: Insights of a CGRA Integration into a Control Engineering Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 93(5), pp. 463-479, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Rohit Prasad, Satyajit Das, Kevin J. M. Martin, Philippe Coussy |
Floating Point CGRA based Ultra-Low Power DSP Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 93(10), pp. 1159-1171, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele |
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1192-1197, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Chen Yin, Qin Wang 0009, Jianfei Jiang 0001, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing |
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1394-1399, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Jungi Lee, Jongeun Lee |
NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021, pp. 1408-1413, 2021, IEEE, 978-3-9819263-5-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson |
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 24th Euromicro Conference on Digital System Design, DSD 2021, Virtual Event / Palermo, Sicily, Italy, September 1-3, 2021, pp. 35-42, 2021, IEEE, 978-1-6654-2703-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Ramon Wirsch, Christian Hochberger |
Towards Transparent Dynamic Binary Translation from RISC-V to a CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings, pp. 118-132, 2021, Springer, 978-3-030-81681-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Chilankamol Sunny, Satyajit Das, Kevin J. M. Martin, Philippe Coussy |
Hardware Based Loop Optimization for CGRA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings, pp. 65-80, 2021, Springer, 978-3-030-79024-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Aleksandr Penskoi |
Synthesis Method for CGRA Processors based on Imitation Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 10th Mediterranean Conference on Embedded Computing, MECO 2021, Budva, Montenegro, June 7-10, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3912-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Zahra Ebrahimi, Akash Kumar 0001 |
BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Maria D. Vieira, Michael Canesche, Lucas Bragança, Josué Campos, Mateus Silva, Ricardo S. Ferreira 0001, José Augusto Miranda Nacif |
RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, pp. 1-5, 2021, IEEE, 978-1-7281-9201-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Graham Gobieski, Ahmet Oguz Atli, Kenneth Mai, Brandon Lucia, Nathan Beckmann |
Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Virtual Event / Valencia, Spain, June 14-18, 2021, pp. 1027-1040, 2021, IEEE, 978-1-6654-3333-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Jinho Lee, Trevor E. Carlson |
Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, pp. 1207-1212, 2021, IEEE, 978-1-6654-3274-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Yijiang Guo, Jiarui Wang, Jiaxi Zhang 0001, Guojie Luo |
Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, pp. 943-948, 2021, IEEE, 978-1-6654-3274-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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21 | Guiqiang Peng, Leibo Liu, Sheng Zhou 0001, Shouyi Yin, Shaojun Wei |
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 55(2), pp. 505-519, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Jiang Sha, Wenbo Song, Yu Gong, Yingying Zhao |
Accelerating Nested Conditionals on CGRA With Tag-Based Full Predication Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 109401-109410, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Zhongyuan Zhao 0004, Weiguang Sheng, Qin Wang 0009, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao |
Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 31(9), pp. 2201-2219, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Muhammad Shafique 0001 |
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10), pp. 2558-2571, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Wei Ge, Shenghua Chen, Benyu Liu, Min Zhu 0001, Bo Liu 0019 |
A Power Analysis Attack Countermeasure Based on Random Data Path Execution For CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 103-D(5), pp. 1013-1022, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Satyajit Das, Rohit Prasad, Kevin J. M. Martin, Philippe Coussy |
Energy Efficient Acceleration Of Floating Point Applications Onto CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 2020 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2020, Barcelona, Spain, May 4-8, 2020, pp. 1563-1567, 2020, IEEE, 978-1-5090-6631-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Guilherme Korol, Michael Guilherme Jordan, Marcelo Brandalero, Michael Hübner 0001, Mateus Beck Rutzig, Antonio Carlos Schneider Beck |
MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020, pp. 33-39, 2020, IEEE, 978-1-7281-9902-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | George Charitopoulos, Dionisios N. Pnevmatikatos |
A CGRA Definition Framework for Dataflow Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed]., pp. 271-287, 2020, Springer, 978-3-030-44533-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Tong Geng, Chunshu Wu, Cheng Tan 0002, Bo Fang, Ang Li 0006, Martin C. Herbordt |
CQNN: a CGRA-based QNN Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPEC ![In: 2020 IEEE High Performance Extreme Computing Conference, HPEC 2020, Waltham, MA, USA, September 22-24, 2020, pp. 1-7, 2020, IEEE, 978-1-7281-9219-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin |
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, 2020, IEEE, 978-1-7281-1085-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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21 | Loris Duch, Soumya Basu 0002, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza |
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 11(2), pp. 50-53, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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21 | Zhengyu Chen 0002, Hai Zhou 0001, Jie Gu 0001 |
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(11), pp. 2655-2667, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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21 | Dajiang Liu, Shouyi Yin, Guojie Luo, Jiaxing Shang, Leibo Liu, Shaojun Wei, Yong Feng 0002, Shangbo Zhou |
Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12), pp. 2271-2283, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
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