Search results for "Carry-Propagation-Free"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001	High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multiple-valued current-mode circuits, high-speed multiplier, carry-propagation-free addition trees, multiple-valued current-mode, carry-propagation-free addition, area efficient design, VLSI, VLSI, tree structure, multiplying circuits, redundant number representations, number representations, multiplier design
43	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
43	Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, Nicolas Vaucher	Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers.	VLSI Design	1995	DBLP DOI BibTeX RDF	layout synthesis, radix-2 dividers, pseudo-radix-4 dividers, redundant number notation, carry-propagation-free addition/subtraction, VLSI, logic CAD, circuit layout CAD, CMOS logic circuits, VLSI implementation, integrated circuit layout, redundant number systems, dividing circuits, digit-recurrence division
32	Naofumi Takagi	Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.	ISMVL	2002	DBLP DOI BibTeX RDF	carry-save form, carry-propagation-free addition, multiplier recoding, computer arithmetic, signed-digit number representation, digit-recurrence algorithm
32	Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima	High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	binary integer multiplication, carry-propagation-free adder, high-speed multiplier, redundant binary representation, VLSI, Arithmetic operations, hardware algorithm, signed-digit number representation
26	Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi	Exploration of approximate multipliers design space using carry propagation free compressors.	ASP-DAC	2018	DBLP DOI BibTeX RDF
26	Yasuhiro Takahashi, Kei-ichi Konta, Kazukiyo Takahashi, Michio Yokoyama, Kazuhiro Shouno, Mitsuru Mizunuma	Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
22	KiJong Lee, Kiyoung Choi	Self-timed divider based on RSD number system.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
16	Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi 0001	Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms.	ISMVL	2003	DBLP DOI BibTeX RDF
11	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001, Hiroshi Inokawa, Yasuo Takahashi	A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.	ISMVL	2004	DBLP DOI BibTeX RDF
11	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
11	Naofumi Takagi	A Hardware Algorithm for Computing Reciprocal Square Root.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
11	Naofumi Takagi, Seiji Kuwahara	A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	computer graphics, Computer arithmetic, VLSI algorithm, Euclidean norm, digit-recurrence algorithm