Search results for "Cosynthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
161	R. Miller, Hal Carter, K. Davis, Satish Venkatesan	Hardware/software cosynthesis: multiple constraint satisfaction and component retrieval.	ICECCS	1996	DBLP DOI BibTeX RDF	hardware software cosynthesis, multiple constraint satisfaction, high-level system specification, constraint-driven retrieval, candidate solution evaluation, cosynthesis tool, multiple design constraints, two constraint Fidducia-Matheyses approach, flexible component retrieval, design database, ad hoc querying, systems analysis, hardware description language, design space, component retrieval
130	Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt	Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
130	Bharat P. Dave, Niraj K. Jha	COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
102	Hyunok Oh, Soonhoi Ha	Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints.	CODES	2002	DBLP DOI BibTeX RDF	hardware-software cosynthesis, multi-task, multi-mode
95	Gul N. Khan, Usman Ahmed	Hardware-Software Cosynthesis of Multiprocessor Embedded Architectures.	AINA Workshops (1)	2007	DBLP DOI BibTeX RDF
85	Pao-Ann Hsiung	CMAPS: a cosynthesis methodology for application-oriented parallel systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	application-oriented general-purpose multiprocessors, hardware-software modeling and cosynthesis, requirements analysis
78	Chen-Wei Liu, Yao-Wen Chang	Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
68	Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian	Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	cosynthesis, energy, Real-time scheduling, MPSoC
68	Jörg Henkel, Rolf Ernst	A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.	ISSS	1995	DBLP DOI BibTeX RDF	hardware runtime, hardware software cosynthesis, local estimation techniques, local list scheduling, path-based technique, scheduling, computational complexity, computer architecture, quality, systems analysis, circuit CAD, computation time, optimising compilers, synthesis tools
61	Li Shang, Robert P. Dick, Niraj K. Jha	SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
61	Robert P. Dick, Niraj K. Jha	MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
61	Jörg Wilberg, Raul Camposano, Wolfgang Rosenstiel	Design flow for hardware/software cosynthesis of a video compression system.	CODES	1994	DBLP DOI BibTeX RDF
51	Hyunok Oh, Soonhoi Ha	A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling.	CODES	1999	DBLP DOI BibTeX RDF	distributed heterogeneous embedded system, hardware-software cosynthesis, system-on-chip
51	Peter Bjørn-Jørgensen, Jan Madsen	Critical path driven cosynthesis for heterogeneous target architectures.	CODES	1997	DBLP DOI BibTeX RDF	critical path driven, heterogeneous target architectures, list based scheduling, path driven cosynthesis, single-rate systems, task scheduling, processor scheduling, data dependencies, target architecture
44	Hyunuk Jung, Hoeseok Yang, Soonhoi Ha	Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	VHDL, system level design, RTL, dataflow graph (DFG), HW/SW codesign
44	Sudeep Pasricha, Nikil D. Dutt	A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
44	Robert P. Dick, Niraj K. Jha	COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
44	Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	A cosynthesis algorithm for application specific processors with heterogeneous datapaths.	ASP-DAC	2004	DBLP DOI BibTeX RDF
44	Hyunuk Jung, Soonhoi Ha	Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	automatic hardware synthesis, VHDL, system level design, dataflow graph(DFG), HW/SW codesign
44	Shampa Chakraverty	Cosynthesis of multiprocessor architectures with high availability.	VLSI Design	2004	DBLP DOI BibTeX RDF
44	Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri	An Evolutionary Scheme for Cosynthesis of Real-Time Systems.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	stochastic task scheduling, hierarchical genetic algorithm, multiprocessor architectures, embedded real-time systems, Hardware software co-synthesis
44	Wayne H. Wolf	Object-oriented cosynthesis of distributed embedded systems.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	object-oriented co-synthesis, distributed embedded systems, hardware-software co-design
44	Rolf Ernst, Jörg Henkel, Thomas Benner	Hardware-Software Cosynthesis for Microcontrollers.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
41	Minyoung Kim, Sudarshan Banerjee, Nikil D. Dutt, Nalini Venkatasubramanian	Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	cosynthesis, energy, real-time scheduling, MPSoC
41	Rick Miller	VHDL-based EDA Tool Implementation with Java.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Hardware/Software CoSynthesis, Java, VHDL
41	Adel Baganne, Jean Luc Philippe, Eric Martin 0001	Hardware interface design for real time embedded systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem
41	Ti-Yen Yen, Wayne H. Wolf	Performance estimation for real-time distributed embedded systems.	ICCD	1995	DBLP DOI BibTeX RDF	real-time distributed embedded systems, efficient analysis algorithm, application task, cosynthesis algorithms, bounding algorithms, performance evaluation, real-time systems, distributed processing, ASICs, data dependencies, execution time, performance estimation, CPUs, tight bounds, communication links
34	Yuichiro Miyaoka, Jinku Choi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
34	Shampa Chakraverty, C. P. Ravikumar	A Stochastic Framework for Co-synthesis of Real-Time Systems.	LCTES	2000	DBLP DOI BibTeX RDF
27	Adam Górski, Maciej Ogorzalek	Genetic Programming based Algorithm for HW/SW Cosynthesis of Distributed Embedded Systems Specified using Conditional Task Graph.	SENSORNETS	2022	DBLP DOI BibTeX RDF
27	Adam Górski, Maciej Ogorzalek	Genetic Programming based Iterative Improvement Algorithm for HW/SW Cosynthesis of Distributted Embedded Systems.	SENSORNETS	2021	DBLP DOI BibTeX RDF
27	Adam Górski, Maciej Ogorzalek	Genetic Programming based Constructive Algorithm with Penalty Function for Hardware/Software Cosynthesis of Embedded Systems.	ICSOFT	2021	DBLP DOI BibTeX RDF
27	Debayan Roy, Licong Zhang, Wanli Chang 0001, Sanjoy K. Mitter, Samarjit Chakraborty	Semantics-Preserving Cosynthesis of Cyber-Physical Systems.	Proc. IEEE	2018	DBLP DOI BibTeX RDF
27	Nishit Ashok Kapadia, Sudeep Pasricha	A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
27	Kunal Arya	Hierarchical Transactions for Hardware/Software Cosynthesis.		2014	RDF
27	Shampa Chakraverty, Anil Kumar	Erratum: A rule-based availability-driven cosynthesis scheme.	Des. Autom. Embed. Syst.	2007	DBLP DOI BibTeX RDF
27	Shampa Chakraverty, Anil Kumar	A rule-based availability-driven cosynthesis scheme.	Des. Autom. Embed. Syst.	2007	DBLP DOI BibTeX RDF
27	Marcus T. Schmitz, Bashir M. Al-Hashimi, Petru Eles	Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
27	Nozomu Togawa, Takao Totsuka, Tatsuhiko Wakui, Masao Yanagisawa, Tatsuo Ohtsuki	A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
27	Salim Ouadjaout, Marie-France Albenge, Dominique Houzet	VSIA Interface Cosynthesis.	DELTA	2002	DBLP DOI BibTeX RDF	VSIA, SoC, Co-design, interface synthesis
27	Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi	Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs.	ASP-DAC	2000	DBLP DOI BibTeX RDF
27	Robert P. Dick, Niraj K. Jha	Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
27	Karsten Lüth, Jürgen Niehaus, Thomas Peikenkamp	HW/SW Cosynthesis Using Statecharts and Symbolic Timing Diagrams.	International Workshop on Rapid System Prototyping	1998	DBLP DOI BibTeX RDF
27	Rolf Ernst, Jörg Henkel, Thomas Benner, Wei Ye 0002, Ulrich Holtmann, Dirk Herrmann, Michael Trawny	The COSYMA environment for hardware/software cosynthesis of small embedded systems.	Microprocess. Microsystems	1996	DBLP DOI BibTeX RDF
27	Dang S. Sananikone	Cosynthesis of embedded systems using coloured interpreted petri nets.		1996	RDF
27	Thomas Benner, Rolf Ernst, Achim Österling	Scalable performance scheduling for hardware-software cosynthesis.	EURO-DAC	1995	DBLP DOI BibTeX RDF
27	Thomas Benner, Rolf Ernst, Ingo Könenkamp, P. Schüler, H.-C. Schaub	A prototyping system for verification and evaluation in hardware-software cosynthesis.	RSP	1995	DBLP DOI BibTeX RDF
27	Kunle Olukotun, Rachid Helaihel, Jeremy R. Levitt, Ricardo Ramírez	A software-hardware cosynthesis approach to digital system simulation.	IEEE Micro	1994	DBLP DOI BibTeX RDF
27	Thomas Benner, Rolf Ernst, Ingo Könenkamp, Ulrich Holtmann, P. Schüler, H.-C. Schaub, N. Serafimov	FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesis.	FPL	1994	DBLP DOI BibTeX RDF
27	Martyn Edwards, John Forrest	A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems.	EDAC-ETC-EUROASIC	1994	DBLP DOI BibTeX RDF
27	Rajesh K. Gupta 0001, Giovanni De Micheli	Hardware-Software Cosynthesis for Digital Systems.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
24	Jesper Grode, Peter Voigt Knudsen, Jan Madsen	Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System.	DATE	1998	DBLP DOI BibTeX RDF	Cosynthesis, LYCOS System, Resource Allocation, HW/SW Partitioning
17	Francisco Assis Moreira do Nascimento, Marcio F. da S. Oliveira, Flávio Rech Wagner	MDE approach to the co-synthesis of embedded systems using a MOF-based internal design representation.	MOMPES	2009	DBLP DOI BibTeX RDF
17	Gul N. Khan, Anika Awwal	Codesign of Embedded Systems with Process/Module Level Real-Time Deadlines.	CSE (2)	2009	DBLP DOI BibTeX RDF
17	Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo	PeaCE: A hardware-software codesign environment for multimedia embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	hardware-software cosimulation, embedded systems, design-space exploration, model-based design, Hardware-software codesign
17	Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz, Petru Eles	Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.	DSD	2005	DBLP DOI BibTeX RDF
17	Amjad Mohsen, Richard Hofmann	Characterizing Power Consumption and Delay of Functional/Library Components for Hardware/Software Co-Design of Embedded Systems.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
17	Keith S. Vallerio, Niraj K. Jha	Task graph transformation to aid system synthesis.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
17	David L. Rhodes, Wayne H. Wolf	RAGS-real-analysis ALAP-guided synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
17	Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Area/delay estimation for digital signal processor cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Yanbing Li, Wayne H. Wolf	Hardware/software co-synthesis with memory hierarchies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Peter Voigt Knudsen, Jan Madsen	Integrating communication protocol selection with hardware/software codesign.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
17	Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki	A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing.	ASP-DAC	1999	DBLP DOI BibTeX RDF
17	Rajesh K. Gupta 0001, Giovanni De Micheli	Specification and analysis of timing constraints for embedded systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
17	Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto	A methodology for control-dominated systems codesign.	CODES	1994	DBLP DOI BibTeX RDF