Search results for "DBC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	Jayanta Banerjee, David K. Hsiao, Richard I. Baum	Concepts and Capabilities of a Database Computer.	ACM Trans. Database Syst.	1978	DBLP DOI BibTeX RDF	database computers, mass memory, structure memory, security, clustering, performance, content-addressable memory, keywords
88	Jai Menon 0001, David K. Hsiao	Access Control Mechanism of a Database Computer (DBC).	Computer Architecture for Non-Numeric Processing	1980	DBLP DOI BibTeX RDF
86	Therapon Skotiniotis, David H. Lorenz	Cona: aspects for contracts and contracts for aspects.	OOPSLA Companion	2004	DBLP DOI BibTeX RDF	design by contract (DBC), aspect-oriented programming (AOP)
67	Yogesh Singh, Anju Saha	Enhancing Data Flow Testing of Classes through Design by Contract.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	design by contract, object oriented testing, data flow testing
60	Jayanta Banerjee, David K. Hsiao	A methodology for supporting existing CODASYL databases with new database machines.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	CODASYL data model, DBC, Database transformation, Network data model, Relative performance, Database management systems, Query translation, Database machines, CODASYL
53	Robert Hirschfeld, Michael Perscheid, Christian Schubert, Malte Appeltauer	Dynamic contract layers.	SAC	2010	DBLP DOI BibTeX RDF	dynamic contract layers, design by contract, software composition, context-oriented programming
53	Wladimir Araujo, Lionel C. Briand, Yvan Labiche	Concurrent Contracts for Java in JML.	ISSRE	2008	DBLP DOI BibTeX RDF
53	Zinovi Rabinovich, Jeffrey S. Rosenschein, Gal A. Kaminka	Dynamics based control with an application to area-sweeping problems.	AAMAS	2007	DBLP DOI BibTeX RDF	dynamics based control, target dynamics, robotics, multiagent systems, control
53	Patrice Chalin	Are Practitioners Writing Contracts?	RODIN Book	2006	DBLP DOI BibTeX RDF	program assertions, empirical study, design by contract, Eiffel
53	Reinhold Plösch	Design by Contract for Python.	APSEC	1997	DBLP DOI BibTeX RDF
42	Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun 0001, Xueqing Li, Huazhong Yang	A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
42	Haipeng Duan, Qin Chen, Xuan Wang, Depeng Cheng, Xin Chen, Xu Wu, Dongming Wang 0002, Lianming Li	A Ku-band transmitter front-end in 65-nm CMOS with >45-dBc image-rejection ratio and >43-dBc LOFT suppression.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
42	Shiwei Zhang, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
42	Zhaoqi Chen, Chunqi Shi, Yuri Lu, Runxi Zhang, Hao Deng 0003, Jinghong Chen	A 71-86 GHz Cascaded Harmonic Enhanced Tripler with -69 dBc Fundamental and -66 dBc Second Harmonic Suppression.	ISCAS	2022	DBLP DOI BibTeX RDF
42	Guo Wei, Keping Wang, Mengqian Cui, Hao Zhang	An Inductor-Less RF Transmitter Using Harmonic-Rejection Edge Combiner with -40 dBc HD3 and -52 dBc HD5 for Low-Power Biomedical Applications.	ISCAS	2022	DBLP DOI BibTeX RDF
42	Mark D. Hickle, Kevin Grout, Curtis Grens, Gregory M. Flewelling, Steven Eugene Turner	A Single-Chip 25.3-28.0 GHz SiGe BiCMOS PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset and -96 dBc Reference Spurs.	BCICTS	2021	DBLP DOI BibTeX RDF
42	Hung-Yi Huang, Tai-Haur Kuo	A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing.	IEEE J. Solid State Circuits	2020	DBLP DOI BibTeX RDF
42	Philipp Thomas, Markus Grözing, Manfred Berroth	32-GS/s SiGe Track-and-Hold Amplifier with 58-GHz Bandwidth and -64-dBc to -29-dBc HD3.	ICECS	2020	DBLP DOI BibTeX RDF
42	Jingcheng Tao, Chun-Huat Heng	A 2.2-GHz 3.2-mW DTC-Free Sampling ΔΣ Fractional-N PLL With -110-dBc/Hz In-Band Phase Noise and -246-dB FoM and -83-dBc Reference Spur.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
42	Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski	An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2018	DBLP DOI BibTeX RDF
42	J. Rimmelspacher, Robert Weigel, Amelie Hagelauer, Vadim Issakov	A Quad-Core 60 GHz Push-Push 45 nm SOI CMOS VCO with -101.7 dBc/Hz Phase Noise at 1 MHz offset, 19 % Continuous FTR and -187 dBc/Hz FoMT.	ESSCIRC	2018	DBLP DOI BibTeX RDF
42	Cheng-Ru Ho, Mike Shuo-Wei Chen	A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
42	Shiyu Su, Mike Shuo-Wei Chen	A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
42	Yongjian Tang, Joost Briaire, Kostas Doris, Robert H. M. van Veldhoven, Pieter C. W. van Beek, Hans Hegt, Arthur H. M. van Roermund	A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
40	Alexandre A. B. Lima, Camille Furtado, Patrick Valduriez, Marta Mattoso	Parallel OLAP query processing in database clusters with data replication.	Distributed Parallel Databases	2009	DBLP DOI BibTeX RDF	OLAP query processing, Virtual partitioning, Dynamic load balancing, Parallel databases, Partial replication, Database clusters
40	Le Wang, Parag Upadhyaya, Pinping Sun, Yang Zhang, Deuk Hyoun Heo, Yi-Jan Emery Chen, DongHo Jeong	A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Sang-Woon Kim, B. John Oommen	On Optimizing Dissimilarity-Based Classification Using Prototype Reduction Schemes.	ICIAR (1)	2006	DBLP DOI BibTeX RDF
40	Marc Lohmann, Stefan Sauer 0001, Gregor Engels	Executable Visual Contracts.	VL/HCC	2005	DBLP DOI BibTeX RDF
40	Hong-Sing Kao, Chung-Yu Wu	An improved low-power CMOS direct-conversion transmitter for GHz wireless communication applications.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
34	J. M. Pierre Langlois, Dhamin Al-Khalili	Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
34	J. M. Pierre Langlois, Dhamin Al-Khalili	A low power direct digital frequency synthesizer with 60 dBc spectral purity.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	DDFS, DDS, phase to sine amplitude conversion, low power
34	Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen	A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Jon Page	A Study of a Parallel Database Machine and its Performance the NCR/Teradata DBC/1012.	BNCOD	1992	DBLP DOI BibTeX RDF
34	Felipe Cariño, Pekka Kostamaa	Exegesis of DBC/1012 and P-90 - Industrial Supercomputer Database Machines.	PARLE	1992	DBLP DOI BibTeX RDF
27	Clément Hurlin	Specifying and checking protocols of multithreaded classes.	SAC	2009	DBLP DOI BibTeX RDF	protocols, object-orientation, multithreading, design by contract
27	Eduardo Gerardo Mendizabal Ruiz, George Biros, Ioannis A. Kakadiaris	An Inverse Scattering Algorithm for the Segmentation of the Luminal Border on Intravascular Ultrasound Data.	MICCAI (1)	2009	DBLP DOI BibTeX RDF
27	Yang Liu, Ashok Kumar Srivastava, Yao Xu	A switchable PLL frequency synthesizer and hot carrier effects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
27	Leburu Manojkumar, Arun Mohan 0003, Nagendra Krishnapura	A Comparison of Approaches to Carrier Generation for Zigbee Transceivers.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Burak Çatli, Mona Mostafa Hella	A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Sinisa Milicevic, Leonard MacEachern	A phase-frequency detector and a charge pump design for PLL applications.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Yang Zhang, Peng Liu, Deuk Hyoun Heo	A low-phase-noise LC QVCO with bottom-series coupling and capacitor tapping.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Zhenyu Yang, Zhangwen Tang, Hao Min	A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
27	Luís Bica Oliveira, Jorge R. Fernandes, Manuel Medeiros Silva, Igor M. Filanovsky, Chris J. M. Verhoeven	Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation Oscillator.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Adnan Gundel, William N. Carr	A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Lenwood S. Heath, Amrita Pati	Genomic Signatures in De Bruijn Chains.	WABI	2007	DBLP DOI BibTeX RDF
27	Vladimir Stankovic 0001, Samuel Cheng 0001, Zixiang Xiong	On dualities in multiterminal coding problems.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
27	Jian Li, Caixin Sun, Qian Du 0001	A New Box-Counting Method for Estimation of Image Fractal Dimension.	ICIP	2006	DBLP DOI BibTeX RDF
27	Chih-Wei Yao, Alan N. Willson Jr.	Energy circulation quadrature LC-VCO.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Ahmed Allam, Igor M. Filanovsky, Luís Bica Oliveira, Jorge R. Fernandes	Synchronization of mutually coupled LC-oscillators.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Igor Miletic, Ralph Mason	Quantization noise reduction using multiphase PLLs.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Inn-yeal Oh, Hyung Joon Jeon	The Verification of Linearizer for Wibro PAM.	ICCSA (2)	2006	DBLP DOI BibTeX RDF	pre-distorter, IM generator, variable attenuator, Wibro PAM, phase shifter
27	Xizhong Zheng, Robert Rettinger, Romain Gengler	Closure Properties of Real Number Classes under CBV Functions.	Theory Comput. Syst.	2005	DBLP DOI BibTeX RDF
27	Ferdous Ahmed Sohel, Laurence S. Dooley, Gour C. Karmakar	A dynamic Bezier curve model.	ICIP (2)	2005	DBLP DOI BibTeX RDF
27	Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia	Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing.	SBCCI	2005	DBLP DOI BibTeX RDF	resistor biasing, low power, wireless, CMOS, low voltage, voltage controlled oscillator (VCO), phase noise
27	Brian Welch, Jing-Hong Conan Zhan, Kevin T. Kornegay	A family of SiGe quadrature oscillators for microwave applications.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
27	Lin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do	A novel methodology for the design of LC tank VCO with low phase noise.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
27	Chung-Yu Wu, Chi-Yao Yu	A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
27	Hyung-Seuk Kim, Mourad N. El-Gamal	A 1-V fully integrated CMOS frequency synthesizer for 5-GHz WLAN.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
27	Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen	1-V 7-mW dual-band fast-locked frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	HiperLAN, WLAN, low-power design, phase-locked loops (PLLs), voltage-controlled oscillator (VCO), phase noise, frequency synthesizer
27	Robert Rettinger, Xizhong Zheng	On the Turing Degrees of Divergence Bounded Computable Reals.	CiE	2005	DBLP DOI BibTeX RDF
27	Jonghae Kim, Jean-Olivier Plouchart, Noah Zamdmer, Melanie Sherony, Yue Tan, Meeyoung Yoon, Robert Trzcinski, Mohamed Talbi, John Safran, Asit Ray, Lawrence F. Wagner	A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate.	ISLPED	2003	DBLP DOI BibTeX RDF	SOI CMOS, high resistivity substrate, phase NoiseFOM, low power, VCO, RF design
27	Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang	1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
27	Charan Meenakarn, Apinunt Thanachayanont	A sine-output ROM-less direct digital frequency synthesiser using a polynomial approximation.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
27	Charan Meenakarn, Apinunt Thanachayanont	100-MHz CMOS direct digital synthesizer with 10-bit DAC.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
27	Jayanta Banerjee, David K. Hsiao	The Use of a Database Machine for Supporting Relational Databases.	Computer Architecture for Non-Numeric Processing	1978	DBLP DOI BibTeX RDF
21	Sooncheol Bae, Hansik Oh, Woojin Choi, Jaekyung Shin, Yifei Chen, Hyeongjin Jeon, Young Chan Choi, Sunwoo Nam, Soohyun Bin, Yoonjung Lee, Kang-Yoon Lee, Keum-Cheol Hwang, Youngoo Yang	60 W Class-E/F3 Switching Power Amplifier With an Improved Second Harmonic Distortion of -49 dBc.	IEEE Access	2024	DBLP DOI BibTeX RDF
21	Behnam Moradi, Xuyang Liu, Hamidreza Aghasi	A 76-82 GHz VCO in 65 nm CMOS With 189.3 dBc/Hz PN FOM and -0.6 dBm Harmonic Power for mm-Wave FMCW Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
21	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
21	Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu	A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
21	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
21	Jinwei Li, Bing Sun, Jiawei Huang, Hudong Chang, Rui Jia, Honggang Liu	A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
21	Huanyu Wang, Lina Huang, Yutong Liu, Zhenyuan Xu, Lu Zhang, Tuming Zhang, Yuxiang Feng, Qing Hua	Highly Integrated DBC-Based IPM with Ultra-Compact Size for Low Power Motor Drive Applications.	IEICE Trans. Electron.	2023	DBLP DOI BibTeX RDF
21	Ioanna Apostolina, Danilo Manstretta	A 20-GHz Multi-Core Digitally Controlled Oscillator with -118 dBc/Hz Phase Noise at 1MHz Offset in 28nm CMOS.	PRIME	2023	DBLP DOI BibTeX RDF
21	Srayan Sankar Chatterjee, Arpit Sahni, Harikrishna Kambham, Zia Abbas, Abhishek Srivastava 0002	Design and Analysis of Low Power 20 GHz Colpitts VCO with FoM of 196.26 dBc/Hz.	MWSCAS	2023	DBLP DOI BibTeX RDF
21	Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi	A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
21	Xinyu Shen, Zhao Zhang 0004, Guike Li, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
21	Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka	A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
21	Hao Guo, Taiyun Chi	An 86.5-105.6GHz LO Generator with Cascaded Implicit Frequency Quintupling and Tripling Achieving -107.7 dBc/Hz Phase Noise and 191. 2dBc/Hz FoM at 1MHz Offset.	CICC	2023	DBLP DOI BibTeX RDF
21	Yunbo Huang, Yong Chen 0005, Chaowei Yang, Pui-In Mak, Rui Paulo Martins	A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output.	ISCAS	2023	DBLP DOI BibTeX RDF
21	Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena	A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications.	VLSID	2023	DBLP DOI BibTeX RDF
21	Yixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.	A-SSCC	2023	DBLP DOI BibTeX RDF
21	Hanzhang Cao, Tongde Huang, Xiaolong Liu, Hao Wang, Jin Jin, Wen Wu	A 5.2GHz Trifilar Transformer-Based Class-F23 Noise Circulating VCO with FoM of 192.6 dBc/Hz.	A-SSCC	2023	DBLP DOI BibTeX RDF
21	Anik Batabyal, Rajesh Zele	A 197 dBc/Hz FoMT 24.8-28.97 GHz Class-F VCO Using Single-Turn Multi-Tap Inductor.	APCCAS	2023	DBLP DOI BibTeX RDF
21	Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems	A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
21	Chi Zhang, Cai Chen, Yi Zhang, Yiyang Yan, Yong Kang	A Stress-Relieved Method Based on Bottom Pattern Design Considering Thermal and Mechanical Behavior of DBC Substrate.	IEEE Access	2022	DBLP DOI BibTeX RDF
21	Zunsong Yang, Yong Chen 0005, Jia Yuan, Pui-In Mak, Rui Paulo Martins	A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
21	Gaurav Kumar Sharma, Arun Kishor Johar, Dharmendar Boolchandani	Low Power, Wide Range Synthesizer for 534 MHz-18.56 GHz Band with FoM of - 192.45 dBc/Hz.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
21	Pengfei Ma, Youxi Wu, Yan Li 0087, Lei Guo 0015, Zhao Li 0007	DBC-Forest: Deep forest with binning confidence screening.	Neurocomputing	2022	DBLP DOI BibTeX RDF
21	Wenxuan Jiang, Yujun Liu, Ji Wang, Rui Li, Xiao Liu, Jian Zhang	Problems of the Grid Size Selection in Differential Box-Counting (DBC) Methods and an Improvement Strategy.	Entropy	2022	DBLP DOI BibTeX RDF
21	Behnam Samadpoor Rikan, David Kim, Kyung-Duk Choi, Arash Hejazi, Joon-Mo Yoo, YoungGun Pu, Seokkee Kim, Hyungki Huh, Yeonjae Jung, Kang-Yoon Lee	T/R RF Switch with 150 ns Switching Time and over 100 dBc IMD for Wideband Mobile Applications in Thick Oxide SOI Process.	Sensors	2022	DBLP DOI BibTeX RDF
21	Enne Wittenhagen, Patrick Kurth, Tobias Kaiser, Friedel Gerfers	A TI 12 GS/s Sampled Beam-Forming Receiver for a $2\times 2$ Antenna-Array with 69 dBc SFDR.	ICECS 2022	2022	DBLP DOI BibTeX RDF
21	Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua	A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS.	ESSCIRC	2022	DBLP DOI BibTeX RDF
21	Dong-Hyun Yoon, Kwang-Hyun Baek, Tony Tae-Hyoung Kim	A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process.	ESSCIRC	2022	DBLP DOI BibTeX RDF
21	Bingtao Zhang, Weimin Wu, Ning Gao, Eftichis Koutroulis 0001, Jianmin Chen, Gang Lu, Henry Shu-Hung Chung, Frede Blaabjerg	An Improved DBC-MPC Strategy for LCL-Filtered Grid-connected Inverters.	IECON	2022	DBLP DOI BibTeX RDF
21	Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka	A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Sarthak Sharma, Hao Gao 0001, Gernot Hueber, Andrea Mazzanti	A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic Extraction.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
21	Muhammed Bolatkale, Robert Rutten, Hans Brekelmans, Shagun Bajoria, Yihan Gao, Bernard Burdiek, Lucien J. Breems	A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction.	ISSCC	2022	DBLP DOI BibTeX RDF
21	Ahmed Mohammed, Lajan Burhan, Kawan Ghafor, Warzer Sarwar, Wael Mahmood	Artificial neural network (ANN), M5P-tree, and regression analyses to predict the early age compression strength of concrete modified with DBC-21 and VK-98 polymers.	Neural Comput. Appl.	2021	DBLP DOI BibTeX RDF
21	Hanyang Su, Jingcheng Tao, Siegfred D. Balon, Chun-Huat Heng	A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
21	Ji-Hwan Seol, Kyojin Choo, David T. Blaauw, Dennis Sylvester, Taekwang Jang	Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF