Search results for "DLX"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
111	Manish Amde, Ivan Blunno, Christos P. Sotiriou	Automating the design of an asynchronous DLX microprocessor.	DAC	2003	DBLP DOI BibTeX RDF	DLX, asynchronous, design flow
96	Milos Becvár, Stanislav Kahánek	VLIW-DLX simulator for educational purposes.	WCAE	2007	DBLP DOI BibTeX RDF	simulation, education, computer architecture, VLIW
64	Joseph A. Driscoll, Ralph M. Butler, Joelle M. Key	A virtual machine environment for teaching the development of system software.	ACM Southeast Regional Conference	2004	DBLP DOI BibTeX RDF	DLX, education, GUI, virtual machine, system software
63	Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, Jestoni V. Zarsuela, Anastacia P. Ballesil, Joy Alinda Reyes	DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache.	ICECS	2008	DBLP DOI BibTeX RDF
48	Krishnamani Kalyanasundaram, R. K. Shyamasundar	Formal verification of pipelined processors with precise exceptions.	MEMOCODE	2004	DBLP DOI BibTeX RDF
48	Hemangee K. Kapoor	Formal Modelling and Verification of an Asynchronous DLX Pipeline.	SEFM	2006	DBLP DOI BibTeX RDF
48	Roland N. Ibbett	HASE DLX Simulation Model.	IEEE Micro	2000	DBLP DOI BibTeX RDF
32	K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula	Power Virus Generation Using Behavioral Models of Circuits.	VTS	2007	DBLP DOI BibTeX RDF	Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
32	Miroslav N. Velev	Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units.	CHARME	2005	DBLP DOI BibTeX RDF
32	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin	A Simulation Methodology for Software Energy Evaluation.	VLSI Design	1997	DBLP DOI BibTeX RDF
31	Nyoman Bogi Aditya Karna, Nimas Fatihah, Dong-Seong Kim 0002	Evaluation of DLX Microprocessor Instructions Efficiency for Image Compression.	ICTC	2019	DBLP DOI BibTeX RDF
31	Sujoy Pandit, Prateek Sikka	Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA.	ICCCNT	2018	DBLP DOI BibTeX RDF
31	Rajesh Kannan Megalingam, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Ashwin Mohan, Vivek Periye	Low power analysis of DLX processor datapath using a novel clocking scheme.	ICWET	2010	DBLP DOI BibTeX RDF
31	Roger Luis Uy, Marizel Bernardo, Josiel Erica	DARC2: 2nd generation DLX architecture simulator.	WCAE	2004	DBLP DOI BibTeX RDF
31	Elham Khorsandi Nia, Omid Fatemi	Multimedia extensions for DLX processor.	ICECS	2003	DBLP DOI BibTeX RDF
31	Chung-Ho Chen, Akida Wu	An enhanced DLX-based superscalar system simulator.	WCAE@HPCA	1997	DBLP DOI BibTeX RDF
31	Yinong Zhang, George B. Adams III	An interactive, visual simulator for the DLX pipeline.	WCAE@HPCA	1997	DBLP DOI BibTeX RDF
31	Philip M. Sailor, David R. Kaeli	The DLX instruction set architecture handbook.		1996	RDF
31	Robert Knuth	Quantitative Analyse von DLX-Pipeline-Architekturen.		1996	RDF
31	Valentín Valero Ruiz, Fernando Cuartero, Antonio Jose Garrido del Solo, Francisco J. Quiles 0001	A simulation tool of parallel architectures for digital image processing applications based on DLX processors.	ICIP (3)	1995	DBLP DOI BibTeX RDF
31	Barry S. Fagin, Pichet Chintrakulchai	Prototyping the DLX microprocessor.	RSP	1992	DBLP DOI BibTeX RDF
31	Herbert Grünbacher, Maziar Khosravipour	WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture.	ECBS	1996	DBLP DOI BibTeX RDF	teaching computer architecture, teaching computer organisation, teaching pipelining, DLX architecture, pipeline visualisation, WinDLX, MIPSim, ECBS
16	Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo	Enhancing bug hunting using high-level symbolic simulation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	bughunter, design for verification, symbolic simulation
16	Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil	Automatic Constraint Based Test Generation for Behavioral HDL Models.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Viswanathan Subramanian, Arun K. Somani	Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
16	Bita Gorjiara, Daniel Gajski	Automatic architecture refinement techniques for customizing processing elements.	DAC	2008	DBLP DOI BibTeX RDF	GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist
16	Ernesto Sánchez 0001, Giovanni Squillero	Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors.	Advances in Evolutionary Computing for System Design	2007	DBLP DOI BibTeX RDF
16	Edward K. Walters II, J. Eliot B. Moss, Trek S. Palmer, Timothy Richards, Charles C. Weems	Modeling Modern Micro-architectures using CASL.	IPDPS	2007	DBLP DOI BibTeX RDF
16	Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar	Module assignment for pin-limited designs under the stacked-Vdd paradigm.	ICCAD	2007	DBLP DOI BibTeX RDF
16	Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001	Low-power process-variation tolerant arithmetic units using input-based elastic clocking.	ISLPED	2007	DBLP DOI BibTeX RDF	elastic clocking, process tolerant, low power
16	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
16	Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou	Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
16	Sven Beyer, Christian Jacobi 0002, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul	Putting it all together - Formal verification of the VAMP.	Int. J. Softw. Tools Technol. Transf.	2006	DBLP DOI BibTeX RDF	Complete microprocessor verification, Tomasulo scheduler, Cache memory interface, Model checking, Formal methods, Theorem proving, Floating point unit
16	Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer	An Experimental Study of Soft Errors in Microprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture
16	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner	XFM: An incremental methodology for developing formal models.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Extreme formal modeling, prescriptive formal models, property ordering, property refactoring, formal specification, formal verification, extreme programming, SPIN, SMV
16	Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic.	DSN	2005	DBLP DOI BibTeX RDF
16	Tun Li, Dan Zhu, Yang Guo 0003, GongJie Liu, Sikun Li	MA2TG: A Functional Test Program Generator for Microprocessor Verification.	DSD	2005	DBLP DOI BibTeX RDF
16	Tun Li, Dan Zhu, Lei Liang, Yang Guo 0003, Sikun Li	Automatic functional test program generation for microprocessor verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
16	Seokkee Kim, Soo-Ik Chae	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor
16	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-based delay fault self-testing of pipelined processor cores.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
16	Dirk Leinenbach, Wolfgang J. Paul, Elena Petrova	Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes.	SEFM	2005	DBLP DOI BibTeX RDF
16	Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero	Code Generation for Functional Validation of Pipelined Microprocessors.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation
16	Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner	Extreme Formal Modeling (XFM) for Hardware Models.	MTV	2004	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai	Functional Verification of Pipelined Processors: A Case Study.	MTV	2004	DBLP DOI BibTeX RDF
16	Sonia López, Oscar Garnica, José Manuel Colmenar	Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.	PATMOS	2004	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Nikil D. Dutt	Graph-Based Functional Test Program Generation for Pipelined Processors.	DATE	2004	DBLP DOI BibTeX RDF
16	Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou	Handshake Protocols for De-Synchronization.	ASYNC	2004	DBLP DOI BibTeX RDF
16	Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Nikil D. Dutt	A Methodology for Validation of Microprocessors using Equivalence Checking.	MTV	2003	DBLP DOI BibTeX RDF
16	Sven Beyer, Christian Jacobi 0002, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul	Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.	CHARME	2003	DBLP DOI BibTeX RDF
16	Miroslav N. Velev	Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.	ITC	2003	DBLP DOI BibTeX RDF
16	Oswaldo Cadenas, Graham M. Megson	Pullpipelining: A technique for systolic pipelined circuits.	IWSOC	2003	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama	Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.	DATE	2002	DBLP DOI BibTeX RDF
16	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
16	Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai	Effectiveness of the ASIP design system PEAS-III in design of pipelined processors.	ASP-DAC	2001	DBLP DOI BibTeX RDF
16	Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick	A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	architectural verification, biased random instruction generation, correctness checking, design error coverage, design verification, coverage metrics
16	Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng	Functionally Testable Path Delay Faults on a Microprocessor.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
16	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
16	S. Ramesh 0001, Purandar Bhaduri	Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study.	CAV	1999	DBLP DOI BibTeX RDF
16	Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions.	ISSS	1999	DBLP DOI BibTeX RDF
16	Asheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau	V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration.	EUROMICRO	1999	DBLP DOI BibTeX RDF
16	Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalakrishnan	Decomposing the Proof of Correctness of pipelined Microprocessors.	CAV	1998	DBLP DOI BibTeX RDF
16	John Matthews, Byron Cook, John Launchbury	Microprocessor Specification in Hawk.	ICCL	1998	DBLP DOI BibTeX RDF	Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification
16	Aarti Gupta, Sharad Malik, Pranav Ashar	Toward Formalizing a Validation Methodology Using Simulation Coverage.	DAC	1997	DBLP DOI BibTeX RDF
16	Tzer-Shyong Chen, Feipei Lai, Rung-Ji Shang	A Simple Tree Pattern Matching Algorithm for Code Generator.	COMPSAC	1995	DBLP DOI BibTeX RDF	Intermediate code, Compiler, Code generator, Instruction set, Tree pattern matching
16	Jerry R. Burch, David L. Dill	Automatic verification of Pipelined Microprocessor Control.	CAV	1994	DBLP DOI BibTeX RDF
16	Sofiène Tahar, Ramayya Kumar	Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL.	TPHOLs	1994	DBLP DOI BibTeX RDF
16	Barry S. Fagin	Quantitative measurements of FPGA utility in special and general purpose processors.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF