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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 56 occurrences of 55 keywords
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Results
Found 68 publication records. Showing 68 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
111 | Manish Amde, Ivan Blunno, Christos P. Sotiriou |
Automating the design of an asynchronous DLX microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 502-507, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DLX, asynchronous, design flow |
96 | Milos Becvár, Stanislav Kahánek |
VLIW-DLX simulator for educational purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2007 Workshop on Computer Architecture Education, WCAE 2007, San Diego, California, USA, Saturday, June 9, 2007, pp. 8-13, 2007, ACM, 978-1-59593-797-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
simulation, education, computer architecture, VLIW |
64 | Joseph A. Driscoll, Ralph M. Butler, Joelle M. Key |
A virtual machine environment for teaching the development of system software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 42nd Annual Southeast Regional Conference, 2004, Huntsville, Alabama, USA, April 2-3, 2004, pp. 440-441, 2004, ACM, 1-58113-870-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DLX, education, GUI, virtual machine, system software |
63 | Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, Jestoni V. Zarsuela, Anastacia P. Ballesil, Joy Alinda Reyes |
DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 466-469, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
48 | Krishnamani Kalyanasundaram, R. K. Shyamasundar |
Formal verification of pipelined processors with precise exceptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 23-25 June 2004, San Diego, California, USA, Proceedings, pp. 129-139, 2004, IEEE Computer Society, 0-7803-8509-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Hemangee K. Kapoor |
Formal Modelling and Verification of an Asynchronous DLX Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM 2006), 11-15 September 2006, Pune, India, pp. 118-127, 2006, IEEE Computer Society, 0-7695-2678-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Roland N. Ibbett |
HASE DLX Simulation Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(3), pp. 57-65, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti 0001, Vivekananda M. Vedula |
Power Virus Generation Using Behavioral Models of Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 35-42, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models |
32 | Miroslav N. Velev |
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings, pp. 97-113, 2005, Springer, 3-540-29105-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin |
A Simulation Methodology for Software Energy Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 509-510, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Nyoman Bogi Aditya Karna, Nimas Fatihah, Dong-Seong Kim 0002 |
Evaluation of DLX Microprocessor Instructions Efficiency for Image Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTC ![In: 2019 International Conference on Information and Communication Technology Convergence, ICTC 2019, Jeju Island, Korea (South), October 16-18, 2019, pp. 612-616, 2019, IEEE, 978-1-7281-0893-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
31 | Sujoy Pandit, Prateek Sikka |
Design and Implementation of Power Optimized Dual Core and Single Core DLX Processor on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 9th International Conference on Computing, Communication and Networking Technologies, ICCCNT 2018, Bengaluru, India, July 10-12, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-4430-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
31 | Rajesh Kannan Megalingam, Shekhil Hassan Thavalengal, Tanmay Muralidhar Rao, Ashwin Mohan, Vivek Periye |
Low power analysis of DLX processor datapath using a novel clocking scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26 - 27, 2010, pp. 874-879, 2010, ACM, 978-1-60558-812-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
31 | Roger Luis Uy, Marizel Bernardo, Josiel Erica |
DARC2: 2nd generation DLX architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE ![In: Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004, pp. 20, 2004, ACM, 978-1-4503-4733-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Elham Khorsandi Nia, Omid Fatemi |
Multimedia extensions for DLX processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003, pp. 1010-1013, 2003, IEEE, 0-7803-8163-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Chung-Ho Chen, Akida Wu |
An enhanced DLX-based superscalar system simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1997 workshop on Computer architecture education, WCAE@HPCA 1997, San Antonio, Texas, USA, February 1997, pp. 5, 1997, ACM, 978-1-4503-4739-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Yinong Zhang, George B. Adams III |
An interactive, visual simulator for the DLX pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@HPCA ![In: Proceedings of the 1997 workshop on Computer architecture education, WCAE@HPCA 1997, San Antonio, Texas, USA, February 1997, pp. 2, 1997, ACM, 978-1-4503-4739-6. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Philip M. Sailor, David R. Kaeli |
The DLX instruction set architecture handbook. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
31 | Robert Knuth |
Quantitative Analyse von DLX-Pipeline-Architekturen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1996 |
RDF |
|
31 | Valentín Valero Ruiz, Fernando Cuartero, Antonio Jose Garrido del Solo, Francisco J. Quiles 0001 |
A simulation tool of parallel architectures for digital image processing applications based on DLX processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 448-451, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Barry S. Fagin, Pichet Chintrakulchai |
Prototyping the DLX microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: Proceedings of the Third International Workshop on Rapid System Prototyping, RSP 1992, Research Triangle Park, North Carolina, USA, June 23-15, 1992, pp. 127-137, 1992, IEEE Computer Society, 0-8186-3520-7. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Herbert Grünbacher, Maziar Khosravipour |
WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 412-, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
teaching computer architecture, teaching computer organisation, teaching pipelining, DLX architecture, pipeline visualisation, WinDLX, MIPSim, ECBS |
16 | Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo |
Enhancing bug hunting using high-level symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 417-420, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
bughunter, design for verification, symbolic simulation |
16 | Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil |
Automatic Constraint Based Test Generation for Behavioral HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 408-421, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Viswanathan Subramanian, Arun K. Somani |
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 14th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2008, 15-17 December 2008, Taipei, Taiwan, pp. 9-16, 2008, IEEE Computer Society, 978-0-7695-3448-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 379-384, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
16 | Ernesto Sánchez 0001, Giovanni Squillero |
Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Advances in Evolutionary Computing for System Design ![In: Advances in Evolutionary Computing for System Design, pp. 303-326, 2007, Springer, 978-3-540-72376-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Edward K. Walters II, J. Eliot B. Moss, Trek S. Palmer, Timothy Richards, Charles C. Weems |
Modeling Modern Micro-architectures using CASL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-6, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar |
Module assignment for pin-limited designs under the stacked-Vdd paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 656-659, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy 0001 |
Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 74-79, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
elastic clocking, process tolerant, low power |
16 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(11), pp. 1203-1215, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou |
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 1904-1921, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Sven Beyer, Christian Jacobi 0002, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul |
Putting it all together - Formal verification of the VAMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(4-5), pp. 411-430, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Complete microprocessor verification, Tomasulo scheduler, Cache memory interface, Model checking, Formal methods, Theorem proving, Floating point unit |
16 | Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer |
An Experimental Study of Soft Errors in Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 25(6), pp. 30-39, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture |
16 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner |
XFM: An incremental methodology for developing formal models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 589-609, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Extreme formal modeling, prescriptive formal models, property ordering, property refactoring, formal specification, formal verification, extreme programming, SPIN, SMV |
16 | Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June - 1 July 2005, Yokohama, Japan, Proceedings, pp. 760-769, 2005, IEEE Computer Society, 0-7695-2282-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Tun Li, Dan Zhu, Yang Guo 0003, GongJie Liu, Sikun Li |
MA2TG: A Functional Test Program Generator for Microprocessor Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 176-183, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Tun Li, Dan Zhu, Lei Liang, Yang Guo 0003, Sikun Li |
Automatic functional test program generation for microprocessor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1039-1042, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Seokkee Kim, Soo-Ik Chae |
Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005, pp. 421-426, 2005, ACM, 1-59593-019-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor |
16 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-based delay fault self-testing of pipelined processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5686-5689, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Dirk Leinenbach, Wolfgang J. Paul, Elena Petrova |
Towards the Formal Verification of a C0 Compiler: Code Generation and Implementation Correctnes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEFM ![In: Third IEEE International Conference on Software Engineering and Formal Methods (SEFM 2005), 7-9 September 2005, Koblenz, Germany, pp. 2-12, 2005, IEEE Computer Society, 0-7695-2435-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Fulvio Corno, Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero |
Code Generation for Functional Validation of Pipelined Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 269-278, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pipelined micro processors, evolutionary algorithms, functional validation, automatic test program generation |
16 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner |
Extreme Formal Modeling (XFM) for Hardware Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 30-35, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai |
Functional Verification of Pipelined Processors: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 79-84, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Sonia López, Oscar Garnica, José Manuel Colmenar |
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 623-632, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Prabhat Mishra 0001, Nikil D. Dutt |
Graph-Based Functional Test Program Generation for Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 182-187, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou |
Handshake Protocols for De-Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 149-158, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 731-737, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Prabhat Mishra 0001, Nikil D. Dutt |
A Methodology for Validation of Microprocessors using Equivalence Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA, pp. 83-88, 2003, IEEE Computer Society, 0-7695-2045-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Sven Beyer, Christian Jacobi 0002, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul |
Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings, pp. 51-65, 2003, Springer, 3-540-20363-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Miroslav N. Velev |
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 138-147, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Oswaldo Cadenas, Graham M. Megson |
Pullpipelining: A technique for systolic pipelined circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 205-210, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama |
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 36-43, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Sumit Ghosh |
P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(1), pp. 28-50, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics |
16 | Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai |
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 649-654, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick |
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 13-27, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
architectural verification, biased random instruction generation, correctness checking, design error coverage, design verification, coverage metrics |
16 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng |
Functionally Testable Path Delay Faults on a Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 17(4), pp. 6-14, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
16 | S. Ramesh 0001, Purandar Bhaduri |
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings, pp. 84-95, 1999, Springer, 3-540-66202-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Peter Grun, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999., pp. 44-50, 1999, ACM / IEEE Computer Society, 0-7695-0356-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Asheesh Khare, Nicolae Savoiu, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau |
V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1196-1203, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Ravi Hosabettu, Mandayam K. Srivas, Ganesh Gopalakrishnan |
Decomposing the Proof of Correctness of pipelined Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings, pp. 122-134, 1998, Springer, 3-540-64608-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
16 | John Matthews, Byron Cook, John Launchbury |
Microprocessor Specification in Hawk. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: Proceedings of the 1998 International Conference on Computer Languages, ICCL 1998, Chicago, IL, USA, May 14-16, 1998, pp. 90-101, 1998, IEEE Computer Society, 0-8186-8454-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Microprocessor Verification, Domain-Specific Language, Functional Language, Hardware Verification |
16 | Aarti Gupta, Sharad Malik, Pranav Ashar |
Toward Formalizing a Validation Methodology Using Simulation Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 740-745, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Tzer-Shyong Chen, Feipei Lai, Rung-Ji Shang |
A Simple Tree Pattern Matching Algorithm for Code Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 19th International Computer Software and Applications Conference (COMPSAC'95), August 9-11, 1995, Dallas, Texas, USA, pp. 162-167, 1995, IEEE Computer Society, 0-8186-7119-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Intermediate code, Compiler, Code generator, Instruction set, Tree pattern matching |
16 | Jerry R. Burch, David L. Dill |
Automatic verification of Pipelined Microprocessor Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 6th International Conference, CAV '94, Stanford, California, USA, June 21-23, 1994, Proceedings, pp. 68-80, 1994, Springer, 3-540-58179-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Sofiène Tahar, Ramayya Kumar |
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and Its Applications, 7th International Workshop, Valletta, Malta, September 19-22, 1994, Proceedings, pp. 424-439, 1994, Springer, 3-540-58450-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Barry S. Fagin |
Quantitative measurements of FPGA utility in special and general purpose processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 6(2), pp. 129-137, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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