Search results for "DMA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
136	Evangelos P. Markatos, Manolis Katevenis	User-Level DMA without Operating System Kernel Modification.	HPCA	1997	DBLP DOI BibTeX RDF
121	Christian Zinner, Wilfried Kubinger	ROS-DMA: A DMA Double Buffering Method for Embedded Image Processing with Resource Optimized Slicing.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
110	Ben-Ami Yassour, Muli Ben-Yehuda, Orit Wasserman	On the DMA mapping problem in direct device assignment.	SYSTOR	2010	DBLP DOI BibTeX RDF	DMA mapping, I/O virtualization, IOMMU, IOMMU protection strategies, SR-IOV, device assignment, direct access, on-demand mapping
96	Matthias A. Blumrich, Cezary Dubnicki, Edward W. Felten, Kai Li 0001	Protected, User-Level DMA for the SHRIMP Network Interface.	HPCA	1996	DBLP DOI BibTeX RDF	SHRIMP network interface, User-level Direct Memory Access, DMA transfers, permission checking, virtual memory translation, operating system, computer networks, file organisation, network interfaces, DMA, address translation, computer interfaces
90	Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto	Lightweight DMA management mechanisms for multiprocessors on FPGA.	ASAP	2008	DBLP DOI BibTeX RDF
83	Tai-Yi Huang, Jane W.-S. Liu, David Hull	A Method for Bounding the Effect of DMA I/O Interference on Program Execution Time.	RTSS	1996	DBLP DOI BibTeX RDF	DMA I/O operation, program execution time, DMA controller, cycle-stealing mode, bus cycles, cycle stealing operation, executing program, machine instruction, instruction-cache architectures, input output operation, simulations, real-time systems, worst-case execution time, data transfer
80	Francesca Palumbo, Danilo Pani, Alessandro Pilia, Luigi Raffo	Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance.	NOCS	2010	DBLP DOI BibTeX RDF	full-duplex DMA, half-duplex DMA, hybrid switching NoC, DMA performance bias, deadlock prevention
78	Vivek Pandey, Weihang Jiang, Yuanyuan Zhou 0001, Ricardo Bianchini	DMA-aware memory energy management.	HPCA	2006	DBLP DOI BibTeX RDF
78	Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioannis Nousias, Iain Lindsay	An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF
78	Andrea Santoro, Francesco Quaglia	PCI-DMA/CPU Handoff for Increased Effectiveness of Checkpointing Functionalities in CCL.	DS-RT	2003	DBLP DOI BibTeX RDF
70	Tao Liu, Haibo Lin, Tong Chen 0001, Kevin O'Brien, Ling Shao 0002	DBDB: optimizing DMATransfer for the cell be architecture.	ICS	2009	DBLP DOI BibTeX RDF	loop blocking, local memory, multi-core system
70	Alexander A. Hagin, Gabriel Dermler, Kurt Rothermel, Gennadij Shchemelev	Distributed Multimedia Application Configuration Management.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	configuration management, assignment, resource reservation, Distributed multimedia application, QoS negotiation
66	Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch	An Enhanced DMA Controller in SIMD Processors for Video Applications.	ARCS	2009	DBLP DOI BibTeX RDF
66	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Speculative DMA for architecturally visible storage in instruction set extensions.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	architecturally visible storage, speculative direct memory access, instruction set extensions, application-specific processors
66	Tai-Yi Huang, Chih-Chieh Chou, Po-Yuan Chen	Bounding the Execution Times of DMA I/O Tasks on Hard-Real-Time Embedded Systems.	RTCSA	2003	DBLP DOI BibTeX RDF
56	Francesco Quaglia, Andrea Santoro	Modeling and optimization of non-blocking checkpointing for optimistic simulation on myrinet clusters.	ICS	2003	DBLP DOI BibTeX RDF	checkpointing, performance optimization, DMA, optimistic simulation
55	Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	Enhancing the Performance of Tiled Loop Execution onto Clusters Using Memory Mapped Network Interfaces and Pipelined Schedules.	IPDPS	2002	DBLP DOI BibTeX RDF	Memory Mapped Interfaces, Zero-Copy Protocols, DMA transfers, Loop Tiling, Communication Overlapping
55	Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell	An optimization method of DMA transfer for a general purpose reconfigurable machine.	FPL	2008	DBLP DOI BibTeX RDF
46	Tong Zhao, Yueming Lu, Yuefeng Ji	Least Interference Optimization Based Dynamic Multi-path Routing Algorithm in ASON.	APNOMS	2008	DBLP DOI BibTeX RDF	routing, load balance, interference, ASON
46	Francesco Quaglia, Andrea Santoro, Bruno Ciciani	Tuning of the Checkpointing and Communication Library for Optimistic Simulation on Myrinet Based NOWs.	MASCOTS	2001	DBLP DOI BibTeX RDF
43	Vaibhav Saxena, Prashant Agrawal, Yogish Sabharwal, Vijay K. Garg, Vimitha A. Kuruvilla, John A. Gunnels	Optimization of BLAS on the Cell Processor.	HiPC	2008	DBLP DOI BibTeX RDF	Direct Memory Access (DMA), multi-core, linear algebra, BLAS, Cell processor
43	Daniel Jiménez-González, Xavier Martorell, Alex Ramírez	Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	arithmetic performance analysis, memory bandwidth application, synergistic processor element, DMA controller, direct memory access, element interconnect bus, bandwidth performance peak, processor component, message passing interface, data stream, single instruction multiple data, cell broadband engine, streaming programming model, processor speed
43	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, partial reconfiguration
43	Tong Chen 0001, Zehra Sura, Kathryn M. O'Brien, John K. O'Brien	Optimizing the Use of Static Buffers for DMA on a CELL Chip.	LCPC	2006	DBLP DOI BibTeX RDF
43	Mattias O'Nils, Axel Jantsch	Synthesis of DMA Controllers from Architecture Independent Descriptions of HW/SW Communication Protocols.	VLSI Design	1999	DBLP DOI BibTeX RDF
41	Wen Su, Ling Wang, Menghao Su, Su Liu	A Processor-DMA-Based Memory Copy Hardware Accelerator.	NAS	2011	DBLP DOI BibTeX RDF	memory copy, accelerator, processor, DMA
40	Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Seon Wook Kim	PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA.	IEEE Access	2023	DBLP DOI BibTeX RDF
40	Jan Kubálek, Jakub Cabal, Martin Spinler, Radek Isa	DMA Medusa: A Vendor-Independent FPGA-Based Architecture for 400 Gbps DMA Transfers.	FCCM	2021	DBLP DOI BibTeX RDF
40	Jinbin Zhu, Limin Xiao, Liang Wang 0020, Guangjun Qin, Rui Zhang, Yuting Liu, Zhonglin Liu	UPM-DMA: An Efficient Userspace DMA-Pinned Memory Management Strategy for NVMe SSDs.	ICA3PP (1)	2021	DBLP DOI BibTeX RDF
40	Sheng Ma, Yuanwu Lei, Libo Huang, Zhiying Wang 0003	MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing.	IEEE Access	2019	DBLP DOI BibTeX RDF
40	Nikola Vujic, Lluc Alvarez, Marc González 0001, Xavier Martorell, Eduard Ayguadé	DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
40	Carsten F. Ball, Kolio Ivanov, Robert Müllner, Hubert Winkler	SI2R-DMA: self-organizing inter- and intra-site interference reduction DMA for GERAN networks.	PIMRC	2004	DBLP DOI BibTeX RDF
35	Thomas Fischer 0003, Kerstin Bauer, Peter Merz	Solving the routing and wavelength assignment problem with a multilevel distributed memetic algorithm.	Memetic Comput.	2009	DBLP DOI BibTeX RDF	Routing and wavelength assignment problem, Multilevel approach, Memetic algorithms, Iterated local search
35	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
35	Michael Gschwind	Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor.	ICCD	2008	DBLP DOI BibTeX RDF
35	Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris	Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.	PATMOS	2007	DBLP DOI BibTeX RDF
35	Amitava Biswas, Purnendu Sinha	On improving performance of Network Intrusion Detection Systems by efficient packet capturing.	NOMS	2006	DBLP DOI BibTeX RDF
35	Zheng Wan	An Efficient Dynamic Multicast Protocol for Mobile IPv6 Networks.	LCN	2006	DBLP DOI BibTeX RDF
35	Kuan Jen Lin, Chuang Hsiang Huang, Cheng Chia Lo	Design and Implementation of a Schedulable DMAC on an AMBA-Based SOPC Platform.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Francesco Quaglia, Andrea Santoro	CCL v3.0: Multiprogrammed Semi-Asynchronous Checkpoints.	PADS	2003	DBLP DOI BibTeX RDF
35	Tai-Yi Huang, Jane W.-S. Liu, Jen-Yao Chung	Allowing cycle-stealing direct memory access I/O concurrent with hard-real-time programs.	ICPADS	1996	DBLP DOI BibTeX RDF	cycle-stealing direct memory access, I/O concurrent, hard-real-time programs, bus cycles, straight-line sequence, cycle-stealing operations, real-time systems, fault tolerant computing, worst-case execution time, schedulability analysis, file organisation
35	David A. Hartley, David M. Harvey	Analysis of the TMS320C40 Communication Channels Using Timed Petri Nets.	Application and Theory of Petri Nets	1993	DBLP DOI BibTeX RDF
33	Ahsan Shabbir, Sander Stuijk, Akash Kumar 0001, Bart D. Theelen, Bart Mesman, Henk Corporaal	A predictable communication assist.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	fpga's, communication, predictable, dma, ca, mp-soc
33	Tong Chen 0001, Tao Zhang, Zehra Sura, Marc González Tallada	Prefetching irregular references for software cache on cell.	CGO	2008	DBLP DOI BibTeX RDF	prefetch, DMA, software cache
33	Mountassar Maamoun, Boualem Laichi, Abdelhalim Benbelkacem, Daoud Berkani	Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing.	IWSOC	2004	DBLP DOI BibTeX RDF	Software/Hardware system, Advanced Physical Addressing, memory integration, Interfacing, DMA
33	Mountassar Maamoun, Abdelhalim Benbelkacem, Daoud Berkani, Abderrezak Guessoum	Interfacing in Microprocessor-based Systems with a Fast Physical Addressing.	IWSOC	2003	DBLP DOI BibTeX RDF	Software/hardware System, Fast Physical Addressing, Interfacing, DMA
33	Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	Pipelined scheduling of tiled nested loops onto clusters of SMPs using memory mapped network interfaces.	SC	2002	DBLP DOI BibTeX RDF	memory mapped network interfaces, tile grouping, SMPs, DMA, pipelined schedules, communication overlapping
33	Jiun-Ming Hsu, Prithviraj Banerjee	Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	parallel CAD, realistic workloads, time interval distributions, statistical functions, nonlinear regression technique, message destinations, trace-drive simulation environment, performance evaluation, performance evaluation, parallel programs, parallel programming, benchmarks, statistical analysis, hypercube networks, digital simulation, workload characterization, execution traces, temporal locality, spatial locality, hypercube multicomputer, software monitoring, DMA, message length, link utilizations
32	Sufian Sudeng, Arthit Thongtak	Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	asynchronous control circuits, asynchronous DMA controller, template based technique, logic synthesis, Signal Transition Graph (STG)
32	Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda	QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	PD77210, successive similarity detection algorithm (SSDA), DMA queue, low power, motion estimation, DSP, MPEG-4, computational cost
32	Ken Yocum, Jeffrey S. Chase, Andrew J. Gallatin, Alvin R. Lebeck	Cut-Through Delivery in Trapeze: An Exercise in Low-Latency Messaging.	HPDC	1997	DBLP DOI BibTeX RDF	message switching, cut-through delivery, low-latency messaging, I/O bus bandwidths, host I/O DMA transfers, network traversal, messaging substrate, network memory, Trapeze prototype, virtual memory pages, Myrinet cluster, DEC AlphaStations, network interfaces, computer clusters, network technology, application performance, messaging systems
32	Chiung-San Lee, Tai-Ming Parng	A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	Bottleneck analysis, DMA transfer, separated address bus and data bus, shared-bus multiprocessor system, subsystem access time modeling, subsystem interferences, performance analysis
32	Eric M. Dowling, Zuqiang Fu, Ron S. Drafz	HARP: An Open Architecture for Parallel Matrix and Signal Processing.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	HARP, matrix processing, Hybrid Array RingProcessor, memory mapped processing cells, open backplane, bidirectional systolic ring, bus controller, DMA function, systolic communication, reduced overhead message passing, digital signalprocessor, systolicarray, parallel algorithms, parallel, parallel architectures, multiprocessor, shared memory, signal processing, signal processing, systolic arrays, shared memory systems, interprocessor communication, open architecture, Application specific architecture
31	Latchesar Ionkov, Aki Nyrhinen, Andrey Mirtchovski	CellFS: Taking the "DMA" out of Cell programming.	IPDPS	2009	DBLP DOI BibTeX RDF
31	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic	Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture.	IPDPS	2009	DBLP DOI BibTeX RDF
31	Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi	A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.	FPL	2008	DBLP DOI BibTeX RDF
31	Christof Pitter, Martin Schoeberl	Time Predictable CPU and DMA Shared Memory Access.	FPL	2007	DBLP DOI BibTeX RDF
31	Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Adonios Thanailakis	A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Zhan Shi, Jiangling Zhang, Xinrong Zhou	Using DMA Aligned Buffer to Improve Software RAID Performance.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
31	Christian Bell, Dan Bonachea	A New DMA Registration Strategy for Pinning-Based High Performance Networks.	IPDPS	2003	DBLP DOI BibTeX RDF
31	Dave Comisky, Sanjive Agarwala, Charles Fuoco	A Scalable High-Performance DMA Architecture for DSP Applications.	ICCD	2000	DBLP DOI BibTeX RDF
23	Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
23	Xuejun Sha, Rong-hui Wen, Xin Qiu	A new multiple-access method based on Fractional Fourier Transform.	CCECE	2009	DBLP DOI BibTeX RDF
23	Chih-Lun Fang, Tsung-Han Tsai 0001, Ren-Chih Kuo	Design and Implementation of a Videotext Extractor on Dual-Core Platform.	APSCC	2008	DBLP DOI BibTeX RDF
23	Roberto Jung Drebes, Takashi Nanya	Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors.	PRDC	2008	DBLP DOI BibTeX RDF
23	Kevin O'Brien, Kathryn M. O'Brien, Zehra Sura, Tong Chen 0001, Tao Zhang	Supporting OpenMP on Cell.	IWOMP	2007	DBLP DOI BibTeX RDF
23	Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.	FPL	2007	DBLP DOI BibTeX RDF
23	Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang	A probabilistic analysis of pipelined global interconnect under process variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
23	Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, Brad Calder	Automatic logging of operating system effects to guide application-level architecture simulation.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	emulating system calls, checkpoints, architecture simulation
23	Qian Wu, Jianping Wu, Mingwei Xu, Yong Cui 0001, Hui Deng	An Agent-Based Scheme for Efficient Multicast Application in Mobile Networks.	ISCIS	2005	DBLP DOI BibTeX RDF
23	Giuseppe Ciaccio	Using a Self-connected Gigabit Ethernet Adapter as a memcpy() Low-Overhead Engine for MPI.	PVM/MPI	2003	DBLP DOI BibTeX RDF
23	Sumesh Udayakumaran, Rajeev Barua	Compiler-decided dynamic memory allocation for scratch-pad based embedded systems.	CASES	2003	DBLP DOI BibTeX RDF	embedded systems, compiler, memory allocation, scratch-pad
23	Khaled Salah 0001, K. El-Badawi	Evaluating System Performance in Gigabit Networks.	LCN	2003	DBLP DOI BibTeX RDF
23	Francesco Quaglia, Andrea Santoro, Bruno Ciciani	Conditional checkpoint abort: an alternative semantic for re-synchronization in CCL.	PADS	2002	DBLP DOI BibTeX RDF	Rollback Based Synchronization, Checkpointing, Performance Optimization, Optimistic Simulation
23	Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	Efficient Utilization of Memory Mapped NICs onto Clusters using Pipelined Schedules.	CCGRID	2002	DBLP DOI BibTeX RDF
23	Sidney Cadot, Frits Kuijlman, Koen Langendoen, Kees van Reeuwijk, Henk J. Sips	ENSEMBLE: A Communication Layer for Embedded Multi-Processor Systems.	LCTES/OM	2001	DBLP DOI BibTeX RDF
23	Adam Smyk, Marek Tudruj	Inter-Process Communication for Parallel Computations of Wavelet Transforms on Hitachi SR2201 Supercomputer.	PARELEC	2000	DBLP DOI BibTeX RDF
21	David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic	On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	embedded systems, real-time, hardware acceleration, virtual prototyping, hardware/software co-design, LTE, DMA
21	Xiandong Meng, Vipin Chaudhary	An adaptive data prefetching scheme for biosequence database search on reconfigurable platforms.	SAC	2007	DBLP DOI BibTeX RDF	FPGA, data prefetching, DMA, Smith-Waterman algorithm
21	Satish Narayanasamy, Gilles Pokam, Brad Calder	BugNet: Recording Application-Level Execution for Deterministic Replay Debugging.	IEEE Micro	2006	DBLP DOI BibTeX RDF	BugNet, debugging, DMA
21	Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias	An integrated hardware/software approach for run-time scratchpad management.	DAC	2004	DBLP DOI BibTeX RDF	AMBA AHB, scratchpad, DMA, dynamic allocation
21	Francesco Quaglia, Andrea Santoro	Nonblocking Checkpointing for Optimistic Parallel Simulation: Description and an Implementation.	IEEE Trans. Parallel Distributed Syst.	2003	DBLP DOI BibTeX RDF	checkpointing, performance optimization, Parallel discrete-event simulation, myrinet, DMA, optimistic synchronization
20	J. Lakshmi, S. K. Nandy 0001	I/O Virtualization Architecture for Security.	CIT	2010	DBLP DOI BibTeX RDF	I/O virtualization, unconstrained DMA, security threats, denial of service attack
20	Takahiro Shinagawa, Hideki Eiraku, Kouichi Tanimoto, Kazumasa Omote, Shoichi Hasegawa, Takashi Horie, Manabu Hirano, Kenichi Kourai, Yoshihiro Oyama, Eiji Kawai, Kenji Kono, Shigeru Chiba, Yasushi Shinjo, Kazuhiko Kato	BitVisor: a thin hypervisor for enforcing i/o device security.	VEE	2009	DBLP DOI BibTeX RDF	parapass-through, shadow dma descriptor, virtual machine monitors, hypervisors, trusted computing base
20	Yufeng Guo, Qiong Li, Guangming Liu, Yusheng Cao, Lei Zhang	A Distributed Shared Parallel IO System for HPC.	ITNG	2008	DBLP DOI BibTeX RDF	Distributed Shared IO system, Remote DMA, Parallel filesystem, HPC
20	Manolis Marazakis, Konstantinos Xinidis, Vassilis Papaefstathiou, Angelos Bilas	Efficient remote block-level I/O over an RDMA-capable NIC.	ICS	2006	DBLP DOI BibTeX RDF	block-level I/O, remote DMA, performance evaluation, networked storage
20	Adam Smyk, Marek Tudruj	Program Implementation Based on Macro Data Flow Paradigm with RDMA Communication Support.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	Macro Data Flow analysis, Remote DMA, MPI, FDTD
20	M. Esen Tuna, Kamlesh Rath, Steven D. Johnson	Specification and synthesis of bounded indirection.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	bounded indirection, complex control structures, dynamic connections, control state indirection, value indirection, net indirection, behavior tables, data path descriptions, DMA controller, formal specification, high level synthesis, finite state machines, interrupts, interrupts, continuations, hardware description languages, hardware description languages, pointers, system specification, data flow computing, control system CAD
20	Chao Pei	DMA-SGCN for Video Motion Recognition: A Tool for Advanced Sports Analysis.	IEEE Access	2024	DBLP DOI BibTeX RDF
20	Kelin Huang, Li You, Mengyu Qian, Xiqi Gao 0001	MetaSWIPT: DMA-Assisted Multi-User MISO Downlink Simultaneous Wireless Information and Power Transfer.	IEEE Wirel. Commun. Lett.	2024	DBLP DOI BibTeX RDF
20	Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini	A High-Performance, Energy-Efficient Modular DMA Engine Architecture.	IEEE Trans. Computers	2024	DBLP DOI BibTeX RDF
20	Dingding Li, Weijie Zhang, Mianxiong Dong, Kaoru Ota	DMA-Assisted I/O for Persistent Memory.	IEEE Trans. Parallel Distributed Syst.	2024	DBLP DOI BibTeX RDF
20	Zheng Zhang, Yuanwei Liu, Zhaolin Wang, Jian Chen, Dong In Kim	Near Field Communications for DMA-NOMA Networks.	CoRR	2024	DBLP DOI BibTeX RDF
20	Zhenyu Cui, Jiahuan Zhou, Yuxin Peng	DMA: Dual Modality-Aware Alignment for Visible-Infrared Person Re-Identification.	IEEE Trans. Inf. Forensics Secur.	2024	DBLP DOI BibTeX RDF
20	Niklas Schelten, Fritjof Steinert, Justin Knapheide, Anton Schulte, Benno Stabernack	A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application.	ACM Trans. Reconfigurable Technol. Syst.	2023	DBLP DOI BibTeX RDF
20	Jibi G. Thanikkal, Ashwani Kumar Dubey, Thomas M. T.	Deep - Morpho Algorithm (DMA) for medicinal leaves features extraction.	Multim. Tools Appl.	2023	DBLP DOI BibTeX RDF
20	Paolo Pazzaglia, Daniel Casini, Alessandro Biondi 0001, Marco Di Natale	Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
20	Kaizhi Huang, Wenyu Jiang, Yajun Chen, Liang Jin, Qingqing Wu, Xiaoling Hu	Robust Anti-jamming Communications with DMA-Based Reconfigurable Heterogeneous Array.	CoRR	2023	DBLP DOI BibTeX RDF
20	Diaeddin Rimawi, Antonio Liotta, Marco Todescato, Barbara Russo	CAIS-DMA: A Decision-Making Assistant for Collaborative AI Systems.	CoRR	2023	DBLP DOI BibTeX RDF
20	Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini	A High-performance, Energy-efficient Modular DMA Engine Architecture.	CoRR	2023	DBLP DOI BibTeX RDF